13769 results about "Semiconductor package" patented technology

The present invention comprises a semiconductor package comprising a bottom semiconductor package substrate which is populated with one or more electronic components. The electronic component(s) of the bottom substrate are covered or encapsulated with a suitable mold compound which hardens into a package body of the semiconductor package. The package body is provided with one or more vias through the completion of laser drilling process, such via(s) providing access to one or more corresponding conductive contacts of the bottom substrate. These vias are either lined or partially filled with a conductive metal material. Subsequently, a top semiconductor package substrate (which may optionally be populated with one or more electronic components) is mounted to the package body and electrically connected to the conductive metal within the via(s) of the package body.

A thin-film transistor array comprises at least first and second transistors. Each transistor comprises a source electrode, a drain electrode a semiconductor electrode, a gate electrode, and a semiconductor layer. The semiconductor layer is continuous between the first and second transistors. The semiconductor layer is preferably unpatterned. In various display applications, the geometry of the transistors is selected to provide acceptable leakage currents. In a preferred embodiment, the transistor array is employed in an encapsulated electrophoretic display.

A method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is then mounted on the interposer.

A stack type semiconductor package, and a method of fabricating the same are provided. The stack type semiconductor package may include a lower unit package and an upper unit package. The lower unit package may include a substrate, and a semiconductor chip on an upper surface of the substrate. A bump may be on an upper surface of the substrate, and a protecting layer, covering the semiconductor chip, may be formed. The protecting layer may include a via hole partially exposing the bump. The upper unit package may be on the protecting layer, and may include an internal connection solder ball on a lower surface of the upper unit package. The internal connection solder ball may be inserted into the via hole and connected to the bump.

A method of making a microelectronic package includes providing a sacrificial layer having a first surface and providing an optoelectronic element having a front face including one or more contacts and a rear surface and securing the rear surface of the optoelectronic element over the first surface of the sacrificial layer. The one or more contacts are then electrically interconnected with one or more conductive pads on the sacrificial layer and a curable and at least partially transparent encapsulant is provided over the first surface of the sacrificial layer so as to encapsulate the optoelectronic element and the conductive pads. The encapsulant is then cured the sacrificial layer is at least partially removed so as to leave said one or more conductive pads on a bottom surface of the encapsulant, the bottom surface of the encapsulant defining the bottom of the package. The optoelectronic element may include a light sensitive chip such as an ultraviolet-erasable programmable read-only memory (UV EPROM) or a light emitting chip, such as a light emitting diode (LED).

A semiconductor package of this invention has an insulating substrates, wiring layers disposed on the surface of the insulating substrate, a semiconductor chip disposed in a device hole provided in the insulating substrate, inner-joint-conductors for connecting at least part of the bonding pads on the surface of the semiconductor chip to the corresponding inner-joint-conductors and connection lands connected to the wiring layers. The device hole is provided so that it goes through the center of the insulating substrate. The semiconductor chip is thinner than the insulating substrate. Then, this semiconductor chip is disposed in the device hole such that a bottom thereof is flush with a bottom plane of the insulating substrate. Further, this invention provides a MCM in which plural pieces of the thin semiconductor packages are laminated. In the MCM, the semiconductor packages are laminated such that top and bottom faces of the thin silicon chip are inverted. Predetermined connection lands are electrically connected to each other through a connecting conductor. This MCM has a high mechanical strength in its stacked structure and there is a low possibility that crack may occur in the package due to stress in the bending direction.

To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, a channel protective layer is provided in a region that overlaps a channel formation region of the semiconductor layer, and a buffer layer is provided between the semiconductor layer and source and drain electrodes. An ohmic contact is formed by intentionally providing the buffer layer having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrodes.

A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.

The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted.

The invention provides a semiconductor device capable of suppressing a short channel effect and fluctuation in a threshold. The semiconductor device includes: a plurality of first transistors formed in a first region in a semiconductor layer in a multilayer substrate having, on a semiconductor substrate, an insulating layer and the semiconductor layer in order from the semiconductor substrate; a plurality of second transistors formed in a second region in the semiconductor layer; a first impurity layer formed in a region opposed to the first region in the semiconductor substrate; a second impurity layer formed in a region opposed to the second region in the semiconductor substrate; and a first isolation part that isolates the first and second regions from each other and electrically isolates the first and second impurity layers from each other to a degree that at least current flowing between the first and second impurity layers is interrupted.

A packaging method comprises: forming a circuit board by forming a substantially continuous conductive layer on an insulating board and removing selected portions of the continuous conductive layer to define an electrically conductive trace; laser cutting the electrically conductive trace to define sub-traces electrically isolated from each other by a laser-cut gap formed by the laser cutting; and bonding a light emitting diode (LED) chip to the circuit board across or adjacent to the laser-cut gap, the bonding including operatively electrically connecting an electrode of the LED chip to one of the sub-traces without using an interposed submount. A semiconductor package comprises an LED chip flip-chip bonded to sub-traces of an electrically conductive trace of a circuit board, the sub-traces being electrically isolated from each other by a narrow gap of less than or about 100 microns.

A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. A through buried oxide via connects the chip(s) to the integrated circuit system.

The present disclosure relates to a semiconductor device package which includes a carrier, an electronic component, conductive elements, a package body, a shield, a magnetic insulating layer, and a patterned conductive layer. The carrier has a top surface on which the electronic component is disposed. The conductive elements are disposed on the top surface of the carrier. The package body is disposed on the top surface of the carrier and encapsulates the electronic component and a portion of each of the conductive elements. The shield is disposed on the package body and covers an exterior of the package body. The magnetic insulating layer is disposed on a top surface of the shield. The patterned conductive layer is disposed on the magnetic insulating layer. Each of the conductive elements electrically connects the patterned conductive layer to the electronic component.

A semiconductor laser device have, on a substrate, a semiconductor layer including an active layer sandwiched between an n-type layer and a p-type layer, the semiconductor layer having a sonator face formed by etching and a projection projecting out in an emission direction relatively to the resonator face, wherein a protective film is formed to extend from the resonator face to an end face of the projection, and, an emission critical angle, which is the largest angle at which light emitted from the resonator face can be radiated without being blocked by the projection and the protective film formed on the projection, is larger than an emission half-angle of an emission distribution in a vertical direction of a laser beam emitted from the resonator face.

A semiconductor package and method of producing the same has a semiconductor die having a first face and a second face. A coating material is coupled to the second face of the semiconductor die. A substrate having a cavity is provided wherein the semiconductor die is placed within the cavity. An encapsulant is used to encapsulate the second face of the semiconductor die placed in the cavity. Connection members are provided to couple the semiconductor die and the substrate in order to transfer signals between the semiconductor die and the substrate. Terminal members are couple to the substrate to connect the semiconductor package to an external device. In the semiconductor package, a thermal expansion coefficient of the coating material C and a thermal expansion coefficient of the encapsulant E should be approximately equal in value in order to limit the problems associated with warpage.