5878 results about "Semiconductor package" patented technology

The invention relates to the field of semiconductor packaging material defect detection, in particular to a semiconductor packaging material defect detection method based on deep learning, which comprises the following steps: acquiring a surface image, and extracting a two-dimensional contour and a feature point set; preprocessing the image, and separating a packaging material main body area; constructing a two-dimensional defect identification model based on Transform, and outputting a two-dimensional detection result; scanning suspected and unknown defect areas to obtain three-dimensional point cloud data, and extracting geometric and texture features; fusing two-dimensional and three-dimensional data through a space-time alignment model; utilizing the multi-modal fusion model to output defect positions and types; and evaluating the defect importance based on the material node connectivity and the stress distribution, and generating a visual detection report. According to the invention, high-precision detection of semiconductor packaging material defects is realized, the defect identification rate, the positioning precision and the detection efficiency are improved through multi-modal data fusion and a deep learning model, and a visual report can be generated based on material structure quantification defect importance.

The invention discloses a semiconductor packaging device electromagnetic compatibility comprehensive test method and system, and belongs to the technical field of electromagnetic compatibility testing. The method comprises the following steps: collecting structure parameters, packaging topology and predefined function states of a to-be-tested packaging device, and constructing a polymorphic working model; establishing a disturbance injection control model according to each state and configuring disturbance source parameters; implementing dynamic disturbance injection and acquiring response data in a real working state of the device; performing time domain and frequency domain conjoint analysis on the response data, constructing an electromagnetic response dynamic feature sequence, inputting the electromagnetic response dynamic feature sequence into a machine learning model, extracting multi-dimensional coupling features and predicting tolerance; calculating performance indexes such as an interference tolerance score and a coupling strength index based on model output indexes, comparing the performance indexes with a standard, and evaluating a compatible risk level in a full state; the method realizes quantitative evaluation of the EMC performance of the packaging device with high reduction degree and multi-state coverage, and has the advantages of comprehensive test, accurate prediction, explainable attribution and the like.

The invention relates to the technical field of semiconductor packaging detection, and provides a self-adaptive semiconductor packaging detection method which comprises the following steps: synchronously acquiring packaging surface heat distribution data, three-dimensional deformation data and pin electric signal data through a multi-source sensor; performing dynamic weighted fusion on the multi-modal data based on the packaging process parameters to generate a defect feature matrix; performing dynamic threshold calibration on the defect feature matrix by adopting an adaptive threshold generation algorithm according to clustering center distribution in the historical defect pattern library; performing matching judgment on the dynamic threshold value and the real-time defect feature matrix through a multi-level logic decision model, and outputting a defect type, a position coordinate and a confidence score; and based on the defect type and the confidence score, triggering adaptive compensation control of the packaging process parameters, generating a feedback control instruction, and adjusting a packaging equipment execution mechanism in real time. The packaging quality and reliability can be improved, and the production cost and the defective rate can be reduced.

A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

The invention discloses an automatic chip thermocompression bonding device and an intelligent calibration method, and belongs to the field of semiconductor packaging and manufacturing. The device comprises a main body frame, an alignment vision system, a side vision system, a bonding arm and a workbench, and micron-order alignment and eutectic bonding of a chip and a substrate can be realized. A bonding arm adopts a vacuum suction nozzle to suck a chip, a substrate is fixed on a workbench through vacuum adsorption, an alignment visual system realizes automatic precision calibration and position feedback of the device by using a calibration sheet, and micron-sized alignment and intelligent matching of chip thermocompression bonding process parameters are realized by collecting image feature recognition. The workbench is finely adjusted to align the marking points of the chip and the substrate, then the bonding arm carries out the thermocompression bonding process, and meanwhile, the side vision system monitors the precision and reliability of chip bonding. The chip alignment precision is high, the method is suitable for the scene that multiple chips are bonded at the same time, the problem that the equipment calibration efficiency is low in the thermocompression bonding process can be solved, and the process reliability can be improved.

An IC stack includes: a plurality of integrated circuit (IC) structure horizontally separate with each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; wherein the area of the bottom surface or the top surface is larger than that of any sidewall; a laterally extending RDL structure covering each first sidewall of the plurality of IC structures; and an upward extending thermal conductivity layer between two adjacent IC structures. The thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si.

Novel tools and techniques are provided for implementing detection and estimation of direct and reflected navigation satellite (e.g., global navigation satellite system (“GNSS”), etc.) signal parameters in a multipath environment. In various embodiments, logic of semiconductor package that is disposed on a user device concurrently receives a plurality of signals from a satellite(s), each signal travelling along a different path between each satellite(s) and the user device within a multipath environment. The logic identifies two or more signal peaks that fall within a tracking aperture based on analysis of the received signals, and determines peak parameter estimates for each signal peak based on measurements of signal parameters from at least one signal peak. The logic provides the determined peak parameter estimates for each signal peak to a position engine (“PE”) of the user device to calculate a navigation solution (e.g., position, velocity, and / or time, etc.) for the user device.

A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

A photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

The invention discloses a semiconductor packaging defect detection system based on machine vision, and relates to the technical field of semiconductor packaging defect detection, and the system comprises a multispectral collection module which uses a multispectral camera and a light source to collect multiband images of a packaging surface from different angles, and carries out the preprocessing of the multiband images; the image fusion module is used for fusing the preprocessed wave band images into a comprehensive image by adopting an image fusion algorithm; the illumination adjusting module is used for carrying out illumination quality analysis on the comprehensive image, adjusting light source parameters based on a quality analysis result and re-collecting a multi-band image; the method has the beneficial effects that through the comprehensiveness of a multispectral image, the detail enhancement capability of image fusion, the stability of dynamic illumination adjustment, the feature extraction capability of deep learning and the anomaly detection capability of an auto-encoder, the robustness of the image fusion is improved; the defects of unstable image quality, insufficient feature extraction capability, inaccurate error judgment and the like in the prior art are comprehensively overcome.

The invention relates to the technical field of radio frequency integrated circuits and advanced semiconductor packaging, in particular to a multilayer spiral inductor structure based on an RDL process and a preparation method. The preparation method comprises the steps of seed layer deposition, gradient line width coil formation through photoetching and electroplating, alternate dielectric layer deposition, through hole etching to form vertical interconnection copper columns, air bridge forming through a photoresist sacrificial layer process and silicon nitride passivation packaging. Through fan-shaped topological layout, dielectric material collaborative optimization and three-dimensional interconnection structure design, the self-resonant frequency bandwidth is effectively improved, conductor and dielectric loss is reduced, and miniaturization integration and high reliability of high-frequency inductance elements are achieved.

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

A semiconductor package and the method for forming the same are provided. The semiconductor package includes a substrate having an upper surface and a lower surface, first integrated circuit devices mounted on the upper surface, and second integrated circuit devices mounted on the lower surface. A first heat spreader in the form of a vapor-chamber (VC) is located over the first integrated circuit devices. A second heat spreader in the form of a vapor-chamber is located over the second integrated circuit devices. A heat-transfer member thermally couples the first heat spreader and the second heat spreader on both sides of the substrate.

The invention relates to a semiconductor packaging structure and a packaging method thereof, and belongs to the technical field of semiconductor devices.The semiconductor packaging structure comprises a substrate, a chip, a radiator and a packaging shell, and further comprises an alloy needle matrix arranged below the radiator and a heated self-deformation fin arranged between the upper surface of the chip and the packaging shell; needle bodies of the alloy needle matrixes penetrate through the through holes in the substrate, needle tips of the alloy needle matrixes directly make contact with the back faces of the chips through the heat conduction springs, the heated self-deformation fins are unfolded through heating and abut against the top of the radiator, a double-channel vertical heat dissipation system is constructed, heat conduction paths from the chips to the radiator are directly broken through, and the double paths work in parallel. It is ensured that heat is vertically transmitted to the radiator through the shortest path, loss of traditional transverse heat diffusion is avoided, and the problems of thermal resistance accumulation caused by series connection of multiple layers of media, interface shear stress and micro cracks caused by mismatch of material thermal expansion coefficients of an existing semiconductor packaging structure are solved. And the problems of heat dissipation path failure and local high temperature of the chip caused thereby are solved.

The invention discloses a bonding full-automatic detection system and method based on image recognition, and belongs to the technical field of semiconductor packaging quality detection.The bonding area image is collected through a multi-angle visual sensor, bonding points are recognized and positioned, coordinates, sizes and arc heights of the bonding points are recorded, and a node network model is constructed according to a spatial distribution structure; selecting an initial node in the model to set a reference, transmitting reference values in sequence along a preset path, judging whether the reference is updated or not by each node by comparing a measured value with a received value, and recording a deviation state at the same time; in the process, the reference adjustment amplitude is recorded in real time, the accumulated adjustment amount of each path is calculated, abnormal transmission paths are identified, and deviation node density is counted to mark abnormal areas; and finally, according to the number of the abnormal paths and the area of the abnormal region, carrying out bonding quality judgment, automatically calculating the marking position of an unqualified product, and executing laser marking.

Provided is an arylalkyl-modified indene composition comprising a plurality of compounds, each of the compounds having one or more arylalkyl groups on an indene ring and differing from the others in the number of arylalkyl groups in one molecule. The content of the compound or compounds having a single arylalkyl group in one molecule is 1% or less in the composition at the percentage calculated on the basis of the area ratio in a GPC chart. At least one of the arylalkyl groups present in the composition is an arylalkyl group having a polymerizable unsaturated bond-containing group, while at least one of the arylalkyl groups present in the composition is an arylalkyl group having no polymerizable unsaturated bond-containing group.

The invention belongs to the technical field of information, and particularly relates to an industrial semiconductor packaging test system based on multi-dimensional intelligent decision making. By deploying multiple types of sensors and detection technologies at the tail end of the industrial robot and packaging test equipment, force touch and vision fusion and multi-modal data fusion technologies are applied, and flexible control, deep learning, big data analysis and reinforcement learning algorithms are combined. And flexible high-precision carrying of chips, rapid detection of packaging quality, deep processing of test data and multi-robot collaborative scheduling are realized. Meanwhile, the packaging test process is optimized by means of digital twinning and virtual simulation. According to the technology, the existing technical problems are effectively solved, and the precision, efficiency and quality of semiconductor packaging testing are remarkably improved.

Provided is an arylalkyl-modified indene composition that contains a plurality of types of compounds having an arylalkyl group on an indene ring, the compounds having different numbers of arylalkyl groups in one molecule, wherein: the content of a compound in which the number of arylalkyl groups in one molecule is 1 is 1% or less as calculated from the area ratio of the GPC chart; at least one of the arylalkyl groups present in the composition has a polymerizable unsaturated bond-containing group; and at least one of the arylalkyl groups present in the composition does not have a polymerizable unsaturated bond-containing group.

The invention relates to the technical field of semiconductor packaging, and provides a semiconductor packaging process which comprises the following steps: obtaining a circuit board, and preprocessing the circuit board; performing SMT assembly operation on the bottom surface of the circuit board; silk-screening solder paste on the top surface of the circuit board; a tin cap of the flip chip is dipped with a soldering flux; mounting a flip chip and other elements on the top surface of the circuit board; performing reflow soldering operation on the top surface of the circuit board; according to the semiconductor packaging process provided by the embodiment of the invention, the tin cap of the flip chip can be dipped with the soldering flux before confluence welding operation is carried out on the flip chip, so that in the reflow soldering process, the soldering flux can effectively protect the tin cap and a PCB bonding pad and prevent oxidation, the collapsed tin cap can recover the original state of the tin cap to the greatest extent during reflow soldering, and the reliability of the flip chip is improved. The tin cap can be in contact with the PCB bonding pad more effectively, good welding is formed, the wettability is improved, oxidation is reduced, the welding strength is enhanced, and the problems of pseudo soldering, open circuit and the like are reduced.

This method for producing an aryl-alkylated indene composition involves: adding an arylalkyl group having a polymerizable unsaturated bond-containing group to an indene compound; and adding an arylalkyl group having no polymerizable unsaturated bond-containing group to the indene compound to which the arylalkyl group having a polymerizable unsaturated bond-containing group is added.

A package includes a photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

Embodiments of the disclosure provide a semiconductor package including a first integrated circuit die having a first side and a second side opposite the first side, a first source / drain, a first interconnect structure disposed on the first side, a second interconnect structure disposed on the second side, and a first power rail extending between the first source / drain and the second interconnect structure. The package includes a second integrated circuit die disposed adjacent the first integrated circuit die, the second integrated circuit die having a first side and a second side, a second source / drain, a third interconnect structure disposed on the first side of the second integrated circuit die, a fourth interconnect structure disposed on the second side of the second integrated circuit die, and a second power rail extending between the second source / drain and the fourth interconnect structure, and an edge interconnect feature having a first end contacting the first interconnect structure and a second end contacting the third interconnect structure.

A semiconductor encapsulation composition includes a polymer resin, a hardener, a filler, and an additive configured to adjust a reaction rate between the polymer resin and the hardener, wherein the polymer resin includes a high heat-dissipating resin having a mesogen unit, and the filler includes diamond powder or a mixture of the diamond powder and an inorganic filler.

A semiconductor package includes a buffer die and a memory die sequentially stacked. The buffer die includes a first substrate having first and second surfaces, a through electrode extending through the first substrate and having a protrusion portion, a protective pattern on the second surface of the first substrate and covering a sidewall of the protrusion portion, a first conductive pad on the protective pattern and contacting the through electrode, and a filling pattern contacting an upper surface of the protective pattern and a sidewall of the first conductive pad and including an inorganic insulating material. The memory die includes a second substrate having first and second surfaces, and a second conductive pad and a conductive connection terminal sequentially stacked beneath the first surface of the second substrate. The first conductive pad contacts the conductive connection terminal.

Provided is a flux agent according to embodiments of the inventive concept, wherein the flux agent includes a first compound including an ester group and an epoxy group, a fourth compound which is a chemical reactant of a second compound including an epoxy group and a third compound including an amine group and a carboxyl group, and a photoinitiator, wherein the content of the first compound is 50 wt % to 60 wt % based on 95 wt % of the total agent, the content of the fourth compound is 3 wt % to 33 wt % based on 100 wt % of the total agent, and the content of the photoinitiator is 2 wt % to 10 wt % based on 100 wt % of the total agent.

A photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

The invention relates to the technical field of semiconductor packaging, in particular to a batch dust-free packaging device for power semiconductor devices and a using method of the batch dust-free packaging device for the power semiconductor devices, and the batch dust-free packaging device comprises a plastic packaging machine main body, a plastic packaging mold and a side frame, an upper plastic packaging mold and a lower plastic packaging mold are installed at the upper end and the lower end of the plastic packaging machine body respectively, a side frame is fixedly connected to one side of the plastic packaging machine body, a cleaning roller storage box is installed on one side of the side frame, and an electric push rod and an air supply and negative pressure unit are arranged in the cleaning roller storage box. Three-step dust-free cleaning of blowing, sucking and shaking is automatically carried out on a mold cavity after each time of plastic packaging; during air blowing, air is expanded and cooled twice through a conical barrel, the mold is synchronously cooled, and stubborn particles are stripped; negative pressure is formed on the surface of the cotton layer during air suction, and all residual scraps are sucked away; after cleaning is finished, the roller body returns to the storage box, the blocking block collides with the toothed plate to enable the roller body to jolt at high frequency, and attachments are shaken off into the box and are sealed and collected.

A semiconductor package has a first semiconductor package which includes a first redistribution structure, a first semiconductor chip on a lower surface of the first redistribution structure, a first encapsulant on at least a portion of the first semiconductor chip, a second redistribution structure on the first encapsulant, and a conductive post electrically connecting the first redistribution structure and the second redistribution structure through the first encapsulant; and a second semiconductor package which is on an upper surface of the first redistribution structure and comprises a third redistribution structure, a second semiconductor chip on the third redistribution structure, and a second encapsulant on at least a portion of the second semiconductor chip, wherein the first encapsulant integrally covers each of a lower surface and a side surface of the first semiconductor chip.

A force sensor has a sensing system including a target piece and a sensing element, configured to provide changes of a magnetic field, being generated by motion of the target piece. The sensing element senses these changes and provides a signal representative of the position of the target piece. An integrated circuit with processing means can process signals from the sensing element. A semiconductor package includes at least the integrated circuit. A flexible piece includes the target, and it is attached to the semiconductor package. The attachment area between the flexible piece and the semiconductor package does not extend beyond the top projection, or outline, of the semiconductor package. The flexible piece receives a force stimulus, so that upon exerting a force on the flexible piece, the displacement of the target piece with respect to the surface of the semiconductor package can be sensed by the sensing element.

A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.