9945 results about "Semiconductor package" patented technology

The invention relates to the field of semiconductor packaging material defect detection, in particular to a semiconductor packaging material defect detection method based on deep learning, which comprises the following steps: acquiring a surface image, and extracting a two-dimensional contour and a feature point set; preprocessing the image, and separating a packaging material main body area; constructing a two-dimensional defect identification model based on Transform, and outputting a two-dimensional detection result; scanning suspected and unknown defect areas to obtain three-dimensional point cloud data, and extracting geometric and texture features; fusing two-dimensional and three-dimensional data through a space-time alignment model; utilizing the multi-modal fusion model to output defect positions and types; and evaluating the defect importance based on the material node connectivity and the stress distribution, and generating a visual detection report. According to the invention, high-precision detection of semiconductor packaging material defects is realized, the defect identification rate, the positioning precision and the detection efficiency are improved through multi-modal data fusion and a deep learning model, and a visual report can be generated based on material structure quantification defect importance.

The invention discloses an AI-driven gold bonding wire process parameter optimization method and system, and relates to the technical field of semiconductor packaging, and the method comprises the steps: building a dual-channel deep learning network of a bonding process; the dual-channel deep learning network comprises a dynamic parameter optimization channel and a static parameter optimization channel; inputting bonding process dynamic data collected in real time and preset bonding process static data into the dynamic parameter optimization channel to obtain a dynamic process evaluation index; inputting preset bonding process static data into the static parameter optimization channel to obtain a static process evaluation index; and fusing the dynamic process evaluation index and the static process evaluation index through an adaptive weight fusion algorithm to obtain a comprehensive evaluation index, and optimizing the bonding process parameters. According to the invention, dynamic and static data are integrated through a dual-channel deep learning network architecture, intelligent and accurate optimization of bonding process parameters is realized in combination with an adaptive weight fusion algorithm, and the bonding quality and process stability are significantly improved.

To provide a semiconductor package containing an insulating material.SOLUTION: A semiconductor package 1000 contains: a re-wiring structure body 300 that contains a re-wiring layer containing copper (Cu) and an insulation layer 310 surrounding the re-wiring layer; a semiconductor chip 100 that is mounted onto the re-wiring structure body, and contains a plurality of chip-coupling members 130; an internal coupling terminal 134 that is arranged between the re-wiring structure body and the semiconductor chip, and electrically connects the re-wiring layer and a connection pad; an external coupling terminal 600 that is adhered to a lower side of the re-wiring structure body, and is electrically connected to the re-wiring layer; and a sealing member 250 that surrounds the semiconductor chip and the internal coupling terminal on the re-wiring structure body. The insulation layer is made of an insulating material, where K satisfies 20 or more in a TC index.SELECTED DRAWING: Figure 1

The invention discloses a semiconductor packaging device electromagnetic compatibility comprehensive test method and system, and belongs to the technical field of electromagnetic compatibility testing. The method comprises the following steps: collecting structure parameters, packaging topology and predefined function states of a to-be-tested packaging device, and constructing a polymorphic working model; establishing a disturbance injection control model according to each state and configuring disturbance source parameters; implementing dynamic disturbance injection and acquiring response data in a real working state of the device; performing time domain and frequency domain conjoint analysis on the response data, constructing an electromagnetic response dynamic feature sequence, inputting the electromagnetic response dynamic feature sequence into a machine learning model, extracting multi-dimensional coupling features and predicting tolerance; calculating performance indexes such as an interference tolerance score and a coupling strength index based on model output indexes, comparing the performance indexes with a standard, and evaluating a compatible risk level in a full state; the method realizes quantitative evaluation of the EMC performance of the packaging device with high reduction degree and multi-state coverage, and has the advantages of comprehensive test, accurate prediction, explainable attribution and the like.

A semiconductor package includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity interconnects located between and / or placed side-by-side with the dies, a substrate carrying all the dies with the substrate having a first cavity allowing a liquid to pass through, and a cold plate disposed over and in direct thermal contact with the top dies with the cold plate having a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first and second cavities. This semiconductor package can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual- or multi-sided cooling, power supply, and signaling. The semiconductor package further includes an underground interconnection (UGI) disposed in a STI region of the processor die.

Embodiments of the disclosure provided herein include a system and method for plasma cleaning and activation using hybrid bonding. The system includes a processing chamber, a substrate support configured to support a substrate during hybrid bonding substrate processing, a gas delivery system coupled to the processing chamber having at least one radical generator, and a controller configured to cause the substrate processing system to form a first layer on a first substrate, dissociate a gas in the at least one radical generator to form a plasma, flow the plasma into the processing volume of the processing chamber for a period of time, exhaust the plasma, by products, and effluent gas from the processing volume after the period of time, and adhere a second layer disposed on a second substrate onto the first layer using a hybrid bonding technique.

An apparatus includes a host and a baseboard management controller. The baseboard management controller includes a semiconductor package; and the semiconductor package includes a memory, a security hardware processor; and a main hardware processor. The main hardware processor causes the baseboard management controller to serve as an agent that, independently from the host, responds to communications with a remote management entity to manage the host. The security hardware processor manages the storage of a secret of the host in the memory.

A semiconductor package includes a redistribution structure, first and second integrated circuit dies that are connected to a first side of the redistribution structure, and third and fourth integrated circuit dies that are connected on a second side, opposite to the first side, of the redistribution structure. An optical bridge die is connected between the third and fourth integrated circuit dies, to the second side of the redistribution structure, which is configured such that the first and second integrated circuit dies optically communicate through the optical bridge die.

The invention relates to the technical field of semiconductor packaging detection, and provides a self-adaptive semiconductor packaging detection method which comprises the following steps: synchronously acquiring packaging surface heat distribution data, three-dimensional deformation data and pin electric signal data through a multi-source sensor; performing dynamic weighted fusion on the multi-modal data based on the packaging process parameters to generate a defect feature matrix; performing dynamic threshold calibration on the defect feature matrix by adopting an adaptive threshold generation algorithm according to clustering center distribution in the historical defect pattern library; performing matching judgment on the dynamic threshold value and the real-time defect feature matrix through a multi-level logic decision model, and outputting a defect type, a position coordinate and a confidence score; and based on the defect type and the confidence score, triggering adaptive compensation control of the packaging process parameters, generating a feedback control instruction, and adjusting a packaging equipment execution mechanism in real time. The packaging quality and reliability can be improved, and the production cost and the defective rate can be reduced.

A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

Semiconductor packages and, more particularly, semiconductor packages with increased power handling capabilities are disclosed. Semiconductor packages may include lead frame structures and corresponding housings that incorporate semiconductor die. To promote increased current and voltage capabilities, exemplary semiconductor packages include one or more arrangements of creepage extension structures, lead frame structures that may include integral thermal pads, additional thermal elements, and combinations thereof. Creepage extension structures may be arranged as part of top sides of semiconductor packages along with thermal pads of lead frame structures and additional thermal elements. Creepage extension structures may also be arranged as part of top sides and along on one or more peripheral edges of semiconductor packages to promote further increases in power handling.

The invention discloses an automatic chip thermocompression bonding device and an intelligent calibration method, and belongs to the field of semiconductor packaging and manufacturing. The device comprises a main body frame, an alignment vision system, a side vision system, a bonding arm and a workbench, and micron-order alignment and eutectic bonding of a chip and a substrate can be realized. A bonding arm adopts a vacuum suction nozzle to suck a chip, a substrate is fixed on a workbench through vacuum adsorption, an alignment visual system realizes automatic precision calibration and position feedback of the device by using a calibration sheet, and micron-sized alignment and intelligent matching of chip thermocompression bonding process parameters are realized by collecting image feature recognition. The workbench is finely adjusted to align the marking points of the chip and the substrate, then the bonding arm carries out the thermocompression bonding process, and meanwhile, the side vision system monitors the precision and reliability of chip bonding. The chip alignment precision is high, the method is suitable for the scene that multiple chips are bonded at the same time, the problem that the equipment calibration efficiency is low in the thermocompression bonding process can be solved, and the process reliability can be improved.

A semiconductor package includes a first semiconductor chip including first bonding pads disposed in a first main region on a first surface of a first substrate, first dummy bonding pads disposed in a first peripheral region on the first surface of the first substrate, and a first passivation layer disposed on the first surface, and a second semiconductor chip on the first semiconductor chip and including a wiring layer on a third surface of a second substrate and including redistribution pads in a second main region, second bonding pads disposed on the redistribution pads, second dummy bonding pads disposed in a second peripheral region on the wiring layer, and a second passivation layer disposed on the wiring layer. The first bonding pads and the second bonding pads are directly bonded to each other. The first dummy bonding pads and the second dummy bonding pads are directly bonded to each other.

The invention discloses a glass substrate structure, a semiconductor packaging structure and a manufacturing method thereof, and the glass substrate structure comprises a glass core plate which is provided with a first surface and a second surface which are opposite to each other; the blind groove is formed in the glass core plate from the first surface; the one or more first conductive through holes penetrate through the glass core plate and are exposed out of the blind groove and the second surface; the one or more second conductive through holes penetrate through the glass core plate and are exposed on the first surface and the second surface; the TSV chip is embedded in the blind groove, the TSV chip is provided with one or more first micro convex points formed on the surface of the TSV chip, and the first micro convex points are connected with the first conductive through holes in a thermocompression bonding mode; and the insulating layer is formed between the TSV chip and the blind slot. According to the glass substrate structure, the glass substrate and the active component can be systematically integrated, the active component is embedded in the glass substrate, the wiring density is improved, meanwhile, back power supply is provided, and high-precision, high-strength, high-reliability interconnection and high-integration-level multi-chip packaging can be achieved.

An IC stack includes: a plurality of integrated circuit (IC) structure horizontally separate with each other, wherein each IC structure comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; wherein the area of the bottom surface or the top surface is larger than that of any sidewall; a laterally extending RDL structure covering each first sidewall of the plurality of IC structures; and an upward extending thermal conductivity layer between two adjacent IC structures. The thermal conductivity of the upward extending thermal conductivity layer is higher than that of Si.

A semiconductor package includes: a first substrate; a bridge chip disposed on the first substrate and having a first region and a second region; an upper semiconductor chip disposed on the first region of the bridge chip; and conductive posts disposed on the second region of the bridge chip and spaced apart from the upper semiconductor chip, wherein the upper semiconductor chip is electrically connected to the conductive posts through the bridge chip.

The invention discloses an intelligent adaptive semiconductor packaging test optimization method, and relates to the technical field of semiconductor packaging test, and the method comprises the steps: S1, constructing a quantization topology sensing network, and collecting test parameters through a quantum tunneling effect dielectric sensing array and a topology photonic crystal waveguide field reconstruction technology; according to the intelligent self-adaptive semiconductor packaging test optimization method, self-consistent optimization of a high-dimensional dynamic test system is realized through a deep coupling architecture of quantum topology dynamic perception and bionic element learning decision and establishment of an intrinsic manifold space of test parameters, and the problem that the test efficiency is high under advanced packaging of semiconductor devices is solved. A traditional test technology has the problem of space-time frequency domain limitation in multi-dimensional parameter coupling detection.

A semiconductor package includes semiconductor chips each including at least one of a front insulating layer or a rear insulating layer, the semiconductor chips bonded to each other through direct bonding between the front insulating layer and the rear insulating layer. At least one of the semiconductor chips includes a device layer including an interconnection structure, and a conductive pattern on a front surface of the device layer. The conductive pattern includes pad patterns electrically connected to the interconnection structure, and a dummy pattern spaced apart from the pad patterns. The dummy pattern includes first dummy patterns between the pad patterns to overlap the pad patterns in a first direction, and a second dummy patterns between the first dummy patterns to overlap the pad patterns in the second direction. The second dummy patterns are spaced apart from the first dummy patterns.

The invention discloses a power source power optimization method, system and device of a copper wire system and a storage medium, and relates to the technical field of bonding copper wire production, and the method comprises the following steps: building an intelligent bonding copper wire system simulation model, obtaining virtual parameters based on the intelligent bonding copper wire system simulation model, and optimizing the virtual parameters; the optimized virtual parameters are applied to actual bonding equipment, and the actual power and the bonding effect of the bonding equipment are collected. According to the intelligent bonding copper wire system, the energy efficiency can be remarkably improved through power optimization of a power source, in the field of semiconductor packaging and microelectronic manufacturing, a traditional bonding process often depends on fixed power setting, the setting cannot adapt to different working conditions and material characteristics, energy loss and unstable bonding quality are caused, and the energy efficiency is affected. By optimizing the power of the power supply in real time, the method reduces unnecessary power consumption, reduces the production cost, and improves the bonding quality at the same time.

The invention relates to a thermoplastic polyimide resin with a block structure and a preparation method thereof, and a polyimide adhesive film and polyimide composite copper foil composed of the thermoplastic polyimide resin with the block structure. The polyimide adhesive film is formed by coating thermoplastic polyimide resin and thermosetting polyimide resin on a polyimide base film and mixing the thermoplastic polyimide resin and the thermosetting polyimide resin. Wherein the thermoplastic resin is composed of a hard segment containing a benzimidazole or amide unit and a soft segment containing a flexible ether bond. The polyimide adhesive film composite copper foil is prepared through rolling, mold pressing and other processing modes. The thermoplastic polyimide resin is of a soluble structure and does not need precursor processing, so that the formation of bubbles is effectively inhibited, and an IPN interpenetrating network structure is formed between the cured thermoplastic resin and thermosetting resin, so that the copper foil has excellent mechanical property, adhesive property and dimensional stability after being compounded; therefore, the method can be applied to the fields of semiconductor packaging, flexible copper-clad plates and the like.

A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.

Novel tools and techniques are provided for implementing detection and estimation of direct and reflected navigation satellite (e.g., global navigation satellite system (“GNSS”), etc.) signal parameters in a multipath environment. In various embodiments, logic of semiconductor package that is disposed on a user device concurrently receives a plurality of signals from a satellite(s), each signal travelling along a different path between each satellite(s) and the user device within a multipath environment. The logic identifies two or more signal peaks that fall within a tracking aperture based on analysis of the received signals, and determines peak parameter estimates for each signal peak based on measurements of signal parameters from at least one signal peak. The logic provides the determined peak parameter estimates for each signal peak to a position engine (“PE”) of the user device to calculate a navigation solution (e.g., position, velocity, and / or time, etc.) for the user device.

A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

The utility model relates to the field of semiconductor processing equipment, and discloses a dispensing device for semiconductor packaging, which comprises a working table, and is characterized in that the front end and the rear end of the upper surface of the working table are respectively provided with a first sliding chute, and a sliding rod is fixedly connected in the first sliding chute at the front end of the upper surface of the working table; according to the dispensing device for semiconductor packaging, compared with most traditional dispensing devices for semiconductor packaging, the first protective shell is arranged on the connecting block, and the supporting block is arranged in the first sliding groove; a user can control the movement of a steel wire rope through a third electric telescopic rod so as to control the angle of a second protective shell relative to a first protective shell, so that the angle of a liquid outlet head arranged in the second protective shell is adjusted, and the trouble that some special positions cannot be aligned during vertical dispensing is reduced; and the device can accurately inject the glue solution to a required position, so that the dispensing efficiency of the device is improved.

A photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

A semiconductor includes a first semiconductor chip, and a second semiconductor chip provided on the first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate including a first front side and a first back side, and a first back-side bonding layer including a first back-side bonding insulating film, and a first back-side bonding pad, wherein the second semiconductor chip includes a second semiconductor substrate including a second front side that faces the first back side and a second back side, and a second front-side bonding layer including a second front-side bonding insulating film bonded to the first back-side bonding insulating film. A side of the first semiconductor chip includes a plurality of first recesses, which are arranged along a vertical direction, and a second recess, which partially exposes a bottom surface of the second front-side bonding layer between the second front-side bonding layer and the first recesses.

The invention discloses a semiconductor packaging defect detection system based on machine vision, and relates to the technical field of semiconductor packaging defect detection, and the system comprises a multispectral collection module which uses a multispectral camera and a light source to collect multiband images of a packaging surface from different angles, and carries out the preprocessing of the multiband images; the image fusion module is used for fusing the preprocessed wave band images into a comprehensive image by adopting an image fusion algorithm; the illumination adjusting module is used for carrying out illumination quality analysis on the comprehensive image, adjusting light source parameters based on a quality analysis result and re-collecting a multi-band image; the method has the beneficial effects that through the comprehensiveness of a multispectral image, the detail enhancement capability of image fusion, the stability of dynamic illumination adjustment, the feature extraction capability of deep learning and the anomaly detection capability of an auto-encoder, the robustness of the image fusion is improved; the defects of unstable image quality, insufficient feature extraction capability, inaccurate error judgment and the like in the prior art are comprehensively overcome.

A package substrate and a method of fabrication thereof including stress buffer layers. Each stress buffer layer may be vertically spaced from and at least partially overlap with a corresponding bonding pad of the package substrate. The stress buffer pads may provide structural reinforcement to distribute tensile stress on the package substrate and inhibit warpage and crack formation in the package substrate. Accordingly, semiconductor package reliability and yields may be improved.

The present application provides a semiconductor package structure having interconnections between dies, and a manufacturing method of the semiconductor package structure. The semiconductor package structure includes a first interposer including a first substrate and a first interconnect layer over the first substrate; a second interposer disposed over the first interposer, wherein the second interposer includes a second substrate and a second interconnect layer over the second substrate; a first die disposed over the first interposer and adjacent to the second interposer; a second die disposed over the second interposer; a first molding disposed over the second interposer and surrounding the second die; and a second molding disposed over the first interposer and surrounding the first die and the first molding, wherein the first interconnect layer includes a first communication member electrically connecting the first die to the second interposer and the second die.

A semiconductor package may include a package redistribution layer including a plurality of package redistribution patterns and a package redistribution insulating layer surrounding the plurality of package redistribution patterns, a plurality of electronic components apart from each other in a horizontal direction on the package redistribution layer and including at least one sub package, a package molding layer covering a top surface of the package redistribution layer and surrounding the plurality of electronic components, and a plurality of package connection terminals attached to a bottom surface of the package redistribution layer in a fan-out manner. The at least one sub package may include a package substrate, a semiconductor chip attached to the package substrate, and a sub molding layer on the package substrate.