82 results about "Transistor array" patented technology

The density and power consumption of modern integrated circuits, such as Graphic Processing Units (GPUs), Central Processing Units (CPUs), and Network Processing Units (NPUs) is growing rapidly, which necessitates designing advanced cooling systems. Existing solutions for characterizing and validating these cooling system are inadequate. A flexible, scalable Thermal Test Vehicle (TTV) is disclosed which is based on an array of power transistors, measurement / control circuitry, and onboard computer. The TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

A kind of multi-channel high-voltage large current transistor array and its reliability test circuit belong to integrated circuit integration and testing technical field.Each column transistor circuit is composed of transistor array unit by composite transistor, freewheeling diode, base series resistance, current limiting resistance, pull-down resistance. Reliability test circuit includes single-chip microcomputer, single-chip microcomputer port indicator light, MOS drive circuit, transistor array device, transistor array device load system. Each interface of the single-chip microcomputer is connected with corresponding indicator light, corresponding MOS drive circuit unit, the output end of each unit of MOS drive circuit is connected with the base of corresponding array of transistor array device, the collector of corresponding array of transistor array device is connected with load system. It solves the problem that existing multi-channel transistor reliability test method cannot test signal interference between channels, thermal effect, potential failure risk under extreme working environment. It is widely used in transistor array product reliability test technical field.

Disclosed are a thin film transistor array and a display device including the same. The thin film transistor array includes: a first gate line extending in a first direction; a first data line and a second data line each extending in a second direction; a first write transistor connected to the first gate line and the first data line; a second write transistor connected to the first gate line and the second data line, and arranged in the first direction with the first write transistor; a first driving transistor connected to the first write transistor and arranged in a second direction with the first write transistor; a second driving transistor connected to the second write transistor, arranged in the first direction with the first driving transistor, and arranged in the second direction with the second write transistor; and a first operation control transistor connected to the first driving transistor and the second driving transistor, and arranged in the second direction with the first driving transistor. The integration level of the pixel circuit in the thin film transistor array can be relatively improved.

A memory device, a memory system, and a fabrication method are provided. The memory device includes a first semiconductor structure including a memory cell array in a memory array region of the first semiconductor structure. The memory cell array includes an array of transistors and an array of storage units which connect to corresponding transistors. The first semiconductor structure further includes an isolation structure surrounding the memory array region and isolating the array of storage units in the memory array region from a contact region of the first semiconductor structure.

A thin film transistor array substrate, a display panel and a display device. The thin film transistor array substrate includes a semiconductor layer, a gate layer and a source-drain layer arranged in a stacked manner, two insulating layers respectively located between the semiconductor layer and the gate layer and between the gate layer and the source-drain layer, the semiconductor layer comprises a source region, a drain region and a channel region located between the source region and the drain region, the channel region is doped with a p-type impurity, a molecular weight of the p-type impurity in the channel region is equal to or greater than 25, a range of a doping depth of the p-type impurity in the channel region is 1 nm to 20 nm.

This disclosure provides a power stage package and its manufacturing method, as well as a voltage regulation module and electronic device including the power stage package. The power stage package includes: a printed circuit board; a transistor array, wherein the first electrode of the low-side transistor is connected to the second electrode of the high-side transistor via a first trace in a first wiring layer, a first via penetrating an insulating layer, and a second trace in a second wiring layer; a first encapsulation layer covering the low-side transistor; a second encapsulation layer covering the high-side transistor; and a first rewiring layer exposed for receiving input signals, including a first rewiring portion covering a portion of a first side surface of the first encapsulation layer; a second rewiring portion covering a portion of a second side surface of the first encapsulation layer; a third rewiring portion covering a portion of a third side surface of the second encapsulation layer; a fourth rewiring portion covering a portion of a fourth side surface of the second encapsulation layer; and a fifth rewiring portion covering a portion of the second encapsulation layer away from the printed circuit board. The power stage package has good heat dissipation and helps to reduce resistance.

This application provides an electrochromic display device, comprising: a substrate; a thin-film transistor array circuit layer formed on the substrate; a transparent electrode layer formed on and electrically connected to the thin-film transistor array circuit layer; an electrochromic layer formed on the transparent electrode layer; an electrolyte layer formed on the electrochromic layer; an ion storage layer formed on the electrolyte layer; and a transparent counter electrode layer formed on the ion storage layer. The ion storage layer is made of an electrochromic material and can switch between a transparent state and a black state under voltage control. The electrochromic polarity of the ion storage layer is the same as that of the electrochromic layer. The electrochromic display device provided by this application improves the problem of color gamut reduction caused by incident light mixing in emitted light during monochrome display.

The application discloses an array type photoelectric tweezers chip and a manufacturing method thereof, and belongs to the technical field of micro-nano manipulation and semiconductor devices. The chip comprises a substrate layer, a transistor array structure, a liquid phase manipulation cavity and an upper plate structure. The transistor array structure comprises a plurality of NPN type or PNP type photoelectric transistors arranged in a horizontal array, and a deep trench isolation structure extending longitudinally into the substrate layer is arranged between adjacent units. The light receiving surface of each photoelectric transistor unit faces the liquid phase manipulation cavity, and is not covered by an upper light shielding metal layer. The virtual electrode working mode is adopted, a localized dielectrophoresis electric field is generated through light irradiation, and the accurate capture and manipulation of micro-nano particles in the liquid phase cavity are realized. The application solves the problems of low integration of a traditional optical tweezers chip, obstruction of light transmission caused by a metal light shielding layer and the like, has the advantages of compact structure, sensitive response, programmable array and the like, and can be widely applied to the fields of biological cell manipulation, nano material assembly and micro-fluidic analysis.

The invention discloses a liquid crystal display panel which comprises an array substrate, a color film substrate, a liquid crystal layer and a plurality of spacers, the liquid crystal layer and the spacers are arranged between the array substrate and the color film substrate, the fixed ends of the spacers are arranged on the color film substrate, and the free ends of the spacers face the array substrate; a transistor array layer is arranged on one side, facing the color film substrate, of the array substrate, the transistor array layer comprises a plurality of thin film transistors, and channels are formed in the thin film transistors; a part of the thin film transistor is a first transistor, a part of the thin film transistor is a second transistor, a channel of the first transistor extends along a first direction, and a channel of the second transistor extends along a second direction; part of the spacers are arranged above the corresponding first transistors, and part of the spacers are arranged above the corresponding second transistors. According to the liquid crystal display panel, the box thickness supporting capacity in a vibration environment can be improved.

This invention discloses a vector modulation active phase shifter, comprising a coupling network (100) for generating quadrature signals, a first active amplitude control module (200) and a second active amplitude control module (300) composed of a common-source cascode transistor array for adjusting the gain of in-phase and quadrature signals, and a power combining and output matching network (400). The vector modulation active phase shifter includes a phase compensation network (500) located between the coupling network for generating quadrature signals and the active amplitude control module, used to optimize the phase bandwidth of the quadrature signals and improve phase shift accuracy. This invention realizes a wideband, high-precision, directly digitally controlled vector combining active phase shifter with a 360° phase shift range.

A method of manufacturing a semiconductor device, a storage device, and an electronic apparatus are disclosed. The manufacturing method of the semiconductor device comprises the steps of forming a first structure layer; forming a first interlayer dielectric layer on the first structure layer; and forming a second structure layer on the first interlayer dielectric layer. Forming the first structural layer includes forming a first transistor array, a first conductive line, and a second conductive line. Forming the second structural layer includes forming a second transistor array, a third conductive line, and a fourth conductive line. The semiconductor device manufactured by the manufacturing method of the semiconductor device can meet the requirements of size and performance, and can improve the reliability of a storage and calculation integrated framework when being used for the storage and calculation integrated framework.

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system, and the semiconductor device comprises a transistor array which comprises a plurality of semiconductor main bodies; the conductive contact structure is positioned at one end of the semiconductor main body along the first direction and is coupled with the semiconductor main body; the first direction is the extension direction of the semiconductor main body; the conductive contact structure comprises a first contact structure and a second contact structure; the first contact structure comprises a first metal layer, and the second contact structure comprises a second metal layer.

The invention provides a transistor array substrate, comprising a thin film transistor, an insulating layer, a flat layer, two electrical testing pins, electrical measuring elements and pixel electrodes, wherein the thin film transistor is arranged on the transistor array substrate; the insulating layer is arranged at the lowest layer of the transistor array substrate; the flat layer is arranged above the insulating layer; the pixel electrodes are distributed above the flat layer; each pixel electrode comprises an upper pixel electrode, a lower pixel electrode and an electrode bridge for connecting the upper pixel electrode with the lower pixel electrode; the electrical measuring elements are arranged at the periphery of the transistor array substrate; the width of parts of electrical measuring elements is same as that of the electrode bridge; and the two electrical testing pins are arranged on the flat layer and connected with two ends of each electrical measuring element respectively. The transistor array substrate can confirm the electrical property of thin film transistor units accurately in time and guide the production condition quickly when any abnormity occurs.

The present disclosure relates to the technical field of display, and discloses a thin film transistor, an array substrate, a display panel and a display device. The thin film transistor is located on one side of a substrate, and comprises a channel part, a first electrode and a second electrode. The channel part is arranged on one side of the substrate. The first electrode comprises a first surface, the first surface is in contact with the channel part, and the first surface comprises a first edge line. The second electrode is arranged separately from the first electrode, and comprises a second surface, the second surface is in contact with the channel part, and the second surface comprises a second edge line. The second edge line is located on the side of the second surface close to the first electrode, and the orthographic projection of the second edge line on the substrate is located within the orthographic projection of the channel part on the substrate. The first edge line is located on the side of the first surface close to the second electrode. The voltage applied to the second electrode is higher than the voltage applied to the first electrode, and the length of the second edge line is greater than the length of the first edge line. The thin film transistor is not easy to be damaged, and the display device can display normally.

This invention relates to the field of integrated circuit technology, and discloses a switching circuit and method for suppressing the hot carrier injection effect. The switching circuit includes a first switching transistor and a second switching transistor array. The second switching transistor array includes multiple switching transistors connected in parallel. The first switching transistor is connected in parallel with the second switching transistor array, and the conduction area of ​​the first switching transistor is smaller than the total conduction area of ​​the second switching transistor array. The first switching transistor is configured to turn on before the second switching transistor array. This invention can effectively suppress the hot carrier injection effect while achieving high current transmission.

An LCD display unit of an aircraft inflight entertainment system includes a backlight driver driving light sources of a backlight panel to emit light through a polarizer layer and transistor array layer toward a liquid crystal layer. An LCD controller operates, during an image display mode, to receive data defining an image, and control transistors of the transistor array layer to directionally orient liquid crystals of corresponding pixels of the liquid crystal layer relative to a polarization direction of the polarization layer to define the image. The LCD controller further operates, during a retained pattern erase mode, to control the backlight driver to turn off or dim below a threshold level the backlight panel and to selectively control transistors of the transistor array layer to repetitively cycle orientations of liquid crystals between at least two offset directions to at least partially erase a retained pattern bias among the pixels.

The present disclosure describes a method for fabricating semiconductor structures having transistor arrays with different pitches. The method can include forming a first and second arrays of structures on a semiconductor substrate. The second array of structures can be blocked with a first mask while exposing the first array. A first treatment can be applied to the first array of structures. The first array of structures can be blocked with a second mask while exposing the second array of structures. A second treatment can be applied to the second array of structures, where the second treatment is different from the first treatment.

The application discloses an array gate driving circuit, a display panel and a display device. The array gate driving circuit comprises a plurality of array gate driving units connected in cascade, the array gate driving unit comprises a reset transistor for resetting the array gate driving unit, the array gate driving unit comprises a first array gate driving unit, the reset transistor of the first array gate driving unit is connected with a first reset signal source, the first reset signal source is not connected with a rear-stage array gate driving unit, and the array gate driving circuit further comprises a shunt module connected with the first reset signal source for shunting the reset transistor of the first array gate driving unit. The array gate driving circuit of the application is connected with the reset transistor of the first array gate driving unit through the shunt module, so that the reset transistor is shunted, damage of the reset transistor caused by no shunting of other rear-stage array gate driving units is avoided, and the phenomenon of horizontal stripe defects is avoided.

A TFT array substrate includes a bottom plate, a first metal layer, an insulating layer, a semiconductor layer, a second metal layer, and a transparent electrode layer. The first metal layer is located on the bottom plate. The insulating layer covers the bottom plate and the first metal layer. The semiconductor layer is located on the insulating layer and overlaps a first portion of the first metal layer. The second metal layer has a first portion on the semiconductor layer and a second portion on the insulating layer, and the second portion of the second metal layer overlaps a second portion of the first metal layer. A first portion of the transparent electrode layer is disposed along the first portion of the second metal layer, and a second portion of the transparent electrode layer is disposed along the second portion of the second metal layer.

The invention discloses a method for low-temperature selective growth of a p-type two-dimensional semiconductor film and preparation of a transistor, and belongs to the technical field of semiconductor devices. The invention provides a method for growing a p-type two-dimensional semiconductor film in a selected area at a low temperature, which comprises the following steps of: forming a Pt metal layer with the thickness of 1-4nm on the surface of a substrate with a dielectric layer through graphical deposition to obtain a sample with the Pt metal layer; the method comprises the following steps: putting powdered sulfur and a sample into an open container, vulcanizing or selenizing by adopting a CVD (Chemical Vapor Deposition) process, and finally annealing to obtain the p-type two-dimensional semiconductor film. The method has the core advantages that limitation of a traditional high-temperature preparation process is broken through, selective area array growth of p-type two-dimensional material films such as PtS2 and PtSe2 is achieved under the low-temperature condition compatible with a back-end-of-line (BEOL) process, a transistor array can be directly manufactured on the basis, the two-dimensional material transfer process is not needed, and the integration level of a CMOS circuit can be improved.

A fabrication process for a memory structure including three-dimensional arrays of thin-film ferroelectric storage transistors is disclosed. In some embodiments, the ferroelectric storage transistors are organized in three-dimensional arrays of horizontal NOR memory strings. In some embodiments, the fabrication process uses a liner underlayer in the deposition process of the channel layer where the liner underlayer provides a uniform surface for the deposition of the channel layer and also serves as an etch stop layer in the subsequent metal replacement process. In another embodiment, the fabrication process applies a liner layer in vertical shafts during the local word line process to reduce or eliminate irregular features in the local word line structures, thereby enhancing the electrical characteristics and reliability of the memory arrays thus formed.

Memory circuit (100) comprising: a first memory cell array (102) on a first layer (F); a second memory cell array on a second layer (F) that is distinct from the first layer (F); a first selection transistor array (104) on a third layer (F) that is distinct from the first layer (F) and the second layer (F); a second selection transistor array (106) on a fourth layer (F) that is distinct from the first layer (F), the second layer (F), and the third layer (F); a first set of bit lines (BL) extending in a first direction (Z) that are coupled to the first memory cell array (102), the second memory cell array, and the first selection transistor array (104); a second set of bit lines (BL) extending in the first direction (Z) and connected to the first memory cell array (102) and the second memory cell array through the first selection transistor array (104) are coupled;a first set of source lines (SL) extending in the first direction (Z) coupled to the first memory cell array (102), the second memory cell array, and the second select transistor array (106), and separated from the first set of bit lines (BL) in a second direction (X) that differs from the first direction (Z); and a second set of source lines (SL) extending in the first direction (Z) and coupled to the first memory cell array (102) and the second memory cell array through the second select transistor array (106), wherein the first select transistor array (104) has: a first select line (SG) extending in the second direction (X);and a first selection transistor (212) comprising a first gate, a first drain and a first source, wherein the first gate is coupled to the first selection line (SG), the first drain is coupled to a first bit line (BL) of the first set of bit lines (BL) and the first source is coupled to a first bit line (BL) of the second set of bit lines (BL), wherein the first memory cell array (102) comprises: a first word line (WL) extending in the second direction (X);and a first n-transistor having a second gate, a second drain and a second source, the second gate being coupled to the first word line (WL), the second drain being coupled to the first drain by the first bit line (BL) of the first set of bit lines (BL) and the second source being coupled to a first source line (SL) of the first set of source lines (SL), and wherein the second memory cell array has: a second word line (WL) extending in the second direction and separated from the first word line in the first direction;and a second n-transistor having a third gate, a third drain and a third source, wherein the third gate is coupled to the second word line (WL), the third drain is coupled to the first drain and the second drain by the first bit line (BL) of the first set of bit lines (BL) and the third source is coupled to the second source by the first source line (SL) of the first set of source lines (SL), and wherein the second select transistor array (106) has: a second select line (SG) extending in the second direction (X) and separated from the first select line (SG) in the first direction (Z);and a second selection transistor (214) having a fourth gate, a fourth drain and a fourth source, wherein the fourth gate is coupled to the second selection line (SG), the fourth drain is coupled to a first source line (SL) of the second set of source lines (SL) and the fourth source is coupled to the second source and the third source by the first source line (SL) of the first set of source lines (SL), wherein the first layer (F) is above the second layer (F), the second layer (F) is above the third layer (F) and the third layer (F) is above the fourth layer (F).

This invention provides a transistor array and its manufacturing method. The transistor array includes: a plurality of U-shaped active pillars with two branches arranged along a first direction and a second direction, respectively; each U-shaped active pillar includes: a channel region; a source at a first end of the channel region; a drain at a second end of the channel region, wherein the first end and the second end are opposite ends of the channel region in a third direction, the third direction being perpendicular to the surface of the substrate used to form the transistor array; the plane formed by the first direction and the second direction is perpendicular to the third direction; a plurality of gate structures, each gate structure being located between two adjacent U-shaped active pillars arranged along the first direction; and a plurality of electrically insulated connection portions, each connection portion electrically connecting two adjacent branches of two U-shaped active pillars that are physically in contact with the corresponding gate structure.

The invention belongs to the related technical field of hardware implementation of neural networks, and discloses a floating gate transistor-based and pre-nonlinear activated neural network in-memory computing system and a training method thereof, the in-memory computing system comprises a plurality of neural network hierarchies connected in series, and each hierarchy comprises a computing array, an input module and an output module; the calculation array is a transistor array formed by floating gate transistors; the input module obtains analog voltage and applies the analog voltage to the floating gate transistor; the floating gate transistor realizes non-linear activation and weighted calculation to obtain current and gathers and outputs the current through a bit line; and the output module is used for reading the current on the bit line, converting the current into a voltage signal and outputting the voltage signal from the output end of the corresponding level. According to the subversive calculation normal form, the non-linear activation step is arranged in front of the summation step, the normal form fundamentally eliminates the requirements for an independent non-linear activation function circuit and an analog-digital converter in the middle of the non-linear activation function circuit, and therefore the system architecture is greatly simplified, and the circuit area and power consumption are remarkably reduced.

The embodiment of the invention provides an array substrate, a display panel and a display device, relates to the technical field of display, and aims to solve the problem of poor display under an outdoor environment condition. The array substrate comprises a plurality of sub-pixels, and at least one sub-pixel in the plurality of sub-pixels comprises a first transistor; the array substrate further comprises a substrate, a gate layer, an active layer and a shading conductive layer, the gate layer comprises a gate pattern of the first transistor, and the active layer comprises an active layer pattern of the first transistor; the shading conductive layer comprises a first pattern and a second pattern, and the orthographic projection of the active layer pattern of the first transistor on the substrate is located in the orthographic projection of the first pattern on the substrate. The distance between the orthographic projection boundary of the first pattern on the substrate and the orthographic projection boundary of the active layer pattern of the first transistor on the substrate is within a set interval range; the transmittance of the first pattern is smaller than or equal to that of the second pattern; the second pattern is connected to the gate pattern of the first transistor.

The application provides a manufacturing method of a thin film transistor array substrate and a display panel. The method comprises the following steps: forming a plurality of dispersed metal oxide crystal grains on a substrate; forming an amorphous metal oxide semiconductor layer in contact with the plurality of metal oxide crystal grains, at least one metal element in the metal oxide crystal grains being the same as a metal element in the metal oxide semiconductor layer; and performing annealing treatment on the amorphous metal oxide semiconductor layer to obtain a crystallized metal oxide semiconductor layer.

Gunn diodes are included in a device plane of an integrated circuit device, e.g., a diode array is in the same plane as a transistor array. A Gunn diode includes two highly n-doped regions surrounding a lower-doped n-type region. The highly-doped regions may be formed through epitaxial deposition. A Gunn diode may be arranged as a vertical diode, with two contacts stacked vertically over and under the diode, or as a horizontal diode, with two contacts at opposite horizontal ends of the diode. The Gunn diodes may be formed around a fin, e.g., with a front-side contact over the fin and a back-side contact under the fin.

A thin film transistor array substrate includes a base substrate, a light shielding layer, a semiconductor layer, a gate insulating layer, a gate layer, and a source-drain metal layer in contact with the semiconductor layer and in contact with the light shielding layer sequentially disposed on the base substrate, a first insulating layer covering the source-drain metal layer disposed on the base substrate, and a metal protection layer disposed on the first insulating layer. The semiconductor layer, the gate layer, and the source-drain metal layer form a thin film transistor. An end of the metal protection layer is in contact with the source-drain metal layer, and another end of the metal protection layer is in contact with the light shielding layer.

The invention relates to a multi-mode electronic skin based on a flexible stretchable field effect transistor, the multi-mode electronic skin comprises a flexible substrate, a transistor array and an extension gate, the transistor array and the extension gate are arranged on the flexible substrate at intervals, and the transistor array comprises a gate array, a semiconductor layer, a dielectric layer and a source-drain electrode array which are sequentially stacked from bottom to top; the grid electrode array comprises a plurality of grid electrodes, the source and drain electrode array comprises a plurality of source and drain electrode pairs, and each grid electrode and the corresponding source and drain electrode pair form an OFET; the extension grid comprises a plurality of sensing units, each sensing unit comprises a working electrode, a reference electrode and a counter electrode, a sensitive layer is arranged on the working electrode of each sensing unit, and at least two sensitive layers in each sensing unit are different from each other; each OFET of the transistor array is divided into a plurality of parts with the same number as the sensing units, each part is in one-to-one correspondence with each sensing unit, and each sensing unit is electrically connected with a grid electrode of each OFET of the corresponding part.

The invention discloses a two-dimensional ring gate transistor doping method based on ultrafast laser direct writing and a CMOS device, and belongs to the technical field of microelectronic device manufacturing and advanced semiconductors. The method comprises the following steps: providing a substrate on which a two-dimensional semiconductor material ring gate transistor array is prepared; constructing a gas-phase or liquid-phase doping environment on the surface of the gate-all-around transistor; carrying out scanning doping on the selected channel region by adopting an ultrafast laser processing system; and carrying out a post-processing step. According to the method, the nonlinear optical effect and the cold machining characteristic of ultrafast laser are utilized, nanoscale precise doping of the two-dimensional ring gate transistor is achieved, and lattice damage of a traditional doping technology to atomic-scale thickness two-dimensional materials is effectively avoided. By regulating and controlling laser parameters and doping environment, monolithic integration of the N-type transistor and the P-type transistor can be realized in a single two-dimensional material system, and the threshold voltage can be precisely regulated and controlled. The method has the advantages of nanoscale spatial resolution, no-damage processing, controllable doping concentration, low process temperature and the like, and is suitable for advanced semiconductor manufacturing and high-performance CMOS (complementary metal oxide semiconductor) integrated circuits.