271 results about "Transistor array" patented technology

The embodiment of the invention provides a display panel and a display device. A first substrate comprises a first substrate, a transistor array layer, a pixel electrode layer, a common electrode layer, a first inorganic insulating layer and a second inorganic insulating layer; the transistor array layer is arranged on one side of the first substrate, and the pixel electrode layer and the common electrode layer are arranged on the side, away from the first substrate, of the transistor array layer; the transistor array layer comprises a transistor, the pixel electrode layer comprises a pixel electrode, and the common electrode layer comprises a common electrode; the insulating layer between one of the pixel electrode layer and the common electrode layer close to the transistor array layer and the transistor array layer is a first inorganic insulating layer; the second inorganic insulating layer is disposed between the pixel electrode layer and the common electrode layer. The insulating layer between one of the pixel electrode layer and the common electrode layer close to the transistor array layer and the transistor array layer is set as the inorganic insulating layer, so that the thickness of the display panel can be reduced, the preparation cost of the display panel is reduced, and the process steps are reduced.

A DC electronic load circuit relates to the technical field of electronic load control. The utility model provides a direct current electronic load circuit which integrates a dissipation MOS tube array, an analog PID loop, a digital integrated control module, a bus electrical parameter sampling and processing module and a WiFi communication module, and realizes a plurality of working modes such as constant current, constant voltage, constant resistance and constant power by accurately controlling the conduction degree of the MOS tube array. The system has the advantages of real-time monitoring, remote control, overvoltage and overcurrent protection, low power consumption design and the like, and an electronic load solution which is high in precision, high in stability and flexible to operate is provided, so that diversified test requirements are met, and the power supply test efficiency and safety are improved.

A method for fabricating a thin film transistor comprises disposing a semiconductor layer including a channel area, and a first and second electrode areas, disposing a gate insulating layer covering the semiconductor layer, disposing a diffusion barrier layer covering the gate insulating layer, disposing first and second electrode holes corresponding to the first and second electrode areas, and disposing a gate electrode overlapping the channel area, first and second electrodes electrically connected to the first and second electrode areas through the first and second electrode holes. The disposing of the first electrode hole, and the second electrode hole includes patterning the diffusion layer with a patterning mask disposed on the diffusion barrier layer. The disposing of the gate electrode and the first and second electrodes may include disposing a conductive material layer covering the diffusion barrier layer, and patterning the conductive material layer.

The invention discloses a terahertz phase shifter chip based on a magnetic coupling line fine adjustment technology, the magnetic coupling line fine adjustment technology is applied to a magnetic coupling line distributed attenuator, and a magnetic coupling line is added below a transmission line of the magnetic coupling line distributed attenuator. And a switching transistor array and a capacitive compensation transistor are respectively added at two ends of the magnetic coupling line. A vector synthesis type structure is adopted, the magnetic coupling line fine adjustment technology is innovatively provided and applied to the magnetic coupling line distributed attenuator, compared with a traditional distributed attenuator, the magnetic coupling line distributed attenuator has the advantages of being higher in precision and smaller in attenuation stepping, the occupied area is the same, the phase shifting control function of the phase shifter is achieved based on the attenuator, and the application range is wide. Finally, the phase of an output signal is controlled to realize a phase control function of 5.625-degree phase shift stepping in a full 360-degree range, and an amplitude control function in a 3dB range can be realized.

The invention provides a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises a first stacking structure which is provided with a first surface for bonding; the first stacked structure comprises a transistor array and a charge storage array, the transistor array and the charge storage array are stacked in the direction perpendicular to the first surface, and the transistor array is closer to the first surface than the charge storage array; wherein the charge storage array is provided with a first connecting end and a second connecting end, the first connecting end is used for connecting the charge storage array and the transistor array, and the second connecting end surrounds the peripheries of the transistor array and the charge storage array and extends to be close to the first surface. The embodiment of the invention can improve the integration density and reliability of the storage circuit at the same time.

The embodiment of the invention provides a thin film transistor, an array substrate and a display device, relates to the technical field of display, and aims to solve the problem that a display picture of the display device flickers. The thin film transistor includes a control electrode, an active layer, a first conductive pattern, and a second electrode. Wherein the control electrode, the active layer and the first conductive pattern are sequentially arranged on the substrate in a stacked mode, in the direction perpendicular to the substrate, the part, right opposite to the active layer, of the first conductive pattern is a first electrode of the thin film transistor, and in the first direction, the active layer exceeds the first electrode. The second electrode and the first electrode are oppositely arranged in the second direction, the part, located between the first electrode and the second electrode, in the active layer is a channel of the thin film transistor, and the orthographic projection of the channel on the substrate is located within the orthographic projection of the control electrode on the substrate. Wherein the first direction and the second direction are parallel to the substrate, and the first direction and the second direction intersect.

The density and power consumption of modern integrated circuits, such as Graphic Processing Units (GPUs), Central Processing Units (CPUs), and Network Processing Units (NPUs) is growing rapidly, which necessitates designing advanced cooling systems. Existing solutions for characterizing and validating these cooling system are inadequate. A flexible, scalable Thermal Test Vehicle (TTV) is disclosed which is based on an array of power transistors, measurement / control circuitry, and onboard computer. The TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

Semiconductor devices and fabricating methods are provided. In some implementations, a disclosed semiconductor device comprises a memory array structure and a peripheral circuit structure connected with the memory array structure. The memory array structure comprises a transistor layer comprising a plurality of arrays of vertical transistors, a storage layer comprising a plurality of arrays of capacitors coupled with the vertical transistors, a plurality of bit lines coupled with the vertical transistors, and a first interconnection layer comprising a first interconnection structure connected with the plurality of bit lines, and a second interconnection structure disconnected with the plurality of bit lines and connected to a common electrical node. The peripheral circuit structure comprises a second interconnection layer comprising a third interconnection structure connected with the first interconnection structure, and a sense amplifier circuit connected with the third interconnection structure.

The embodiment of the utility model provides an array substrate, a display panel and a display device, relates to the technical field of display, and aims to solve the problem of poor display under an outdoor environment condition. The array substrate comprises a plurality of sub-pixels, and at least one sub-pixel in the plurality of sub-pixels comprises a first transistor; the array substrate further comprises a substrate, a gate layer, an active layer and a shading conductive layer, the gate layer comprises a gate pattern of the first transistor, and the active layer comprises an active layer pattern of the first transistor; the shading conductive layer comprises a first pattern and a second pattern, and the orthographic projection of the active layer pattern of the first transistor on the substrate is located in the orthographic projection of the first pattern on the substrate. The distance between the orthographic projection boundary of the first pattern on the substrate and the orthographic projection boundary of the active layer pattern of the first transistor on the substrate is within a set interval range; the transmittance of the first pattern is smaller than or equal to that of the second pattern; the second pattern is connected to the gate pattern of the first transistor.

The invention discloses a CNFET-based high-speed digital low dropout regulator power supply chip, which comprises a silicon-based SOC and a CNFET power supply management chip layer grown above the silicon-based SOC, a plurality of digital LDOs are arranged on the CNFET power supply management chip layer, the input end of the CNFET power supply management chip layer is connected to an external power supply end, and the output end of the CNFET power supply management chip layer is connected with the silicon-based SOC to supply power to the silicon-based SOC. The digital LDO comprises a comparator, a coarse adjustment unit, a fine adjustment unit and a voltage output unit which are connected in sequence. The input end of the comparator is respectively connected with a reference voltage end and the voltage output unit, and the output end is respectively connected to the coarse adjustment unit and the fine adjustment unit; the coarse adjustment unit comprises an adjustment controller and a coarse adjustment power transistor array which are connected with each other; the fine adjustment unit comprises a shift register and a fine adjustment power transistor array which are connected with each other. According to the invention, high-efficiency and stable voltage regulation can be realized under the condition of considering the response speed and the regulation precision.

A kind of multi-channel high-voltage large current transistor array and its reliability test circuit belong to integrated circuit integration and testing technical field.Each column transistor circuit is composed of transistor array unit by composite transistor, freewheeling diode, base series resistance, current limiting resistance, pull-down resistance. Reliability test circuit includes single-chip microcomputer, single-chip microcomputer port indicator light, MOS drive circuit, transistor array device, transistor array device load system. Each interface of the single-chip microcomputer is connected with corresponding indicator light, corresponding MOS drive circuit unit, the output end of each unit of MOS drive circuit is connected with the base of corresponding array of transistor array device, the collector of corresponding array of transistor array device is connected with load system. It solves the problem that existing multi-channel transistor reliability test method cannot test signal interference between channels, thermal effect, potential failure risk under extreme working environment. It is widely used in transistor array product reliability test technical field.

A method includes, during a time period A, in a computer storage element having first and second power inputs separated by an array of transistors, the computer storage element configured to store computer data bits, move an input of the array of transistors, a logic value "1" or "0" to a master latch; during a time period B, recovering at least a portion of the energy containing the input using the first clock; during a time period C, moving the input in the main latch to the isolation stage; recovering at least a portion of the energy containing the input from the isolation stage using a second clock during a time period D; during a time period E, recovering at least a portion of the energy containing the input from the slave latch using a third clock; and moving at least a portion of the input from the isolation stage to the slave latch during the time period F.

Disclosed are a thin film transistor array and a display device including the same. The thin film transistor array includes: a first gate line extending in a first direction; a first data line and a second data line each extending in a second direction; a first write transistor connected to the first gate line and the first data line; a second write transistor connected to the first gate line and the second data line, and arranged in the first direction with the first write transistor; a first driving transistor connected to the first write transistor and arranged in a second direction with the first write transistor; a second driving transistor connected to the second write transistor, arranged in the first direction with the first driving transistor, and arranged in the second direction with the second write transistor; and a first operation control transistor connected to the first driving transistor and the second driving transistor, and arranged in the second direction with the first driving transistor. The integration level of the pixel circuit in the thin film transistor array can be relatively improved.

A memory device, a memory system, and a fabrication method are provided. The memory device includes a first semiconductor structure including a memory cell array in a memory array region of the first semiconductor structure. The memory cell array includes an array of transistors and an array of storage units which connect to corresponding transistors. The first semiconductor structure further includes an isolation structure surrounding the memory array region and isolating the array of storage units in the memory array region from a contact region of the first semiconductor structure.

A semiconductor device includes a transistor array and a sense pad. The transistor array includes a plurality of transistor cells electrically connected in parallel between a source electrode and a drain structure. The drain structure is formed in a semiconductor portion based on a single-crystalline wide bandgap material. A sense element formed from the wide bandgap material includes at least one rectifying junction electrically connected between the sense pad and the source electrode.

The utility model discloses a power transistor array comprising a transistor array substrate, an upper guard plate and transistors, the upper end of the transistor array substrate is integrally injection-molded with a needle groove, the middle parts of the two ends of the substrate are provided with assembling grooves, the inner walls of the assembling grooves are provided with through holes, the top of the upper end of the transistor array substrate is in butt joint with the upper guard plate, and the upper guard plate is in butt joint with the upper guard plate. And flow channels are formed around the middle part of the upper protection plate. When the power transistor array is used, the upper protection plate serves as an upper end protection structure of the transistor array substrate, the whole upper protection plate is designed by adopting a symmetrical distribution structure, transistors in the transistor array substrate can be well protected in multiple directions, damage to the transistors is reduced, and the reliability of the power transistor array is improved. Meanwhile, the upper protection plate is connected with the transistor array substrate in an embedded connection mode, the upper protection plate is connected with the transistor array substrate through the butt joint columns and the through holes, and the connection mode is easy to operate, convenient to use and practical.

A thin film transistor array substrate, a display panel and a display device. The thin film transistor array substrate includes a semiconductor layer, a gate layer and a source-drain layer arranged in a stacked manner, two insulating layers respectively located between the semiconductor layer and the gate layer and between the gate layer and the source-drain layer, the semiconductor layer comprises a source region, a drain region and a channel region located between the source region and the drain region, the channel region is doped with a p-type impurity, a molecular weight of the p-type impurity in the channel region is equal to or greater than 25, a range of a doping depth of the p-type impurity in the channel region is 1 nm to 20 nm.

The invention discloses a triode array reliability test method and a test circuit thereof, and belongs to the technical field of transistor test. The test method comprises a triode working point confirmation method, a reliability test power confirmation method, a reliability test circuit setting method, a reliability test circuit state monitoring method and a reliability test circuit anti-interference protection method. The test circuit comprises an NPN triode, a B pole voltage reference circuit, a B pole / voltage source constant current bias circuit, a B pole reverse breakdown prevention protection circuit, an E pole constant current bias circuit, an open circuit / poor contact display circuit, a short circuit display circuit and an anti-interference protection circuit. The problems that in the prior art, whether the aging power of the triodes reaches the standard or not cannot be judged, open-circuit or short-circuit triodes cannot be screened out in time, the total aging current is large when batch products are aged under the same power source, and the direct-current aging power of the products fluctuates due to external noise interference or crosstalk between the products are solved. The method is widely applied to reliability test technologies of transistors and transistor arrays.

The present invention discloses a multi-gain flat-panel detector and a reading data processing method, belonging to the field of image processing. The multi-gain flat-panel detector includes a scintillator layer and a reading circuit layer. Before reading, the reading circuit layer detects and corrects the signal and then outputs the image. Each pixel of the read image corresponds to its own independent thin-film transistor array, control circuit, and analog-to-digital converter, thereby achieving independent pixel reading. In addition, the overall capacitance of the charge amplifier can be adjusted by software control of the switching of the circuit containing the individual capacitors in the charge amplifier, thereby achieving control of the reading gain, solving the problems of data saturation and low data signal-to-noise ratio that are prone to occur in flat-panel detectors.

This disclosure provides a power stage package and its manufacturing method, as well as a voltage regulation module and electronic device including the power stage package. The power stage package includes: a printed circuit board; a transistor array, wherein the first electrode of the low-side transistor is connected to the second electrode of the high-side transistor via a first trace in a first wiring layer, a first via penetrating an insulating layer, and a second trace in a second wiring layer; a first encapsulation layer covering the low-side transistor; a second encapsulation layer covering the high-side transistor; and a first rewiring layer exposed for receiving input signals, including a first rewiring portion covering a portion of a first side surface of the first encapsulation layer; a second rewiring portion covering a portion of a second side surface of the first encapsulation layer; a third rewiring portion covering a portion of a third side surface of the second encapsulation layer; a fourth rewiring portion covering a portion of a fourth side surface of the second encapsulation layer; and a fifth rewiring portion covering a portion of the second encapsulation layer away from the printed circuit board. The power stage package has good heat dissipation and helps to reduce resistance.

The invention provides a graphene transistor sensor and a preparation method and application thereof, and belongs to the technical field of biosensors. The graphene transistor sensor is used for noninvasive detection of depression and can detect depression-related markers in body fluids such as sweat, urine and saliva through noninvasive collection. According to the invention, a biosensing chip is constructed by using a graphene transistor array modified by gold nanoparticles, and simultaneous monitoring of multiple biomarkers can be realized by fixing different aptamers; the response speed and the sensitivity of the sensor are improved by utilizing the ultrahigh carrier mobility of the single-layer graphene with the quasi-single-crystal structure, and high-precision accurate detection is realized when the concentration of a biomarker is relatively low; the gold nanoparticle layer is used for fixing the aptamer of the target biomolecule, the coverage rate of the gold nanoparticles can be regulated and controlled by limiting the thickness of the gold film, more active sites are provided, the detection range can be expanded, and the detection requirement for continuously and dynamically monitoring the concentration change of the biomarker is met.

This application provides an electrochromic display device, comprising: a substrate; a thin-film transistor array circuit layer formed on the substrate; a transparent electrode layer formed on and electrically connected to the thin-film transistor array circuit layer; an electrochromic layer formed on the transparent electrode layer; an electrolyte layer formed on the electrochromic layer; an ion storage layer formed on the electrolyte layer; and a transparent counter electrode layer formed on the ion storage layer. The ion storage layer is made of an electrochromic material and can switch between a transparent state and a black state under voltage control. The electrochromic polarity of the ion storage layer is the same as that of the electrochromic layer. The electrochromic display device provided by this application improves the problem of color gamut reduction caused by incident light mixing in emitted light during monochrome display.

An oxide semiconductor thin-film transistor array substrate and a stretchable display device including the same are provided. The stretchable display device can include a substrate having a pixel area and a stretchable area, an insulating member disposed over the substrate in the pixel area and including a first open area exposing the stretchable area, and a thin-film transistor disposed over an area including a side surface of the insulating member exposed by the first open area. Accordingly, the area occupied by the thin-film transistor can be reduced, thereby the size of the pixel area can be reduced and resolution can be improved.

The invention discloses a non-contact handwriting device based on an ultraviolet specific image sensor and a preparation method, and relates to the technical field of image sensing and human-computer interaction. Comprising a glass substrate 1, a transparent thin film transistor array 2 formed on the substrate, a photosensitive material layer 3 formed on the thin film transistor array, and an ultraviolet curing adhesive packaging layer 4 covering the photosensitive material layer. A light-sensitive material is a Bi2S3 material with a wavelength selective light current memory characteristic, generates long-time light current maintenance based on a photo-thermal electric effect in an ultraviolet band, rapidly attenuates in visible to near-infrared bands, and has ultraviolet input selectivity and ambient light anti-interference capability. According to the system, an ultraviolet laser pen is used as an input tool, handwriting patterns which can be kept for a long time are formed on an image sensor array, and image erasing based on a background normalization mechanism is supported. The image sensor array is composed of synaptic-like devices, has a long-term optical memory characteristic, and realizes integration of perception and storage.

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: forming a columnar channel of a transistor array on the surface of a wafer; wherein the extension direction of the columnar channel is perpendicular to the surface of the wafer; the columnar channels are distributed in an array along a first direction parallel to the surface of the wafer and a second direction parallel to the surface of the wafer; grid electrodes are formed on one side wall of each columnar channel of the transistor array, and the grid electrodes are parallel to the first direction and are arranged in the second direction; metal layers are formed between the adjacent columnar channels, and the metal layers extend in the first direction; source electrodes and drain electrodes of the transistors are respectively formed at the two ends of the extension direction of each columnar channel of the transistor array. The source electrode and the drain electrode are located at the two ends of the columnar channel in the extending direction respectively, the grid electrode is located on one side wall of the columnar channel, and the area of the transistor array is reduced. And the metal layers are formed between the adjacent columnar channels, so that the interference of the word lines on the adjacent columnar channels can be shielded.

The application discloses an array type photoelectric tweezers chip and a manufacturing method thereof, and belongs to the technical field of micro-nano manipulation and semiconductor devices. The chip comprises a substrate layer, a transistor array structure, a liquid phase manipulation cavity and an upper plate structure. The transistor array structure comprises a plurality of NPN type or PNP type photoelectric transistors arranged in a horizontal array, and a deep trench isolation structure extending longitudinally into the substrate layer is arranged between adjacent units. The light receiving surface of each photoelectric transistor unit faces the liquid phase manipulation cavity, and is not covered by an upper light shielding metal layer. The virtual electrode working mode is adopted, a localized dielectrophoresis electric field is generated through light irradiation, and the accurate capture and manipulation of micro-nano particles in the liquid phase cavity are realized. The application solves the problems of low integration of a traditional optical tweezers chip, obstruction of light transmission caused by a metal light shielding layer and the like, has the advantages of compact structure, sensitive response, programmable array and the like, and can be widely applied to the fields of biological cell manipulation, nano material assembly and micro-fluidic analysis.

The invention discloses a liquid crystal display panel which comprises an array substrate, a color film substrate, a liquid crystal layer and a plurality of spacers, the liquid crystal layer and the spacers are arranged between the array substrate and the color film substrate, the fixed ends of the spacers are arranged on the color film substrate, and the free ends of the spacers face the array substrate; a transistor array layer is arranged on one side, facing the color film substrate, of the array substrate, the transistor array layer comprises a plurality of thin film transistors, and channels are formed in the thin film transistors; a part of the thin film transistor is a first transistor, a part of the thin film transistor is a second transistor, a channel of the first transistor extends along a first direction, and a channel of the second transistor extends along a second direction; part of the spacers are arranged above the corresponding first transistors, and part of the spacers are arranged above the corresponding second transistors. According to the liquid crystal display panel, the box thickness supporting capacity in a vibration environment can be improved.

A three-dimensional semiconductor memory device may include a transistor array including a plurality of transistors on a substrate, a first guard contact plug extended into a region between the transistors, second guard contact plugs disposed to enclose the transistor array, and an impurity region below the first guard contact plug. The transistors may include a pair of first transistors, which are adjacent to each other with the first guard contact plug interposed therebetween, and a pair of second transistors, which are adjacent to the pair of first transistors. A distance between the pair of second transistors may be smaller than a distance between the pair of first transistors.

This invention discloses a vector modulation active phase shifter, comprising a coupling network (100) for generating quadrature signals, a first active amplitude control module (200) and a second active amplitude control module (300) composed of a common-source cascode transistor array for adjusting the gain of in-phase and quadrature signals, and a power combining and output matching network (400). The vector modulation active phase shifter includes a phase compensation network (500) located between the coupling network for generating quadrature signals and the active amplitude control module, used to optimize the phase bandwidth of the quadrature signals and improve phase shift accuracy. This invention realizes a wideband, high-precision, directly digitally controlled vector combining active phase shifter with a 360° phase shift range.

Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.