The invention relates to the field of
clock synchronization, in particular to a
broadband arbitrary reference adaptive
clock synchronization device. An input
signal is amplified and shaped to generate two paths of signals, one path of signals is sent to an FPGA, the other path of signals is sent to an orthogonal power divider and then is mixed with a
local oscillator signal through an orthogonal modulator to obtain a
frequency mixing signal, the
frequency mixing signal passes through a
fixed frequency divider to obtain a frequency division signal, the frequency division signal and a DDS output signal are subjected to
phase discrimination to generate error
voltage, and the error
voltage passes through a low-pass filter to control a
crystal oscillator. The output of the
crystal oscillator passes through the coupler to generate two paths of signals, one path is used as a
global system clock, the other path passes through the
fixed frequency multiplier to obtain a frequency-doubled signal, the frequency-doubled signal passes through the filter
amplifier to the power divider, the power divider divides the frequency-doubled signal into two paths of signals, one path is used as a reference clock, and the other path is used as a reference clock; a corresponding frequency point generation output signal is generated under the control of the FPGA, and the other path of signal is used as a
local oscillator signal of the
quadrature modulator after passing through the
amplifier. The invention is applicable to the self-adaptive
clock synchronization device.