2806 results about "Device under test" patented technology

A testing apparatus includes a tester rack with a plurality of slots where at least one slot in the tester rack is a dedicated slot operable to receive a test interface board (TIB) from a back of the tester rack, where the back of the tester rack is opposite a front of a tester rack, and where the front of the tester rack faces a handler and a front-facing elevator. The apparatus also includes a handler operable to load devices under test (DUTs) onto the TIB and a front-facing elevator move the TIB from the dedicated slot to an available slot in the tester rack, wherein the available slot includes power electronics operable to connect to the TIB to test devices under test (DUT) disposed on the TIB.

A test and measurement instrument has a port to receive a signal from a device under test (DUT), one or more processors configured to execute code that causes the one or more processors to acquire a waveform from the signal, derive a pattern waveform from the waveform using one of either hardware or software clock recovery, perform linear fit pulse response (LFPR) extractions on the pattern waveform to extract more than one LFPR, determine a reference pulse response from the more than one LFPRs, compare at least one of the LFPRs to the reference pulse response to determine a difference, and tune the DUT to reduce the difference. The test and measurement instrument may also use the multiple LFPRs as an input to a machine learning network to perform measurement predictions for the DUT.

Embodiments of the present disclosure provide a fuzz testing method, an electronic device, and a computer readable storage medium. The fuzz testing method comprises: acquiring a data packet; generating a protocol rule tree model on the basis of the data packet; generating a test case on the basis of the protocol rule tree model; sending the test case to a device under test; and determining a test result on the basis of response information of the device under test.

Apparatuses, systems, and methods for generative Artificial Intelligence (AI) assisted test process development based on an initial input of a specification of a device under test (DUT). The specification of the DUT may be inputted into the Generative AI model. The Generative AI model may summarize the specification, request further input via an interaction with an end user to finalize a description of the DUT, and generate / create test assets, such as code, documentation, tables, diagrams, and so forth. The Generative AI model may collaborate with the end user to refine outputs from the test assets. The refined test assets may be sent to software applications that can use / run / deploy various test assets. Additionally, the generative AI may access local test hardware and enumerate test hardware on other systems via network / serial communications to create a test system that fits the identified hardware.

A signal processing method includes the steps of: receiving, by a first measurement circuit, an analog measurement signal from a device under test; digitizing, by the first measurement circuit, the analog measurement signal, thereby obtaining a digital measurement signal; removing, by a first noise reduction circuit, noise from the digital measurement signal, thereby obtaining a noise-corrected measurement signal; receiving, by a second measurement circuit, an analog reference signal, wherein the device under test generates the analog measurement signal based on the analog reference signal; digitizing, by the second measurement circuit, the analog reference signal, thereby obtaining a digital reference signal; removing, by a second noise reduction circuit, noise from the digital reference signal, thereby obtaining a noise-corrected reference signal; and determining, by a subtraction circuit, a digital difference signal based on the noise-corrected measurement signal and based on the noise-corrected reference signal. Further, a measurement system is described.

A fault identification system and method. The system comprises an edge device and a server. The edge device can extract, from an original vibration signal, signal characteristics reflecting an abnormal vibration state of a device under test and report the signal characteristics to the server; and the server can identify a fault state of the device under test on the basis of the signal characteristics. The data volume of the signal characteristics reported in the process is small, thereby reducing the bandwidth requirement; and the signal characteristics can be used for accurate fault identification, thereby improving the accuracy of fault identification.

The invention provides an online monitoring method for junction temperature and thermal impedance of a power device in a power cycle heating process, which comprises the following steps of: in the power cycle process, setting a relationship between conduction voltage drop and junction temperature of a tested device on line; on the basis of the relationship between the conduction voltage drop and the junction temperature, calculating the junction temperature of the tested device in the heating process on line by using the conduction voltage drop; on the basis of the junction temperature, calculating the transient thermal impedance of the tested device on line; in the power cycle process, a criterion is set to automatically judge and reset the relationship between the conduction voltage drop and the junction temperature, so as to ensure the accuracy of the junction temperature and the transient thermal impedance. The method overcomes the influence of device aging on the measurement accuracy of the junction temperature and the thermal impedance, can be completed only by using original hardware equipment for power circulation, and has the advantages of convenience and high efficiency in implementation.

The invention relates to the technical field of aircraft lightning protection tests, and discloses an aircraft lightning indirect effect and HIRF conduction sensitivity test device and method, and the device comprises a device under test (EUT), an accompanying monitoring device, an auxiliary device, an HIRF injection probe, a lightning injection probe, a monitoring probe, a lightning signal isolator, and an HIRF conduction test system. The invention discloses a lightning indirect effect test system and a digital oscilloscope. Aiming at the problem of electromagnetic environment potential safety hazards caused by independent evidence obtaining and independent rectification of civil aircraft thunder and lightning and HIRF airworthiness, thunder and lightning indirect effect and HIRF conduction sensitivity tests can be simultaneously carried out on an aircraft electronic and electrical system, the thunder and lightning and HIRF comprehensive protection performance of the aircraft electronic and electrical system is verified, and the potential safety hazards of the electromagnetic environment are effectively reduced. The thunder and lightning indirect effect and HIRF conduction sensitivity test device is simple in construction and easy for engineering realization, and can also be used for thunder and lightning and HIRF protection performance verification tests of other aircrafts.

Disclosed is a robotic system and method designed for the verification and validation of smart connected Human-Machine Interface (HMI) devices. The robotic system integrates a multi-finger modular robotic module, a haptic module, a finger actuator, vision cameras, vision lights, a finger rotary module, a Cartesian robotic arm, an onboard user interface, and an L-shaped door. The method involves replicating human finger interactions, simulating touch sensations on a device under test (DUT), ensuring continuous and reliable operation, utilizing vision cameras for navigation and verification, optimizing vision with controlled lighting, positioning cameras strategically, executing various tasks with a robotic arm, and facilitating user interaction through an onboard interface.

A probe card mounted in an of electronic device testing apparatus is described, having a probe head housing a plurality of contact probes, each having a first end portion which abuts onto contact pads of a device under test, a main board and a connected intermediate board which provides a distance spatial transformation between contact pads made on opposite faces thereof. The intermediate board is a space transformer which includes a plurality of modules that are plate-shaped and coplanar, and structurally and functionally independent from each other. Each module has a first face facing towards the probe head and a first plurality of contact pads whereonto respective second end portions of the contact probes abut and an opposite second face facing towards the main board. The second face has a second plurality of contact pads connected to the first plurality of contact pads.

The utility model relates to a power supply device and a testing machine, and the power supply device comprises a loop controller which receives an error value and outputs a driving signal; the digital-to-analog converter is connected with the loop controller, receives the driving signal and outputs a test signal; the output and sampling unit is connected with the digital-to-analog converter and the tested device, transmits the test signal to the tested device, samples a feedback signal output by the tested device and outputs a sampling signal; the analog-to-digital converter is connected with the output and sampling unit, receives the sampling signal and outputs a sampling value; and the clamping control unit is connected with the analog-to-digital converter and the loop controller, and outputs a pre-clamping instruction to the loop controller when determining that a pre-clamping condition is met according to the sampling value output by the analog-to-digital converter and a preset pre-clamping set value, so that the loop controller slows down output. The trigger of the clamping function can be predicted in advance to act in advance, the high overshoot voltage / overshoot current for triggering the clamping can be avoided, and the tested device can be prevented from being damaged when an abnormality occurs.

A measurement system includes a signal analysis circuit, a signal generator circuit, a control circuit, and a DUT connector. The DUT connector is connectable to a device under test for receiving a measurement signal outputted by the DUT. The signal analysis circuit is connected to the DUT connector for receiving the measurement signal. The signal generator circuit is configured to generate a radio frequency (RF) test signal that is transmitted to the DUT. The signal analysis circuit is configured to digitize the measurement signal, thereby obtaining a digitized measurement signal. The control circuit is configured to control the signal generator circuit to generate the RF test signal based on the digitized measurement signal, based on known error parameters of an error model of the measurement system, and based on a desired reflection coefficient at a reference plane associated with the DUT.

The invention discloses a scattering parameter de-embedding method, device and equipment, and relates to the technical field of semiconductors. The method comprises the following steps: obtaining n de-embedding test structural members; constructing a first ABCD matrix and a second ABCD matrix according to the first admittance and the second admittance; according to the third admittance, the fourth admittance and the length of each transmission line in the n transmission lines, constructing n third ABCD matrixes; the third admittance is the admittance between the unit length transmission line and the ground in the equivalent pi-type circuit corresponding to the unit length transmission line, and the fourth admittance is the admittance of the unit length transmission line; and according to the first ABCD matrix, the second ABCD matrix and the n third ABCD matrixes, solving to obtain a de-embedded ABCD matrix of the to-be-tested device, and converting the ABCD matrix of the to-be-tested device into scattering parameters. According to the embodiment of the invention, scattering parameter de-embedding can be more efficiently and flexibly realized, so that the overall scattering parameter de-embedding efficiency and precision can be effectively improved.

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

An example hinged device flexible substrate testing system includes: a first plate comprising a first surface configured to hold stationary a first side of a hinged device under test; a second plate comprising a second surface configured to hold a second side of the hinged device under test; a first cam follower coupled to the second plate; a first drive arm configured to move the first cam follower to cause the second plate to rotate about a hinge pivot axis of the hinged device under test; an actuator configured to rotate the drive arm; and a load cell configured to measure loads on the first plate while the actuator moves the second plate.

The invention discloses a junction temperature testing device and method for a high-electron-mobility transistor. A current measuring module in the junction temperature testing device for the high-electron-mobility transistor is used for acquiring current flowing through a tested device; the power supply module is electrically connected with the other end of the switch module, and the power supply module and the switch module are connected in parallel with the bus capacitor; the control module is electrically connected with the control end, the driving end and the regulation and control end of the switch module, and the control module is used for providing switching signals for the control end, the driving end and the regulation and control end of the switch module so as to control the switching states of the switch protection module, the tested device and the switch module; the heating plate is used for heating a tested device; the temperature detection module is used for measuring the temperature of the detected device; and the waveform analysis module is electrically connected with the control module, the temperature detection module and the current measurement module, and is used for obtaining and forming an experimental oscillogram of the tested device at the temperature according to the temperature, the current and the conduction time of the tested device controlled by the control module.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention provides an air interface testing system, and relates to the technical field of OTA testing, the system can comprise a reverberation chamber and a radio frequency shielding box, and the reverberation chamber is used for providing an electromagnetic environment for air interface testing of to-be-tested wireless equipment. The radio frequency shielding box is used for providing an environment without external electromagnetic interference for an air interface test of a to-be-tested wireless device. The calculation control equipment calculates the total omnidirectional sensitivity of the to-be-tested wireless equipment according to the ratio of the product of the output power of the to-be-tested wireless equipment in the radio frequency shielding box and the sensitivity of the radio frequency channel to the total radiation power of the to-be-tested wireless equipment in the reverberation chamber; the output power is the output power at the antenna port of the radio frequency front-end circuit of the to-be-tested wireless equipment, so that the total omnidirectional sensitivity can be calculated according to the total radiation power, and the signal transmitting power does not need to be gradually reduced for testing at different angles (microwave darkroom testing) or different stirring states (reverberation room testing); and the time for testing the total omnidirectional sensitivity is reduced.

The invention discloses a differential noise traction system and a differential signal noise parameter measurement method and device, and belongs to the field of chip measurement. The system is characterized in that a vector network analyzer comprises four ports, the input ends of two impedance tuners are respectively connected to a differential output port pair of the vector network analyzer, the output ends of the two impedance tuners are respectively connected to the differential input end of a tested device, the differential output end of the tested device is connected to the receiving end of a noise receiver, and the noise receiver is connected to the output end of the noise receiver. The output end of the noise receiver is respectively connected to a differential receiving port pair of the vector network analyzer; the direct-current power supply is used for supplying power to the tested device and the switch controller, and the switch controller is used for controlling an internal switch of the noise receiver; the differential output port pair generates a differential signal; the differential receiving port pair is used for receiving noise power of a differential signal; and the impedance tuner is used for adjusting the impedance point, so that the differential signals input to the tested device correspond to different differential impedances. The method can improve the measurement precision.

A method, apparatus, and / or system for soft defects modeling of measurements using time-domain reflectometry. Electro-Optic Sampling based Time-Domain Reflectometry (EOS-TDR) may quickly detect soft defects in a chip under test. For example, EOS-TDR may detect soft defects in each pin from a trace-structure point at a relatively high resolution. To interpret the results in a time sensitive manner, a reference model for chips may be established from chips that are known to have met the expected quality standards. Through automated analysis of the features of the device under test waveform, soft defects of a chip may be detected that would be otherwise undetectable under time constraints, temperature variations, applied current variations, applied voltage variations, vibration variations, moisture variations, or any other kind of possible variation.

The invention provides a method for setting a relationship between conduction voltage drop and junction temperature of a power device in a large-current on-off state, and the method enables a tested device to work in the on-off state, and the large current flowing through the device is a square wave current with a fixed amplitude and a fixed duty ratio. The operation junction temperature and the reference point temperature are set by controlling the operation condition of the circuit and the temperature of the radiator; after the device runs to a thermal steady state, measuring the conduction voltage drop and the reference point temperature of the device, then cutting off a large current, and injecting a constant small current into the measured device to measure the junction temperature of the measured device; the equivalent temperature of the packaging material is represented by the reference point temperature, and a linear relation among the conduction voltage drop, the reference point temperature and the junction temperature under the large current is fitted. According to the invention, the self-heating and external heating conditions of the whole timer can be flexibly controlled, and the influence of the temperature of the packaging material on the conduction voltage drop is considered, so that the accuracy of predicting the junction temperature by using the conduction voltage drop under large current is improved.

The invention discloses a method for preventing needle burning during testing of breakdown voltage of a discrete device. According to the method, in a test loop comprising a probe card and a test source, a voltage-withstanding module is connected in series between the probe card and a low-potential end of the test source. The voltage-withstanding module comprises a detection resistor Rx and a voltage-withstanding switching device connected with the detection resistor Rx in parallel. When the test current I is applied, if the current is increased abnormally due to poor contact and the like, and the voltage drop on the detection resistor Rx is greater than or equal to the starting voltage VT of the voltage-withstanding switching device, the voltage-withstanding switching device is switched on, the test current I is shunted, and the current flowing through the probe card is reduced, so that the probe is prevented from being burnt. The breakdown voltage of the tested device is calculated by measuring the total voltage V at the two ends of the test source and subtracting the voltage drop (I * Rx) on the detection resistor Rx, and the test accuracy is ensured. The method can effectively protect the probe card and improve the test reliability and efficiency.

A test system has ovens configured to hold devices under test (DUTs), DUT switches, each connected to the DUTs in an oven, splitters, each splitter connected to a DUT switch, an instrument switch connected to one output of each splitter, the other output of each splitter connected to a test instrument, and one or more processors to control the instrument switch to select one of the DUT switches connected to an oven, control the selected DUT switch to connect each DUT in the oven to a channel of the test and measurement instrument, use machine learning to tune the DUT to a set of parameters until the DUT passes or fails, repeat the connecting, tuning, and testing of each DUT until all DUTs in an oven have been tested, and repeat the selection and control of the DUT switches until each DUT in each oven has been tuned and tested.

A near-field testing apparatus for testing a device under test having an array of transmitter antennas is provided. The near-field testing apparatus includes a frame structure and a receiver circuit. The frame structure defines an array of grid sections, and is arranged for receiving the array of transmitter antennas at a first side of the array of grid sections. A periphery of each grid section at the first side surrounds a plurality of transmitter antennas in the array of transmitter antennas. The grid section is arranged to guide respective electromagnetic signals emitted by the transmitter antennas from the first side to a second side of the array of grid sections. The receiver circuit, disposed at the second side of the array of grid sections, is arranged to couple the electromagnetic signals out of the grid section.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

The invention relates to a software and hardware co-simulation chip verification method, system and device and a storage medium, and relates to the field of software and hardware co-simulation. The method is based on a hyperSemu system comprising an hsComple and an hsRun and an FPGA (Field Programmable Gate Array) comprising a DUT (Device Under Test) and a Transactor. The method comprises the following steps of: writing an RTL (Real Time Language) design code of a chip; compiling the RTL design code by utilizing hsCompile to obtain a DB file; downloading the DB file to an FPGA (Field Programmable Gate Array) through hsRun so as to carry out hardware simulation; according to the DUT and the Transactor, a Hybrid server program and a Hybrid client program are written, and the Hybrid client program comprises a simulator program and a Linux system; and performing software simulation in the Linux system according to the DUT and the simulator program. The technical effect of the invention is that the efficiency and speed of chip simulation verification are improved.

The present disclosure relates to a circuit board that includes a first edge connector configured to communicatively couple the circuit board to a first connector of a second circuit board. The first edge connector extends from a side of the circuit board a first length. The circuit board also includes a second edge connector configured to communicatively couple the circuit board to a second connector of the second circuit board. The second edge connector extends from the side of the circuit board a second length that is different than the first length.

The invention discloses a system and a method for testing the dynamic on resistance of a power GaN device. The testing system comprises a low-voltage power supply, a booster circuit, a constant current source circuit, a clamping circuit and a driving circuit, the low-voltage power supply is connected with the booster circuit; the test module comprises a switch tube QC and tested device groups Q1, Q2... Qn, the drain electrode of the control tube QC is connected with one side of the booster circuit, the source electrode of the control tube QC is connected with the drain electrode of the GaN device Q1, the source electrode of the GaN device Q1 is connected with the drain electrode of the GaN device Q2, the source electrode of the GaN device Q2 is connected with the drain electrode of the GaN device Q3,..., and so on, the source electrode of the GaN device Qn-1 is connected with the drain electrode of the GaN device Qn, and the source electrode of the GaN device Qn is grounded; the grid electrode of the switching tube QC and the grid electrodes of the tested device groups Q1, Q2... Qn are connected with the driving circuit; source electrodes and drain electrodes of the tested device groups Q1, Q2... Qn are respectively connected in parallel with resistors R1, R2... Rn. The tested device groups Q1, Q2... Qn are connected with the constant current source circuit; two ends of the resistors R1, R2... Rn are respectively connected with a clamping circuit, and the clamping circuit is connected with a data acquisition system. The reliability of measuring the dynamic on-resistance of the gallium nitride device is improved.

Disclosed is a test board which includes a substrate that includes a device under test (DUT) placement area where a first DUT and a second DUT are disposed, a first load switch connected in series with the first DUT and configured to be set to a switch on state or a switch off state based on a first enable signal, a second load switch connected in series with the second DUT and configured to be set to the switch on state or the switch off state depending on a second enable signal, and a test controller. The test controller may be configured to perform a test operation in a (1-1)-th mode by activating the first enable signal and deactivating the second enable signal and then perform the test operation in a (1-2)-th mode by deactivating the first enable signal and activating the second enable signal.

The embodiment of the invention provides a test method, which comprises the following steps of: when the alternating current noise of a target object is measured, firstly obtaining a circuit board file of the target object; and obtaining a typical direct current voltage value, a maximum direct current voltage value (namely the maximum voltage value received by the power supply pin) and a minimum direct current voltage value (namely the minimum voltage value received by the power supply pin) corresponding to the circuit board file, and finally determining the alternating current noise corresponding to the target object according to the first power supply parameter corresponding to the circuit board file. Therefore, the AC noise of the target object is determined by comprehensively considering the first power supply parameter of the target object, so that the range of the AC noise corresponding to the target object can be determined more accurately, the determined AC noise has more guiding significance for guiding the design of the tested equipment, and potential problems can be eliminated in a design simulation stage.