2070 results about "Device under test" patented technology

Embodiments of the present disclosure provide a fuzz testing method, an electronic device, and a computer readable storage medium. The fuzz testing method comprises: acquiring a data packet; generating a protocol rule tree model on the basis of the data packet; generating a test case on the basis of the protocol rule tree model; sending the test case to a device under test; and determining a test result on the basis of response information of the device under test.

A fault identification system and method. The system comprises an edge device and a server. The edge device can extract, from an original vibration signal, signal characteristics reflecting an abnormal vibration state of a device under test and report the signal characteristics to the server; and the server can identify a fault state of the device under test on the basis of the signal characteristics. The data volume of the signal characteristics reported in the process is small, thereby reducing the bandwidth requirement; and the signal characteristics can be used for accurate fault identification, thereby improving the accuracy of fault identification.

Disclosed is a robotic system and method designed for the verification and validation of smart connected Human-Machine Interface (HMI) devices. The robotic system integrates a multi-finger modular robotic module, a haptic module, a finger actuator, vision cameras, vision lights, a finger rotary module, a Cartesian robotic arm, an onboard user interface, and an L-shaped door. The method involves replicating human finger interactions, simulating touch sensations on a device under test (DUT), ensuring continuous and reliable operation, utilizing vision cameras for navigation and verification, optimizing vision with controlled lighting, positioning cameras strategically, executing various tasks with a robotic arm, and facilitating user interaction through an onboard interface.

A probe card mounted in an of electronic device testing apparatus is described, having a probe head housing a plurality of contact probes, each having a first end portion which abuts onto contact pads of a device under test, a main board and a connected intermediate board which provides a distance spatial transformation between contact pads made on opposite faces thereof. The intermediate board is a space transformer which includes a plurality of modules that are plate-shaped and coplanar, and structurally and functionally independent from each other. Each module has a first face facing towards the probe head and a first plurality of contact pads whereonto respective second end portions of the contact probes abut and an opposite second face facing towards the main board. The second face has a second plurality of contact pads connected to the first plurality of contact pads.

The utility model relates to a power supply device and a testing machine, and the power supply device comprises a loop controller which receives an error value and outputs a driving signal; the digital-to-analog converter is connected with the loop controller, receives the driving signal and outputs a test signal; the output and sampling unit is connected with the digital-to-analog converter and the tested device, transmits the test signal to the tested device, samples a feedback signal output by the tested device and outputs a sampling signal; the analog-to-digital converter is connected with the output and sampling unit, receives the sampling signal and outputs a sampling value; and the clamping control unit is connected with the analog-to-digital converter and the loop controller, and outputs a pre-clamping instruction to the loop controller when determining that a pre-clamping condition is met according to the sampling value output by the analog-to-digital converter and a preset pre-clamping set value, so that the loop controller slows down output. The trigger of the clamping function can be predicted in advance to act in advance, the high overshoot voltage / overshoot current for triggering the clamping can be avoided, and the tested device can be prevented from being damaged when an abnormality occurs.

A measurement system includes a signal analysis circuit, a signal generator circuit, a control circuit, and a DUT connector. The DUT connector is connectable to a device under test for receiving a measurement signal outputted by the DUT. The signal analysis circuit is connected to the DUT connector for receiving the measurement signal. The signal generator circuit is configured to generate a radio frequency (RF) test signal that is transmitted to the DUT. The signal analysis circuit is configured to digitize the measurement signal, thereby obtaining a digitized measurement signal. The control circuit is configured to control the signal generator circuit to generate the RF test signal based on the digitized measurement signal, based on known error parameters of an error model of the measurement system, and based on a desired reflection coefficient at a reference plane associated with the DUT.

The invention discloses a junction temperature testing device and method for a high-electron-mobility transistor. A current measuring module in the junction temperature testing device for the high-electron-mobility transistor is used for acquiring current flowing through a tested device; the power supply module is electrically connected with the other end of the switch module, and the power supply module and the switch module are connected in parallel with the bus capacitor; the control module is electrically connected with the control end, the driving end and the regulation and control end of the switch module, and the control module is used for providing switching signals for the control end, the driving end and the regulation and control end of the switch module so as to control the switching states of the switch protection module, the tested device and the switch module; the heating plate is used for heating a tested device; the temperature detection module is used for measuring the temperature of the detected device; and the waveform analysis module is electrically connected with the control module, the temperature detection module and the current measurement module, and is used for obtaining and forming an experimental oscillogram of the tested device at the temperature according to the temperature, the current and the conduction time of the tested device controlled by the control module.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention discloses a differential noise traction system and a differential signal noise parameter measurement method and device, and belongs to the field of chip measurement. The system is characterized in that a vector network analyzer comprises four ports, the input ends of two impedance tuners are respectively connected to a differential output port pair of the vector network analyzer, the output ends of the two impedance tuners are respectively connected to the differential input end of a tested device, the differential output end of the tested device is connected to the receiving end of a noise receiver, and the noise receiver is connected to the output end of the noise receiver. The output end of the noise receiver is respectively connected to a differential receiving port pair of the vector network analyzer; the direct-current power supply is used for supplying power to the tested device and the switch controller, and the switch controller is used for controlling an internal switch of the noise receiver; the differential output port pair generates a differential signal; the differential receiving port pair is used for receiving noise power of a differential signal; and the impedance tuner is used for adjusting the impedance point, so that the differential signals input to the tested device correspond to different differential impedances. The method can improve the measurement precision.

The invention discloses a method for preventing needle burning during testing of breakdown voltage of a discrete device. According to the method, in a test loop comprising a probe card and a test source, a voltage-withstanding module is connected in series between the probe card and a low-potential end of the test source. The voltage-withstanding module comprises a detection resistor Rx and a voltage-withstanding switching device connected with the detection resistor Rx in parallel. When the test current I is applied, if the current is increased abnormally due to poor contact and the like, and the voltage drop on the detection resistor Rx is greater than or equal to the starting voltage VT of the voltage-withstanding switching device, the voltage-withstanding switching device is switched on, the test current I is shunted, and the current flowing through the probe card is reduced, so that the probe is prevented from being burnt. The breakdown voltage of the tested device is calculated by measuring the total voltage V at the two ends of the test source and subtracting the voltage drop (I * Rx) on the detection resistor Rx, and the test accuracy is ensured. The method can effectively protect the probe card and improve the test reliability and efficiency.

A test system has ovens configured to hold devices under test (DUTs), DUT switches, each connected to the DUTs in an oven, splitters, each splitter connected to a DUT switch, an instrument switch connected to one output of each splitter, the other output of each splitter connected to a test instrument, and one or more processors to control the instrument switch to select one of the DUT switches connected to an oven, control the selected DUT switch to connect each DUT in the oven to a channel of the test and measurement instrument, use machine learning to tune the DUT to a set of parameters until the DUT passes or fails, repeat the connecting, tuning, and testing of each DUT until all DUTs in an oven have been tested, and repeat the selection and control of the DUT switches until each DUT in each oven has been tuned and tested.

Disclosed is a test aid unit that is installed between automatic test equipment (ATE) and a device under test (DUT), generates a test data signal according to a data processing and transmission / reception rate of the DUT in response to a control signal transmitted from the ATE, transmits the test data signal to the DUT, self-tests a test result signal transmitted from the DUT, and transmits the test result to the ATE. The test aid unit includes a clock signal divider, an integrated digital logic unit, a transmitter, and a receiver.

The invention relates to a software and hardware co-simulation chip verification method, system and device and a storage medium, and relates to the field of software and hardware co-simulation. The method is based on a hyperSemu system comprising an hsComple and an hsRun and an FPGA (Field Programmable Gate Array) comprising a DUT (Device Under Test) and a Transactor. The method comprises the following steps of: writing an RTL (Real Time Language) design code of a chip; compiling the RTL design code by utilizing hsCompile to obtain a DB file; downloading the DB file to an FPGA (Field Programmable Gate Array) through hsRun so as to carry out hardware simulation; according to the DUT and the Transactor, a Hybrid server program and a Hybrid client program are written, and the Hybrid client program comprises a simulator program and a Linux system; and performing software simulation in the Linux system according to the DUT and the simulator program. The technical effect of the invention is that the efficiency and speed of chip simulation verification are improved.

The present disclosure relates to a circuit board that includes a first edge connector configured to communicatively couple the circuit board to a first connector of a second circuit board. The first edge connector extends from a side of the circuit board a first length. The circuit board also includes a second edge connector configured to communicatively couple the circuit board to a second connector of the second circuit board. The second edge connector extends from the side of the circuit board a second length that is different than the first length.

Disclosed is a test board which includes a substrate that includes a device under test (DUT) placement area where a first DUT and a second DUT are disposed, a first load switch connected in series with the first DUT and configured to be set to a switch on state or a switch off state based on a first enable signal, a second load switch connected in series with the second DUT and configured to be set to the switch on state or the switch off state depending on a second enable signal, and a test controller. The test controller may be configured to perform a test operation in a (1-1)-th mode by activating the first enable signal and deactivating the second enable signal and then perform the test operation in a (1-2)-th mode by deactivating the first enable signal and activating the second enable signal.

A measurement system includes a common port, the common port being connectable to a signal output of the device under test. The measurement system further includes a signal line being connected to the common port, wherein the signal line includes a first directional coupler portion and a second directional coupler portion. The measurement system further includes a signal processing circuit, wherein the signal processing circuit includes an IQ analysis circuit and an IQ synthesizer circuit. The IQ analysis circuit is connected with the common port via the first directional coupler portion so as to receive a forward-travelling signal from the common port. Further, a testing method of testing a device under test is described.

A method for determining timing accuracy of one or more radio data packets includes: generating stimulus data, wherein the stimulus data includes the radio data packets and a reference time for transmission of the radio data packets over the air; storing the stimulus data on a test device; and replaying the stimulus data, by the test device, in order to determine the timing accuracy of the transmission of the one or more radio data packets by a device under test.

The invention discloses a dynamic reverse bias test method and system for a power semiconductor device, and relates to the technical field of power semiconductor device testing, and the method comprises the steps: obtaining a test parameter of a tested device, and carrying out the test circuit configuration based on the test parameter of the tested device; performing a dynamic reverse bias test based on the configured test circuit to obtain a test result; and analyzing and evaluating a test result. According to the method, the accuracy and reliability of a test result are improved, a solid foundation is provided for a subsequent dynamic reverse bias test, potential problems of the device can be found in time, it is ensured that the test result has an actual reference value, real-time data support is provided for subsequent evaluation and analysis, the performance state of the device can be accurately judged, and the reliability of the device is improved. The safety of the test process is ensured, the integrity and sufficiency of the test are ensured, and misjudgment caused by insufficient test is avoided.

A dynamic on-resistance and threshold voltage instability evaluation circuit for power devices and its operation method thereof are provided. The evaluation circuit includes a first switch element and a device under test which forms a half bridge circuit, an RL load, as well as a second switch element in parallel with a capacitor. The device under test is connected as a lower switch of the half bridge circuit. And the RL load enables repetitive hard switching operation of the device under test for dynamic on-resistance measurement. The second switch element in parallel with the capacitor enables threshold voltage measurement of the device under test. By adopting the circuit to characterize both instabilities of dynamic on-resistance and gate threshold voltage, the present invention is beneficial to achieving in shorter pulse width, faster measuring speed and inexpensive measuring equipment, and can thus be widely applied to group III-N based power devices.

The invention provides a device aging device and method, and an aging plate in the device aging device is arranged in a heat preservation box, and is connected with a microwave test module and a power supply module outside the heat preservation box, so that the microwave test module and the power supply module provide microwave signals and power required by testing for the aging plate. The aging board is provided with a plurality of test stations, each test station is provided with a plurality of connecting terminals, the first end of each connecting terminal is connected with the connector of the heat preservation box, the aging board is connected with the microwave test module and the power supply module through the connecting terminals and the connector, and in the heat preservation box, the aging board is connected with the microwave test module and the power supply module through the connecting terminals and the connector. And aging at different environment temperatures can be realized. Each aging seat is used for installing a plurality of tested devices, after the plurality of tested devices are installed on the aging seats, the aging seats are installed on the test stations on the aging plate, and the aging plate is provided with the plurality of test stations, so that the plurality of aging seats can be arranged on the aging plate, and batch tested devices can be synchronously subjected to an aging experiment.

A signal processing method includes: receiving, by a signal input, a digital input signal from a device under test; capturing, by a measurement circuit, at least one IQ measurement set based on the received input signal, wherein the at least one IQ measurement set comprises a plurality of IQ measurement points; determining, by an analysis circuit, a total noise of the digital input signal over frequency based on the at least one IQ measurement set; determining, by the analysis circuit, an instrument noise over frequency, wherein the instrument noise corresponds to noise generated by the measurement instrument; and determining, by the analysis circuit, a ratio of the instrument noise and the total noise over frequency, thereby obtaining a frequency-dependent scaling factor. Further, a measurement instrument is described.

The utility model relates to a light-operated calibration tool. The light-operated calibration tool particularly comprises the controllable photoresistor branch circuit, the controllable resistance value of the controllable photoresistor branch circuit can be accurately calculated by means of the known resistor branch circuit and the voltage measurement branch circuit, and then the light-operated calibration tool can be accurately calibrated by means of the characteristics that the resistance value of a photoresistor in the controllable photoresistor branch circuit is controllable when the photoresistor is illuminated and the resistance value of the photoresistor is stable. Any required accurate resistance value is provided for calibration, a standard resistor disc does not need to be replaced frequently, damage to a calibration instrument is avoided, safety is improved, meanwhile, testing of resistance values in different ranges of the to-be-tested equipment can be completed with high flexibility, and finally high-safety, flexible and accurate dynamic calibration of the to-be-tested equipment is achieved.

A test and measurement device has an input port to receive a signal from a device under test (DUT), the signal having a symbol rate, one or more analog-to-digital converters (ADC) to convert the signal to waveform samples at a sampling rate, and one or more processors, when aliasing is present: up-sample a portion of the signal having aliased samples to produce up-sampled samples; use the up-sampled samples to produce a real-time waveform; perform clock recovery on the real-time waveform to produce a recovered clock; and resample the aliased samples to produce a non-aliased waveform.

This application relates to apparatus and methods for simultaneously servicing a plurality of computing devices. In one example, a testing system includes a testing frame with a plurality of cabinets, each of the plurality of cabinets housing a computing device under test. Further, the testing frame includes a control cabinet housing a testing computing device, where the testing computing device is communicatively coupled, through one or more hubs located in one or more networking cabinets of the testing frame, to each of the plurality of computing devices under test. The testing frame may also include a bracket that secures a monitor and a keyboard, where the monitor and keyboard are communicatively coupled to the testing computing device. The testing computing device can simultaneously service the plurality of computing devices, such as by causing the deletion of user data, the loading of software, and the testing of various functions.

The utility model relates to the technical field of automobile testing, in particular to a double-pulse automatic testing device which comprises a shell provided with a containing cavity, an opening is formed in the shell, and a cover plate capable of being opened and closed is arranged at the opening; a signal generator, a tested device and an oscilloscope which are electrically connected in sequence are arranged in the accommodating chamber; the door lock module is used for locking the cover plate when the cover plate is closed; the high-voltage control module is electrically connected with the high-voltage power supply, the high-voltage power supply end of the tested device, the door lock module and the output end of the signal generator, and is used for connecting the high-voltage power supply and the tested device when the door lock module is locked and disconnecting the high-voltage power supply and the tested device after a double-pulse signal is output; the discharging module is electrically connected with the high-voltage control module and the high-voltage power supply end of the tested device and is used for releasing the high-voltage power supply after the high-voltage power supply is disconnected; and the door lock module is electrically connected with the high-voltage power supply end of the tested device and is used for unlocking the cover plate after the high-voltage power supply is released. By adopting the device, the test safety can be improved.

The present disclosure provides a testing apparatus, which includes a plurality of devices under test (DUTs) and an advanced process control monitor (APCM). The APCM includes a switch circuit, a control circuit, a detection circuit, and an auxiliary control circuit. The switch circuit includes a plurality of switch devices corresponding to the DUTs. The control circuit includes a plurality of control devices corresponding to the switch devices, and is configured to sequentially activate one of the switch devices during a test procedure of the testing apparatus. The detection circuit is configured to provide a first power supply voltage to a first terminal of each switch device. The auxiliary control circuit is configured to provide a second power supply voltage to a second terminal of each switch device deactivated the control circuit.

The invention discloses a passive DHTRB test circuit, method and product with optimized performance. The test circuit comprises a power supply, a first test accompanying tube S1, a second test accompanying tube S2, a tested device DUT, a positive overshoot circuit and a negative overshoot circuit. The positive electrode of the power supply is connected to the input end of the positive electrode overshoot circuit, the output end of the positive electrode overshoot circuit is connected with the drain electrode of the first test accompanying tube S1, the source electrode of the first test accompanying tube S1 is connected with the second test accompanying tube S2 and the drain electrode of the tested device DUT, the source electrode of the second test accompanying tube S2 is connected with the input end of the negative electrode overshoot circuit, and the output end of the negative electrode overshoot circuit is connected with the source electrode of the tested device DUT and is connected to the negative electrode of the power supply; when the first test accompanying tube S1 is switched on and the second test accompanying tube S2 is switched off, the positive overshoot circuit outputs forward overshoot voltage to the outside; when the first test accompanying tube S1 is turned off and the second test accompanying tube S2 is turned on, the negative overshoot circuit outputs a reverse overshoot voltage to the outside. According to the invention, the dV / dt performance of the passive DHTRB test can be improved.

A measurement system for determining a noise figure of a device under test is described. The measurement system determines a first total error power based on the output signal by a first noise canceling technique, wherein the first total error power includes systematic errors originating in the device under test and in the measurement system. The measurement system determines a second total error power based on the output signal by a different, second noise canceling technique. The second total error power includes systematic errors originating in the measurement system. The second total error power further includes noise originating in the device under test and in the measurement system outside of the measurement instrument. The measurement system is configured to subtract the first total error power from the second total error power, thereby obtaining an external noise power.

The invention belongs to the field of discrete device testing, and particularly discloses a discrete device testing system resource self-adaptive extension device and method. According to the application, the number of channel gating is set according to the tested device, so that the test system resource is matched with the circuit of the tested device; the gating state of the test channel and the resource switching sequence are judged by controlling the switching unit, and the switching unit is linked with the test system to automatically switch the channel, so that the time division multiplexing of the resources of the discrete device test system is realized; and then the test system resources are connected to the pins of the tested device in a customized manner through the resource expansion interface, so that the resource expansion of the discrete device test system can be realized. The method has a good application prospect under the problems of insufficient discrete device test system resources and low test efficiency. Experiments do not need to frequently replace testing system programs and clamps, and testing system resources are effectively expanded.