The invention discloses a dynamic bypass fault-tolerant
router in a network-on-
chip. The dynamic bypass fault-tolerant
router comprises input and output ports, an input buffer area, a
crossbar switch, a routing calculation unit, a self-checking circuit and a bypass channel. Key features comprise a fault information unit, a bypass selector, a single flit buffer area and an arbitration unit. The
router detects the self-fault through the self-checking circuit, and the fault information unit stores the information. And if the router fails, the bypass selector transmits the data packet through the bypass channel and bypasses the failed router. If the router is healthy, the router exchanges fault information with an adjacent router, the fault information is used for
routing decision of a data packet after integration, and meanwhile, the router can select a routing path with smaller congestion in an effective direction according to the flow distribution condition in a network. According to the method, the area overhead is relatively low, the routing hop count of the data packet is remarkably reduced, the
transmission delay of the data packet is reduced while the high reliability is maintained, and the network
throughput is improved.