2894 results about "Verification" patented technology

A technique verifies a compound software code using a modularized architecture. The compound software code may be divided into smaller components or modules that provide various functions (e.g., services) of the code. A set of properties may be defined for the modules, such that the verification technique may be used to verify that the modules manifest those properties, wherein at least one property may be security related and the remaining properties may be related to the services of the modules. The compound software code is divided into smaller modules to facilitate verification of the properties related to the services provided by the modules. Properties of the modules may be verified in accordance with an enhanced verification procedure to demonstrate that the modules manifest those properties and transform those modules into verified code bases (VCBs). The services of the VCBs may then be combined to provide functionality of the compound software code using well-defined interfaces, such as application programming interfaces (APIs).

Embodiments of the invention provide a construction verification method and device capable of verifying a security two-dimensional code offline. The method comprises the following steps of inputting information that needs coding and type information, carrying out digital signature operation and encryption operation on the input information according to an information release type, constructing combination information, and encoding to generate a security two-dimensional code which can be verified off-line according to a two-dimensional code coding rule; inputting the information of the security two-dimensional code and identifying included combination information and type information, analyzing and decoding the combination information to obtain independent sub-information according to the type information of the two-dimensional code, and verifying digital certificate effectiveness information, a digital signature of the input information and an effective time limit of the input information; and if all verifications pass, showing that the offline verification of the security two-dimensional code is correct and the coding information source of the security two-dimensional code is credible, otherwise showing that the information release source of the security two-dimensional code is incredible. The method and the device have the beneficial effects that the security two-dimensional code cannot be tampered, counterfeited and denied, the public or private information can be released, and the integrity of the information of the security two-dimensional code and the authenticity of the source can be verified offline without a network connection.

The invention discloses a method for installing application software. The method includes acquiring signature information carried by an installation program; utilizing prestored original signature information of an installation program of the application software to verify the signature information carried by the installation program, and if a verification result is unsuccessful, exiting installation of the application software; if the verification result is successful, executing an executable code of the installation program. The invention further discloses a device for installing the application software. By the method and the system, a tampered installation program can be effectively recognized, so that the application software which is maliciously modified is effectively avoided from being installed in an operation system.

Embodiments of the invention are directed to human challenge response test delivery systems and methods. Specifically, embodiments of the present invention are directed to secure human challenge response test delivery services of configurable difficulty for user devices. One embodiment of the present invention is directed to methods and systems for implementing a familiar and dynamic human challenge response test challenge repository created from transaction data. The dynamic human challenge response test challenge repository may be created by a server computer receiving a plurality of transaction data. Challenge items may be extracted from the transaction data using an extraction algorithm. Furthermore, in some embodiments a challenge message may be sent to a requestor, a verification request may be received, and the verification request may be compared to the challenge message. Another embodiment may be directed at using user information in a human challenge response test to mutually authenticate a user and a service provider.

Various techniques are provided for verifying the authenticity of software applications. Such techniques are particularly useful for verifying the authenticity of software applications used in online transactions involving users, payment service providers, and/or merchants. In one example, a set of application identifiers associated with a plurality of authenticated software applications are maintained and a verification request is received comprising an application identifier associated with an unverified software application. A token is generated in response to the verification request if the application identifier is in the set of application identifiers. The generated token is passed to the unverified software application. A user token is received and processed to determine whether the unverified software application is one of the authenticated software applications. A verification request is sent based on the processing. Additional methods and systems are also provided.

A method for the static analysis of concurrent multi-threaded software which bypasses the state explosion situation that plagues the prior art, thereby making our method scalable while—at the same time—producing no loss in precision. Our inventive method maintains patterns of lock acquisition and lock release by individual threads by constructing augmented versions of the threads. Once the augmented versions have been constructed, our inventive method verifies the concurrent program using existing tools for the verification of sequential programs—thereby greatly reducing implementation overhead. Finally, our inventive augmentation and method is carried out in an automatic manner—without requiring user intervention.

The invention relates to a production line design and optimization method based on digital twinning. The production line design and optimization method comprises the following steps: performing digital process design on a product, integrally planning a production line, constructing and integrating a digital twinning model of the production line, performing simulation verification on a virtual production line, constructing and implementing a physical production line, and performing virtual-real mapping and optimization on the production lines. According to the invention, the digital twinning model is constructed according to three levels of elements, behaviors and rules, and has production line evaluation, evolution and reasoning capabilities; a virtual production line model is established,virtual debugging and simulation operation of the virtual production line are achieved, the production line does not need to be constructed firstly, design risks are avoided, and debugging time is saved; and a virtual-real mapping relationship and an interaction mechanism between the virtual production line and the physical production line are established, statistical analysis is performed on theoperation data of the virtual production line, and optimization and management and control on the physical production line are realized.

A system and method for ontology-enhanced traceability in design and management applications employ ontology nodes embedded in a processor executable traceability link (network) coupling processor executable requirement modules to processor executable engineering object modules to facilitate in all stages of engineering object development. The engineering object development occurs through multiple models of computation, control, and visualization platform networked together via ontology-enhanced traceability mechanism. Processor executable design rule checking module embedded in the design concept nodes creates a pathway for the development process validation and verification at early stages of the object lifecycle. Linking of ontologies/meta-models is performed for the purposes of supporting ontology-enabled traceability across multiple domains.

The invention discloses a validation method and a system based on a heterogeneous network, comprising the steps that: a log server receives a unique label of a client; the log server and the client interactively determine second network information for transmitting a verification code by a first network; the log server sends a verification code notification massage to a notice server, the notification server sends the verification code to the client by a second network according to the verification code notification massage; the log server saves the verification code; the client sends a confirmation request including a unique label and a verification code to the log server by the first network; the log server verifies the unique label in the confirmation request, matches the unique label in the confirmation request with the unique label in the verification request, as well as matches the verification code in the confirmation request with the saved verification code. The validation method and the system based on the heterogeneous network improve the convenience and flexibility of a validation process based on the heterogeneous network.

The invention provides a reliable firmware upgrading realizing method applied to a distributed control system. The reliable firmware upgrading realizing method enables any controller nodes or a host in the system to have program upgrading capacity, greatly improves the expansion capacity of hardware equipment and the customizing performance of the system and reduces later maintenance and upgrading cost. The reliable firmware upgrading realizing method is different from a traditional method in that receiving of a target program package is realized in an application program, the received data package is stored into a backup program area at first, after the target program package is completely received and CRC verification is passed, parameter information marks are generated in an IAP mark area, and a Boot loader is called for to realize program upgrading. Even if an unpredictable failure occurs in any link, existing programs cannot be replaced, and therefore the stability of the system is greatly improved.

The invention discloses a bar-code-based information verification system. The information verification system comprises a bar code, a database subsystem, a management subsystem, a server cluster, a fixed terminal and a mobile terminal, wherein the bar code is used for identifying and encoding a product and comprises encrypted product information; the database subsystem is used for storing bar code information and the position information of the terminals; the management subsystem is used for information management and operation maintenance; the server cluster is used for providing support for verification service; the fixed terminal is used for reading the bar code information and sending the bar code information to the server cluster for processing; and the mobile terminal is used for real-time anti-counterfeiting verification. The bar-code-based information verification system has the advantages that (1) system safety is improved by using a dynamic encryption algorithm; (2) the response speed and throughput of the system are increased by using the server cluster; (3) data safety is improved by data backup; and (4) the improved bar code design is suitable for the anti-counterfeiting traceability of commodity.

In a system for statically analyzing a specified computer, a verification condition generator converts the program into a logical equation, called a verification condition, and inserts program flow control labels into the sub-equations of the verification condition. The flow control labels identify conditional branch points in the specified computer program. A theorem prover is applied to the logical equation to determine truth of the logical equation, and when the truth of the logical equation cannot be proved, the theorem prover generates at least one counter-example identifying one of the conditions, one or more variable values inconsistent with that condition, and any of the flow control labels for conditional branch points of the program associated with the identified variable values. A post processing module converts each counter-example into an error message that includes a program trace when the counter-example identifies one or more of the flow control labels.

The invention relates to a technique for safely updating a software and provides a software update packet packaging method for ensuring the legality and completeness of an updated software, as well as a software updating method. Digital certificates of trustworthy authentication institutes are prearranged in a terminal apparatus, or a server is used for determining the trustworthy authentication institutes; the authentication institutes respectively perform digital signing to the software and transmit an original cleartext software together with all digital signatures and digital certificates to the terminal apparatus; the terminal apparatus verifies whether all digital certificates are legal and judges the authentication institutes working together for updating the software; if all conditions are satisfied, the terminal apparatus verifies all digital signatures and then updates the software after the verification. As the legality of a software update packet is verified according to the digital certificates of the authentication institutes, the completeness of the software update packet is verified according to the digital signatures of the authentication institutes and a plurality of parties participate the concerted signing to the software, the safe update of the software is ensured.

The invention relates to a system for automatically converting a hardware language VHDL (Vhsic Hardware Description Language) into an MSVL (Modeling, Simulation and Verification Language). The system can convert a VHDL language program file into an MSVL language program file; the conversion system comprises a file analysis module, a lexical analysis module, a syntactic analysis, an information storage module, a translation module and a translation result character string connection module. After a VHDL program is converted into an MSVL program, model construction and property description use the same language, so that verification is carried out in the same logic framework and indirect model detection on the VHDL language program is conveniently realized. In the converting process, the VHDL program is converted into the semantic equivalent MSVL program by making conversion rules of different grammatical structure through a plurality of additional auxiliary means, so that correctness of a source VHDL program can be ensured by carrying out simulation, model construction and verification on the equivalent MSVL program.

The invention discloses an installing verification method for an intelligent terminal application program. The method comprises the following steps: acquiring a first public key pre-stored in an intelligent terminal system layer; judging if a to-be-installed application program meets an installing condition according to the pre-stored first public key; if yes, allowing to install the to-be-installed application program; if not, forbidding the installing for the to-be-installed application program. The invention also provides a system for realizing the method. According to the installing verification method for the intelligent terminal application program provided by the invention, before the application program is installed, the pre-stored first public key of the system layer is utilized to judge if the application program meets the installing condition, and the application program can be installed when the installing condition is met, so that the application program on the terminal equipment being an authenticated legal program can be ensured; the installing for an illegal application program can be effectively prevented; the manageable and controllable terminal application can be ensured; the illegal entry and spreading of harmful information can be prevented; the benefits of operators and users can be protected.

The present invention provides a method, system and computer program for automated debugging for pre-fabricated digital synchronous hardware designs implemented in Hardware Description Language (HDL). Required information is captured by interacting with the verification environment after verification fails. This capture information is used to build a diagnosis problem where the solution is a set of logic level error sources. Using the HDL information, the error at the logic level is translated to gates, modules, statements, and signals in the HDL description. The diagnosis problem can be solved efficiently formulating a Quantified Boolean Formula (QBF) problem and also by using the hierarchical and modular nature of the HDL design during diagnosis.

The invention provides a software simulation verification method based on a Cache coherence protocol. According to the method, pseudo random test which is capable of compiling constraint models and also carrying out band constraint in a manual mode is subject to software simulation and verification; specific objects are verified, and the accuracy and defect of the protocols are fed back. The method based on software simulation comprises the following steps of: firstly determining a multi-stage coherence description mode based on an expanded Cache Coherence protocol; and subsequently realizing the software simulation verification method, counting the coverage rate and carrying out error report. With the adoption of the method, the Cache Coherence protocol in multi-stage domains in a multi-state space can be verified effectively so as to enable a protocol table to realize the establishment of corresponding logic relationship, judge whether the state transition of a system in accordance with the protocol table accords with the coherence definition through an overall checker, and primarily judge whether a mode established in accordance with the protocol table has expected properties. The model system has the remarkable advantages that counter-examples can be generated automatically so as to assist in debugging errors of the system and accelerating system diagnosis and debugging.

To aim provide a software update apparatus including an install module group (130) composed of a plurality of install modules. Each of the install modules has a function of receiving, from an external server (200), a replacement protection control module (121) to be used for updating a protection control module (120) having a function of verifying whether a predetermined application has been tampered with. Each of the install modules simultaneously running is verified by at least another one of the install modules simultaneously running, as to whether the install module has a possibility of performing malicious operations.

The invention discloses a method for utilizing Elagamal public key algorithm to generate a software license code to solve the problem of the software license code. The method comprises steps as follows: a cipher key generating module generates a public key/private key pair with a certain length through a random cipher key generator; secondly, a host computer ID generating module computes an ID with a fixed length according to the hardware information of the host computer and by combining with a random number Rand, and a software user submits the host computer ID to a software developer; a license code computing module computes a corresponding license code according to the host computer ID and the random number Rand, the private key provided by the cipher key generating module is used for signing, and the software developer submits an ordered pair, namely, the ID and the license code, to the user; and the legality of the ID must be determined at first by a license code verification module before operating the software program, and if the ID is illegal, the program terminates.

An embodiment of the present application provides a method for verifying the signature of an application program, including: calling a target function in a preset dynamic link library; obtaining the dynamic signature information of the application program through the target function; and verifying the dynamic signature information Whether it is consistent with the first signature information pre-embedded in the dynamic link library; if not, close the application program; if consistent, run the application program. In the embodiment of the present application, the dynamic signature information of the application program is acquired by calling a function in the dynamic link library, and the dynamic signature information is compared with the pre-embedded first signature information. If they are inconsistent, the application program is closed. Since it is difficult to crack the dynamic link library, the method of obtaining the signature information by calling the function of the JAVA layer in the dynamic link library is also difficult to crack. This makes it difficult for counterfeiters to obtain the signature information of the application, thereby preventing the program from being repackaged.

The invention belongs to the field of computers, and relates to an automatic construction and uploading method and a device for an application program, computer equipment and a storage medium. The method comprises the steps of receiving an application program construction uploading request; acquiring a program code file according to the application program construction uploading request and transmitting the program code file to a program construction directory; acquiring program construction configuration information matched with the category of the application construction uploading request,and compiling a program code file according to the program construction configuration information to generate a compiled file; packaging the compiled file to generate a package file to be uploaded; and signing and verifying the package file, and uploading the package file to a target software platform after the package file passes the verification, thereby finishing automatic construction and uploading of the application program. According to the method provided by the invention, the links of code acquisition, compiling construction, uploading review and the like are connected in series and integrated together, operation is carried out in an automatic mode, continuous integration can be accessed, the application program construction time can be greatly saved, and the working efficiency isimproved.

The invention discloses a method for automatically generating a device test vector and a schematic diagram net list corresponding to the device test vector and automatically performing consistency check and error analysis of a layout and a schematic diagram, namely an optimization method for increasing the verification efficiency of an electric rule file in an integrated circuit aided design software tool, and belongs to the field of the consistency verification of the layout and the schematic diagram in the integrated circuit aided design software tool. The conventional manual layout drawing, schematic diagram test vector, one-by-one net list extraction and one-by-one manual verification of the correctness of the electric rule file have large flow workload and long development time and require that engineers have better design capacity and integrally master the verification flow of a process rule file better, so that the design threshold is high, and the development period is long. The invention provides a flow method for automatically verifying the correctness of the electric rule file. Compared with the conventional manual drawing, comparison and result analysis flows in the industry, the method is easy to operate, the development efficiency is greatly increased, and subsequent frequent amendment and maintenance are facilitated.

The embodiment of the invention provides a logic design segmentation method and system, and belongs to the technical field of logic array prototype system verification, and the method specifically comprises the steps: collecting an RTL design file for describing a logic circuit; performing grammatical analysis processing on the RTL design file, extracting an always object and an assign object in the logic model object, respectively packaging, constructing and generating a hypergraph data structure, performing attribute analysis, processing according to the clock domain information to obtain operation frequency information, and performing associated storage on the clock domain information domain and the operation frequency information and corresponding nodes; and performing segmentation processing to obtain corresponding grouped data. By means of the processing scheme, other processing at the back end of the process is not affected, the segmentation duration is shortened, the segmentation efficiency is improved, meanwhile, efficient, reasonable and correct segmentation processing is conducted on the chip design logic content, the performance and efficiency of design segmentation aregreatly improved, then the process of user front-end function verification is accelerated, and the appearance of integrated circuit products is accelerated.