114 results about "Formal verification" patented technology

The invention relates to the field of chip verification, and provides a chip verification method, device and equipment, a medium and a chip. The method comprises the following steps: establishing a dynamic simulation verification environment of a to-be-verified design, and generating a plurality of test scenes and corresponding test excitation according to a design specification definition; sending the test excitation to a driver through a sequencer, converting the test excitation into a signal conforming to a to-be-verified design interface protocol by the driver, and transmitting the signal to the to-be-verified design; the monitor collects an input signal and an output signal of a to-be-verified design in real time, converts the input signal and the output signal into transactions, and transmits the transactions to the scoreboard; comparing the reference model with an output signal of the to-be-verified design to generate a dynamic simulation verification result; according to the dynamic simulation result, the state space is reduced, state space traversal is carried out on a design part which is not covered by dynamic simulation in the design to be verified, and a formal verification analysis result is generated; and evaluating the to-be-verified design according to the formal verification analysis result.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

A neural-symbolic hybrid system for generating binary document formats directly from natural language input comprises a binary-aware hierarchical tokenizer operating across four levels (binary bytes, structural elements, semantic content, and concepts), a constraint satisfaction engine with 64 parallel processing cores for enforcing structural integrity and mathematical consistency, format-specific processors for Excel, PowerPoint, PDF, and CAD documents, and a formal verification system generating mathematical proofs of correctness. The system includes custom AI Document Generation Processor (AIDGP) silicon spanning 600 mm2 with specialized cores providing 500 TOPS processing power. Performance characteristics include 99.7% structural accuracy, 100% format compliance, 15.3 second average generation time for complex documents, and distributed capacity of 1,000,000 documents per hour. The system eliminates intermediate conversion steps while maintaining semantic preservation through hardware-accelerated constraint satisfaction and formal verification engines ensuring structural integrity, format compliance, and security through AES-256 encryption and automated regulatory compliance across 25+ international standards.

The invention belongs to the technical field of Internet of Things security, and particularly relates to a multi-level Internet of Things equipment security management and access control method, which comprises the following steps of: performing bidirectional verification on a digital certificate and a hardware fingerprint through an edge node when equipment is accessed; calculating credibility in real time and dynamically dividing security levels by using a hybrid evaluation algorithm based on equipment operation context data; a fine-grained access strategy is generated in combination with equipment attributes and environmental risks, and cross-level collaboration is realized through a lightweight protocol; abnormal behaviors are detected in real time in the access process, and high-risk operation is blocked within milliseconds; and strategy conflict resolution and adaptive optimization are realized through formalized verification and deep reinforcement learning. According to the technical scheme, the identity authentication reliability, the authority dynamic adaptability, the strategy consistency and the threat response speed of the Internet of Things equipment are remarkably improved, and a systematic security guarantee is provided for large-scale Internet of Things applications with high security requirements.

The invention relates to the technical field of block chains and security technologies, and particularly provides a security protection detection method and system for a smart contract based on a block chain. The security indexes at least comprise a password economics security index, a dynamic behavior characteristic index, a formalized verification index and a consensus layer security index; and performing quantitative evaluation on the collected multi-dimensional security index to obtain a comprehensive security score of the target block chain, scoring the cryptoeconomics security index through a preset cryptoeconomics security index scoring model to obtain a cryptoeconomics security score, and sending the cryptoeconomics security score to the target block chain. The current comprehensive security score of the target block chain is compared with the adaptive dynamic risk threshold, and if the current comprehensive security score is higher than the adaptive dynamic risk threshold, an early warning signal is sent out, and the effect of comprehensively evaluating the block chain smart contract is achieved.

The invention relates to the technical field of industrial control, and provides an industrial control logic intelligent generation system and method. The multi-modal input module is used for acquiring multi-modal data for a to-be-controlled process; the domain knowledge graph module is used for storing a pre-constructed knowledge graph; the preprocessing module is used for preprocessing the multi-modal data based on a pre-constructed knowledge graph; the controlled logic generation module is used for generating a logic control intermediate representation for a to-be-controlled process through a large language model according to the preprocessed multi-modal data; the formalized verification and interaction module is used for carrying out formalized verification on the logic control intermediate representation; and the target file generation and output module is used for compiling the logic control intermediate representation which is qualified through formalization verification into a control logic file aiming at the target platform. Under the constraint of the domain knowledge graph, the large language model can generate flexible and high-adaptability industrial control logic according to background knowledge to accurately adapt to different process requirements.

The invention discloses an awareness perception quantum gravitational nerve acceleration unified computing platform and method based on formalized verification, and belongs to the field of high-performance computing, medical AI and quantum information processing. A quantum gravitational coupling neural processing unit (QGCNPU); a consciousness information integral calculation core (phi ICC); formalizing a receipt chain verifier (FRCV); and the mirror reflection symmetry correction module (MRSCM) is used for eliminating the continuous projection mistake and the discrete Boolean mistake through topological equivalence verification of a local observer and a global GodCam visual angle. The system adopts an FPGA + ASIC + quantum processor three-layer heterogeneous architecture, and supports real-time pathological modeling (precision gt; gt) of neurodegenerative diseases such as Alzheimer's disease, Parkinson's disease and ALS; 99.7%), drug target discovery (acceleration by 50 times) and consciousness state monitoring (time resolution lt; and meanwhile, the mathematical proving performance and the clinical auditing performance of the calculation process are ensured, and the requirements of the global 152 billion dollar neural science and technology market and the 89 billion dollar quantum calculation industry are met.

The invention discloses an AI knowledge base continuous optimization system and method based on man-machine cooperation and closed-loop feedback. The continuous optimization system for the AI knowledge base comprises a multi-mode co-emotion knowledge input module, a knowledge active discovery and construction module, a layered depth inference engine, a response generation module oriented to a specific scene, an output formal verification and interpretability analysis module, a dynamic resource scheduling and reflection module and a man-machine collaborative feedback interface. A feedback data deep analysis module, a knowledge base dynamic update and conflict resolution module and a model increment optimization and security alignment module. Through the mode, the systematic system which has the capabilities of active learning, deep reasoning, self-verification and efficient man-machine cooperation and can realize continuous self-optimization of the knowledge base is provided.

The invention provides a chip design verification method and system, electronic equipment and a storage medium. The chip design verification method comprises the following steps: acquiring a design file of a chip and a design stage corresponding to the design file; selecting a target collaborative verification mode matched with the design stage from a plurality of collaborative verification modes; wherein the cooperative verification mode comprises a mode for verifying the design file through cooperation between logic simulation verification and form verification; the collaborative verification modes corresponding to different design stages are different, and the collaborative modes between logic simulation verification and form verification in the different collaborative verification modes are different; and verifying the design file based on the target collaborative verification mode. According to the method, logic simulation verification and formal verification work cooperatively, and respective advantages are combined for complementation, so that the efficiency and effectiveness of chip design and verification are improved.

The invention relates to the technical field of software engineering and artificial intelligence, and discloses a high-credibility programming agent system and method based on a large model and a formalization method. A high-credibility programming agent system based on a large model and a formalization method comprises an agent core module used for providing common perception, memory, decision and execution capabilities for various professional agents; the multi-agent cooperation module is constructed on the agent core module and comprises a coding agent, a form analysis agent and a form verification agent; the coding agent is responsible for generating, complementing, reconstructing and optimizing program codes based on natural language requirements or contexts. The system realizes full-process automation from demand understanding to code generation, analysis, verification and restoration through autonomous planning and multi-task execution capability of the intelligent agent, reduces manual intervention links, and remarkably shortens the development period.

The present disclosure provides a Boolean formula unsatisfiability core prediction method based on hypergraph modeling. A CNF formula generated by a software and hardware formal verification problem coding in the field of electronic design automation is received from the outside, input into a hypergraph representation learning model, and modeling for solving a SAT problem corresponding to the software and hardware formal verification problem is obtained. The model is constructed in the following manner: first, SAT problem representation based on hypergraph is performed. Specifically, the CNF formula is modeled as a clause-literal hypergraph by using a SAT problem modeling method based on hypergraph and a message passing method based on hypergraph, and a clause correlation graph is further constructed to obtain problem representation. Then, a polarity-aware variable decomposition method is applied to the clause correlation graph, and the problem representation is structured and modeled. The hypergraph representation learning model is trained by using a training method based on polarity-aware consistency constraints, and is integrated with a SAT problem solver, so that the model can be used to solve the problems that the existing graph neural network-based SAT learning method has in the aspects of polarity modeling and high-order structure expression.

The application discloses a circuit input sensitivity analysis method based on Undef SAT, which comprises five steps of netlist analysis and input division, two groups of CNF clause construction, S set assignment and initial solving, first group of solution increment SAT processing and termination and result output. The method uses the incremental SAT processing mode to gradually determine the final assignment of the input variables of the L set, effectively avoids full space search, significantly reduces the search space, and improves the analysis and determination efficiency. The method constructs two groups of CNF clauses supporting irrelevant item propagation, directly processes the irrelevant input variables of the S set by using the Undef SAT solver, reduces the number of logic propagation, and thus reduces the operation time. The integrated process of the circuit input sensitivity analysis formed by the method is suitable for mainstream EDA tool chains, has good engineering applicability, and is suitable for different scenes such as logic synthesis stage, formal verification, functional equivalence checking and loop oscillation detection.

This invention belongs to the interdisciplinary field of digital twins and artificial intelligence, specifically disclosing an automatic generation method for manufacturing equipment control logic based on neural-symbolic collaboration and intermediate representation verification. This method utilizes a neural-symbolic collaboration strategy, employing four-element semantic model constraints and thought chain reasoning to transform unstructured natural language process instructions into structured hierarchical state machine (HSM) intermediate representations. Through linear temporal logic (LTL) formal verification and graph theory connectivity analysis, static security verification of the control logic is performed, effectively improving the system's temporal determinism and deadlock resistance. Based on this, the system performs dynamic physical simulation in a digital twin environment, extracting spatial coordinate deviations when mechanical interference occurs, and inversely mapping these deviations into structured error correction prompts, which are then fed back to the large language model for logic reconstruction. This invention constructs a cross-modal "generation-verification-correction" closed-loop mechanism, achieving deep integration of model cognitive intent and underlying physical space constraints, ultimately deterministically compiling the verified intermediate representation into highly reliable industrial standard control code.

This invention discloses a live-cell analysis method and system based on a large model and formal verification. The method includes context injection and intent reasoning, receiving natural language and analyzing it using a large language model to infer the required algorithm modules and output candidate configuration files. Formal logical verification involves reading the candidate configuration files and converting them into standardized logical constraint code, which is then verified by a solver. Conflict self-healing and iteration are implemented: if the solver verification fails, the conflict core is identified, and the connection method of the candidate configuration file or algorithm module is modified according to an arbitration strategy, while updating the logical constraint code until the solver verification passes. An analysis pipeline is instantiated and constructed: if the solver verification passes, an executable analysis pipeline is built based on the final determined candidate configuration files for live-cell analysis. Analysis code is generated using a large language model and logically verified using formal methods to analyze live-cell microscopic images.

Systems and methods for mathematical modeling of the hardware and software stack of commodity computer platforms are provided, enabling provable guarantees on memory, device, and program execution. This approach addresses the technical problem of reliance on system agents that rely on implicit trust in the operating environment, which can be exploited by sophisticated attackers using complex threats such as memory access exploits and code / data integrity exploits. The solution provides a proactive, mathematically-backed security solution that eliminates entire classes of cyberattacks by design, ensuring realizable guarantees on commodity computer platforms running hardware and software stack elements at the lowest operating level. This approach has significant advantages over current reactive cybersecurity methods, including reduced complexity and overhead, and increased confidence in the integrity of the system. The solution's main uses include providing mathematically-backed security and availability guarantees for critical infrastructure, financial institutions, and other organizations vulnerable to cyberattacks.

This invention relates to a reliable translation method for synchronous dataflow languages ​​based on the 8114 criterion, belonging to the field of code generation. The invention obtains the abstract syntax tree of the Ctemp intermediate language through lexical and syntactic analysis and translation of Lustre source code; it traverses the Ctemp abstract syntax tree and designs translation methods for control flow statements and assignment statements within the tree structure; it traverses expressions within statements and designs translation methods that add type casting to ensure that statements are semantically correct while avoiding implicit type conversions; it extends the theorem on type relations in Cltype for verifying type operations; and it extends the theorem on type casting and binary operations in Ctemp semantics to achieve semantic formal verification. This invention significantly improves the compliance of C code generated by code generation tools with the GJB 8114 specification.

The invention relates to the technical field of formal verification, and provides a convolutional neural network robustness verification method and device based on abstract interpretation. The method comprises the following steps: adding preset disturbance into a plurality of input pictures to obtain corresponding disturbance images; converting the disturbance image into a range value matrix, and taking the range value matrix as an abstract element; performing abstract transformation on each network layer of the neural network to be tested to obtain a transformed network; performing neural network propagation on the abstract elements in the converted network to obtain output data; according to the labels of the multiple input pictures and the corresponding output data, the correct classification proportion of the converted network is verified so as to calculate the robustness score of the neural network to be tested, and the problem that the coverage rate and effectiveness of testing a neural network model are poor due to the fact that exhaustion traversal type testing cannot be used is solved.

The application discloses a kind of big model reinforcement learning network configuration generation methods based on verification feedback, input network phenomenon and state content are converted into semantic and action sequence by network configuration semantic analysis, based on semantic action sequence, through hybrid action space strategy generation and neural symbol collaborative reinforcement learning model, the configuration framework and parameter that meet the requirements are generated, the network configuration information generated is verified and fed back in digital twin system, formal verification and performance simulation are carried out in virtual environment, real network scene is simulated, the correctness and performance of configuration are comprehensively evaluated, and then feedback signal containing multidimensional information is generated, strategy model is modified and optimized according to digital twin verification, finally, through reward mechanism, intelligent agent is guided to adjust high-entropy configuration item, and optimization configuration generation big model.

The embodiment of the invention relates to the technical field of computers, and discloses a constraint perception code generation method based on multilayer verification feedback, and the method comprises the steps: obtaining a code generation request; according to the code generation request, inputting the code generation request into a code generation agent based on a constrained Markov decision process, and outputting a current code; inputting the current code into a multi-layer verification engine, and respectively performing static analysis and formalized verification to obtain a current verification result and a current feedback signal; when the current verification result is not passed, sending the current verification result and the current feedback signal to a code generation agent, iteratively executing the generation of a modified code and the static analysis and formalized verification of the multi-layer verification engine to obtain a modified verification result and a modified feedback signal, and when the verification is not passed, regenerating the code. And obtaining the target code until the verification result is that the verification is passed. According to the embodiment of the invention, the effect of accurately generating codes is realized.

The present application belongs to the technical field of network security and artificial intelligence, and provides a large language model driven password protocol automatic formalization modeling method and system, acquires a natural language protocol specification document, and performs preprocessing; according to the priority order of a message block, a verification block and a calculation statement, a large language model extracts corresponding semi-structured intermediate representations from text blocks; all intermediate representation statements are scanned at one time by using the large language model, protocol functions and symbols are identified and stored in a knowledge base, the large language model is driven in units of intermediate representation statements to be refined one by one, and global context and local context are extracted; the completely structured intermediate representations, a protocol role set and the updated knowledge base are taken as inputs to perform deterministic one-to-one mapping with formal verification tool code, and conversion is completed. The present application can automatically generate symbol model code which can be directly input into a formal verification tool.

The invention discloses a formal verification method and system for a deep reinforcement learning charging strategy, and the method comprises the steps: constructing a mixed integer abstract domain, and mapping a continuous state space in an operation scene of an electric vehicle charging station into abstract elements; modeling a deep reinforcement learning network and random environment dynamics into an abstract converter on the mixed integer abstract domain; within a preset time step length, starting from an initial abstract element, alternately iteratively applying the abstract converter of the deep reinforcement learning network and the abstract converter of the random environment dynamics to obtain a final abstract element; and converting the symbol constraint in the final abstract element into a specific mixed integer programming problem by taking the lower bound of the strategy accumulation reward as a target function, and solving by using an MIP solver. According to the method, the uncertainty caused by environment randomness can be overcome, and the safety verification precision and reliability of an intelligent charging strategy in a complex vehicle network interaction scene are remarkably improved.

The invention discloses a low-altitude aircraft endogenous safety navigation system and method based on formalized verification, and belongs to the field of aviation safety key systems. According to the system, the first low-altitude aircraft endogenous safety navigation system passing formalized verification in the world is constructed, the core is that'endogenous credibility 'is defined as the unified measurement of system output, and a five-dimensional credibility enhancement engine is innovatively provided. The endogenous credibility is generated and continuously verified through the synergistic effect of the physical unclonable fingerprint of the signal layer, the anti-quantum trust chain of the data layer, the mathematical proof stability of the algorithm layer, the causal traceable evaluation of the decision-making layer and the dynamic minimum permission strategy of the control layer. Through fourth-level conformity verification of the Chinese civil aviation bureau, the integrity risk probability of the system in 2000-hour continuous testing is 8.3 * 10 / hour and is improved by two orders of magnitude compared with the DO-365C standard, and the limit of the prior art is substantially exceeded. According to the invention, through tight integration of hardware and software, the problems of loss of trust roots and incomplete verification in navigation of the low-altitude aircraft are solved, and qualitative leap of safety performance is realized.

The invention relates to a cross-chain protocol generation method and system based on a large language model, and the method comprises the steps: obtaining the technical data of two heterogeneous block chains corresponding to a cross-chain operation, and building the chain feature information for each block chain based on the technical data; inputting the chain feature information and the user intention into a trained protocol packet generation model, so that the protocol packet generation model and a preset formal verification rear end carry out interactive verification and code repair, and an initial protocol packet is obtained; the initial protocol packet comprises an intelligent contract code corresponding to the service logic and a formalized proof script; inputting the initial protocol packet into the trained security monitoring model to obtain a target protocol packet; the target protocol packet is a protocol packet in which monitoring logic, a smart contract of a built-in circuit breaker and a security governance contract are added on the initial protocol packet. According to the method, the development efficiency is improved, the error rate is reduced, and the security of a formalized verification level is improved.

This invention discloses a verification device and method for a background mechanism cyclic redundancy check (CRC) algorithm, relating to the field of integrated circuit verification technology. It introduces formal verification to automatically exhaustively enumerate the input state space, comparing the calculation results of the hardware design RTL with the software golden reference model and generating a difference report. Based on formal verification, simulation verification is performed, constructing a competition scenario between the master end (at the same communication level as the background CRC calculation module) and the slave end (relative to the background CRC calculation module). Simulation verification is executed, cross-covering different combinations of master end functions. Interrupt monitoring detects the presence of verification errors, achieving comprehensive verification of the background mechanism, calculation, and error notification functions of the verification object from memory access to memory data loading to output data verification results. Finally, regression management encapsulates formal verification and simulation verification into a parameter-passable regression task, transforming verification into a reliable and automated solution.

This invention discloses a cloud-edge-airborne collaborative intelligent flight management system and method. The system includes: a cloud brain decision center for generating and evolving a global flight strategy knowledge graph based on hierarchical federated meta-reinforcement learning; an edge intelligent collaborative network whose nodes possess multimodal threat causal prediction and distributed collaborative decision-making capabilities based on graph neural networks and game theory; and an airborne autonomous safety agent integrating a trusted execution environment and formal verification, employing a hierarchical-reflective adaptive controller with independent reflection layers. The system ensures trusted data synchronization across layers through a blockchain-enabled decentralized data lake and achieves closed-loop collaborative evolution of strategies, models, and control logic based on a digital twin simulation environment. This method realizes autonomous intelligent management from global strategy optimization and local real-time collaboration to airborne safety execution, significantly improving flight safety, efficiency, and system adaptability in complex airspace.

An example operation may include one or more of receiving a logical model of a circuit written in a hardware description language (HDL), the logical model of the circuit comprising normalized and ratioed clocks, and simulation-efficient edge-triggered latches or flip-flops, translating the logical model of the circuit into a physical model of the circuit in the HDL via a software application, wherein the translating comprises replacing the normalized and ratioed clocks in the logical model of the circuit with a base system clock, divider logic generating hold waveforms to achieve ratioed behavior, and pulse-enabled latches, and replacing the edge-triggered latches or flip-flops with pulse-generation logic and pulse-enabled latches, executing a formal verification which determines whether the logical model of the circuit is functionally equivalent to the physical model of the circuit, and displaying results of the formal verification via a graphical user interface (GUI) of the software application.

This invention discloses a knowledge-driven automated formal verification method and system for smart contracts, belonging to the fields of blockchain and artificial intelligence technology. First, it constructs a formal verification language knowledge graph and an expert experience knowledge graph to extract grammatical rules, vulnerability patterns, and verification logic. Then, it performs project preprocessing and static analysis on the target smart contract to extract an abstract syntax tree, call relationships, and system model. Combining the knowledge graph and large language model, it automatically generates formal verification constraints and executes the verification task through a formal verifier. For errors and counterexamples generated during the verification process, the system uses a feedback mechanism to repair rules and optimize parameters. Finally, it generates a formal verification report containing verification results, risk analysis, and remediation suggestions. This invention achieves full-process automation from verification requirement generation to verification execution and optimization, effectively improving the efficiency and accuracy of smart contract security verification.

This invention discloses a formal verification method for processor branch prediction attack vulnerabilities, comprising the following steps: S1, establishing the security attributes violated by the branch prediction attack, wherein the security attributes describe the security specifications that a secure branch predictor design should comply with; S2, establishing a branch prediction behavior model, describing the branch prediction attack as a combination of a series of abstract branch operations; wherein the branch operation is a quintuple consisting of operator, operation type, operation address, jump direction, and jump address, which is an abstract representation of a certain branch instruction; S3, modeling the branch predictor design as accepting branch prediction behavior instructions, and designing different variations of the branch prediction model state machine according to different input instructions, outputting the prediction result, checking the security specifications, and converting the branch prediction attack into a path specification on the state machine; S4, performing model verification on the state machine of the branch predictor design to determine whether it has a branch prediction attack vulnerability.