158 results about "Formal verification" patented technology

The invention relates to the field of chip verification, and provides a chip verification method, device and equipment, a medium and a chip. The method comprises the following steps: establishing a dynamic simulation verification environment of a to-be-verified design, and generating a plurality of test scenes and corresponding test excitation according to a design specification definition; sending the test excitation to a driver through a sequencer, converting the test excitation into a signal conforming to a to-be-verified design interface protocol by the driver, and transmitting the signal to the to-be-verified design; the monitor collects an input signal and an output signal of a to-be-verified design in real time, converts the input signal and the output signal into transactions, and transmits the transactions to the scoreboard; comparing the reference model with an output signal of the to-be-verified design to generate a dynamic simulation verification result; according to the dynamic simulation result, the state space is reduced, state space traversal is carried out on a design part which is not covered by dynamic simulation in the design to be verified, and a formal verification analysis result is generated; and evaluating the to-be-verified design according to the formal verification analysis result.

The invention discloses a causal control VLA end-to-end system fusing perception and a world model, and belongs to the technical field of automatic driving. The system comprises a perception and world modeling subsystem; a reasoning and generating subsystem; a verification and collaborative learning subsystem; moreover, the perception and world modeling subsystem is composed of an environment perception module and a world model training module, the reasoning and generation subsystem is composed of a causal modeling module and a diffusion trajectory generation module, and the verification and collaborative learning subsystem is composed of a form verification module and a federal collaborative distillation module. According to the VLA end-to-end system, traditional correlation modeling of a world model is enhanced through causal modeling, so that the world model becomes more accurate; meanwhile, on the basis of traditional verification and updating of the world model, the verification and updating process of the world model generation trajectory is further enhanced through the verification and collaborative learning subsystem, so that the generated trajectory is safer and more reliable.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

A neural-symbolic hybrid system for generating binary document formats directly from natural language input comprises a binary-aware hierarchical tokenizer operating across four levels (binary bytes, structural elements, semantic content, and concepts), a constraint satisfaction engine with 64 parallel processing cores for enforcing structural integrity and mathematical consistency, format-specific processors for Excel, PowerPoint, PDF, and CAD documents, and a formal verification system generating mathematical proofs of correctness. The system includes custom AI Document Generation Processor (AIDGP) silicon spanning 600 mm2 with specialized cores providing 500 TOPS processing power. Performance characteristics include 99.7% structural accuracy, 100% format compliance, 15.3 second average generation time for complex documents, and distributed capacity of 1,000,000 documents per hour. The system eliminates intermediate conversion steps while maintaining semantic preservation through hardware-accelerated constraint satisfaction and formal verification engines ensuring structural integrity, format compliance, and security through AES-256 encryption and automated regulatory compliance across 25+ international standards.

The invention belongs to the technical field of Internet of Things security, and particularly relates to a multi-level Internet of Things equipment security management and access control method, which comprises the following steps of: performing bidirectional verification on a digital certificate and a hardware fingerprint through an edge node when equipment is accessed; calculating credibility in real time and dynamically dividing security levels by using a hybrid evaluation algorithm based on equipment operation context data; a fine-grained access strategy is generated in combination with equipment attributes and environmental risks, and cross-level collaboration is realized through a lightweight protocol; abnormal behaviors are detected in real time in the access process, and high-risk operation is blocked within milliseconds; and strategy conflict resolution and adaptive optimization are realized through formalized verification and deep reinforcement learning. According to the technical scheme, the identity authentication reliability, the authority dynamic adaptability, the strategy consistency and the threat response speed of the Internet of Things equipment are remarkably improved, and a systematic security guarantee is provided for large-scale Internet of Things applications with high security requirements.

The invention provides a method and a system for automatically checking and correcting a PCB (Printed Circuit Board) design rule, belonging to the technical field of PCB design. The method comprises the following steps of: analyzing data such as texts, images and tables in a PCB design document through a multi-modal large model, extracting a structured signal information table, automatically generating a dynamically adaptive checking rule, and automatically checking and correcting the PCB design rule. Comprising bit width check, connectivity verification and functional analysis. And the generated rule is optimized by combining a retrieval enhancement generation (RAG) technology with a verification rule base, so that the coverage is comprehensive and the accuracy is high. The system further evaluates the rule through a form verification tool, automatically corrects potential defects, and improves the quality and adaptability of the rule. According to the method, the efficiency and accuracy of PCB design inspection are remarkably improved, the manual intervention requirement is reduced, the method can be widely applied to complex electronic design scenes, and the rapid changing technology and market requirements are met.

The invention relates to the technical field of block chains and security technologies, and particularly provides a security protection detection method and system for a smart contract based on a block chain. The security indexes at least comprise a password economics security index, a dynamic behavior characteristic index, a formalized verification index and a consensus layer security index; and performing quantitative evaluation on the collected multi-dimensional security index to obtain a comprehensive security score of the target block chain, scoring the cryptoeconomics security index through a preset cryptoeconomics security index scoring model to obtain a cryptoeconomics security score, and sending the cryptoeconomics security score to the target block chain. The current comprehensive security score of the target block chain is compared with the adaptive dynamic risk threshold, and if the current comprehensive security score is higher than the adaptive dynamic risk threshold, an early warning signal is sent out, and the effect of comprehensively evaluating the block chain smart contract is achieved.

The invention relates to the technical field of industrial control, and provides an industrial control logic intelligent generation system and method. The multi-modal input module is used for acquiring multi-modal data for a to-be-controlled process; the domain knowledge graph module is used for storing a pre-constructed knowledge graph; the preprocessing module is used for preprocessing the multi-modal data based on a pre-constructed knowledge graph; the controlled logic generation module is used for generating a logic control intermediate representation for a to-be-controlled process through a large language model according to the preprocessed multi-modal data; the formalized verification and interaction module is used for carrying out formalized verification on the logic control intermediate representation; and the target file generation and output module is used for compiling the logic control intermediate representation which is qualified through formalization verification into a control logic file aiming at the target platform. Under the constraint of the domain knowledge graph, the large language model can generate flexible and high-adaptability industrial control logic according to background knowledge to accurately adapt to different process requirements.

The invention relates to the technical field of software security, in particular to a high-credibility construction of a synchronous modeling language code generator and a formalized verification method and device thereof, electronic equipment and a medium, and the method comprises the following steps: obtaining a synchronous modeling language source program generated by the code generator; translating the synchronous modeling language source program to the abstract syntax tree; converting the abstract syntax tree into an intermediate representation, and converting the current intermediate representation into a next intermediate representation; and performing formalized verification on each transformation process until the translation process verification of all the language features of the synchronous modeling language source program is completed, and the formalized verification comprises the steps that each intermediate representation formalized definition has operation semantics meeting semantic certainty, and semantic retentivity is proved for the current intermediate representation transformation process. Therefore, the problems that related technologies only support partial language characteristics, compiling architecture design is simple, the formalized verification range is limited, and the requirements for complete modeling ability and high credibility are difficult to meet are solved.

The invention discloses a verification feedback-based large model reinforcement learning network configuration generation method, which comprises the following steps of: converting input network phenomena and state contents into a semantic and action sequence through network configuration semantic analysis; the method comprises the following steps: generating a configuration framework and parameters meeting requirements through a hybrid action space strategy generation and neural symbol collaborative reinforcement learning model, verifying and feeding back the generated network configuration information in a digital twin system, simulating a real network scene through formalized verification and performance simulation in a virtual environment, and establishing a network configuration model. According to the method, the correctness and the performance of configuration are comprehensively evaluated, then a feedback signal containing multi-dimensional information is generated, a strategy model is corrected and optimized according to digital twinborn verification, and finally, an intelligent agent is guided to adjust a high-entropy configuration item through a reward mechanism, and configuration is optimized to generate a large model.

The invention discloses an awareness perception quantum gravitational nerve acceleration unified computing platform and method based on formalized verification, and belongs to the field of high-performance computing, medical AI and quantum information processing. A quantum gravitational coupling neural processing unit (QGCNPU); a consciousness information integral calculation core (phi ICC); formalizing a receipt chain verifier (FRCV); and the mirror reflection symmetry correction module (MRSCM) is used for eliminating the continuous projection mistake and the discrete Boolean mistake through topological equivalence verification of a local observer and a global GodCam visual angle. The system adopts an FPGA + ASIC + quantum processor three-layer heterogeneous architecture, and supports real-time pathological modeling (precision gt; gt) of neurodegenerative diseases such as Alzheimer's disease, Parkinson's disease and ALS; 99.7%), drug target discovery (acceleration by 50 times) and consciousness state monitoring (time resolution lt; and meanwhile, the mathematical proving performance and the clinical auditing performance of the calculation process are ensured, and the requirements of the global 152 billion dollar neural science and technology market and the 89 billion dollar quantum calculation industry are met.

Embodiments of the present disclosure include a formal verification method comprising a plurality of custom generative AI-based tools configured in a bottoms up methodology to generate formal verification code using an LLM. In another embodiment, the present disclosure includes a generative AI-based tool architecture comprising an index of code examples. A query from a user is used to retrieve code examples, and the query and code examples are sent to an LLM to generate code corresponding to the query.

The invention provides a vehicle part interaction logic verification file generation method and an interaction logic verification method, and relates to the technical field of formal verification. The method comprises the following steps: acquiring multi-modal data of vehicle parts; analyzing the multi-modal data of the vehicle parts to obtain vehicle model information; according to the vehicle model information, respectively generating a vehicle part state transition path set and a linear sequential logic rule set; and generating an executable interaction logic verification file based on the vehicle component state transition path set and the linear sequential logic rule set. The vehicle model information is obtained based on the multi-modal data, the vehicle part state transition path set and the linear sequential logic rule set are automatically generated according to the vehicle model information, and the verification accuracy of interaction logic between vehicle parts is improved.

The application discloses a kind of causal control VLA end-to-end systems of fusion perception and world model, belong to the technical field of automatic driving;The system includes: perception and world modeling subsystem;Reasoning and generation subsystem;Verification and collaborative learning subsystem;And, perception and world modeling subsystem is constituted by environment perception module and world model training module, reasoning and generation subsystem is constituted by causal modeling module and diffusion trajectory generation module, verification and collaborative learning subsystem is constituted by formal verification module and federal collaborative distillation module;The VLA end-to-end system of the application, through causal modeling, enhances the traditional correlation modeling of world model, so that the world model becomes more accurate;At the same time, on the basis of traditional verification and updating of world model, the verification and updating process of trajectory generated by world model is further strengthened through verification and collaborative learning subsystem, so that the generated trajectory is more safe and reliable.

The invention provides a formal verification method and device for state transition implementation codes and a program product, and the method comprises the steps: compiling a first state transition function implemented by a C language Switch Case statement to obtain a bit code file; obtaining a Cryptol file, wherein the Cryptol file comprises a second state transfer function which is realized by using a Cryptol programming language; acquiring a first input parameter set and a first output value set corresponding to the first state transfer function, and acquiring a second input parameter set and a second output value set corresponding to the second state transfer function; simulating state transition function symbolic execution based on the first output value set, the second output value set, the first input parameter set and the second input parameter set, converting the state transition function symbolic execution into a satisfiability model theory problem, and solving the satisfiability model theory problem through an external solver to obtain a verification result of a state transition implementation code; the problem that whether state transition is implemented correctly or not cannot be guaranteed only through a manual checking mode can be solved, and the state transition code implementation correctness is guaranteed.

The invention discloses an AI knowledge base continuous optimization system and method based on man-machine cooperation and closed-loop feedback. The continuous optimization system for the AI knowledge base comprises a multi-mode co-emotion knowledge input module, a knowledge active discovery and construction module, a layered depth inference engine, a response generation module oriented to a specific scene, an output formal verification and interpretability analysis module, a dynamic resource scheduling and reflection module and a man-machine collaborative feedback interface. A feedback data deep analysis module, a knowledge base dynamic update and conflict resolution module and a model increment optimization and security alignment module. Through the mode, the systematic system which has the capabilities of active learning, deep reasoning, self-verification and efficient man-machine cooperation and can realize continuous self-optimization of the knowledge base is provided.

The invention discloses a verification device and a verification method for a background mechanism cyclic redundancy check algorithm, and relates to the technical field of integrated circuit verification, a formalized verification automatic exhaustion input state space is introduced, calculation results of a hardware design RTL and a software golden reference model are compared, and a difference report is formed; performing simulation verification on the basis of formalized verification, constructing a competition scene of the master end and the background CRC calculation module which are located at the same communication level as the background CRC calculation module relative to slave end equipment, executing simulation verification, crosswise covering different master end function combinations, and finding whether a verification error exists or not through monitoring interruption; the comprehensive verification of the background mechanism, the calculation and the error notification function of the verification object is realized in the process from initiating the memory access to loading the memory data to outputting the data verification result. And finally, packaging the formalized verification and the simulation verification into a regression task which can be executed through parameter transmission through regression management, and converting the verification into a reliable operation automation scheme.

The invention provides a chip design verification method and system, electronic equipment and a storage medium. The chip design verification method comprises the following steps: acquiring a design file of a chip and a design stage corresponding to the design file; selecting a target collaborative verification mode matched with the design stage from a plurality of collaborative verification modes; wherein the cooperative verification mode comprises a mode for verifying the design file through cooperation between logic simulation verification and form verification; the collaborative verification modes corresponding to different design stages are different, and the collaborative modes between logic simulation verification and form verification in the different collaborative verification modes are different; and verifying the design file based on the target collaborative verification mode. According to the method, logic simulation verification and formal verification work cooperatively, and respective advantages are combined for complementation, so that the efficiency and effectiveness of chip design and verification are improved.

The invention relates to the technical field of software engineering and artificial intelligence, and discloses a high-credibility programming agent system and method based on a large model and a formalization method. A high-credibility programming agent system based on a large model and a formalization method comprises an agent core module used for providing common perception, memory, decision and execution capabilities for various professional agents; the multi-agent cooperation module is constructed on the agent core module and comprises a coding agent, a form analysis agent and a form verification agent; the coding agent is responsible for generating, complementing, reconstructing and optimizing program codes based on natural language requirements or contexts. The system realizes full-process automation from demand understanding to code generation, analysis, verification and restoration through autonomous planning and multi-task execution capability of the intelligent agent, reduces manual intervention links, and remarkably shortens the development period.

The invention discloses an arbitration-based automatic driving decision-making method, system and device and a storage medium. The method comprises the steps of heterogeneous parallel sensing and planning calculation, and synchronous starting of two independent calculation assembly lines; performing unified representation and space-time alignment, and performing standardization processing on output of the two calculation assembly lines; certified security arbitration and decision making are carried out, and security verification and utility evaluation are carried out on each candidate track output by the main brain; performing control execution and global health monitoring, and sending the selected track to a vehicle controller for execution; and performing off-line closed-loop self-evolution, retraining and optimizing the model, and updating and deploying the model to a vehicle end system through OTA. According to the method, a heterogeneous double-brain system integrating an end-to-end AI model and a traditional rule model is constructed, and a certifiable safety arbitration mechanism with strict formalized verification capability is introduced, so that the absolute safety, dynamic reliability and continuous self-evolution of an automatic driving decision are ensured while the AI performance advantages are fully played.

The invention relates to the technical field of block chain technology and education data management, and discloses an education data management system and method based on a block chain, and the method comprises the steps: constructing an education business field specific language, and training an education business intention understanding model; applying a constraint solving algorithm to solve the smart contract parameters meeting various constraint conditions, and generating a smart contract code meeting multi-objective optimization; performing multi-level formalized verification on the generated intelligent contract code; constructing an educational policy and regulation knowledge base and calculating a contract policy compliance score; implementing a hierarchical transition strategy; the system is constructed based on a domestic Feiteng processor and a Kylin operating system, and stable operation and data security in an extreme environment are ensured; the technical problems of difficulty in intelligent contract development, difficulty in policy compliance evaluation and complexity in contract evolution upgrading in education data management are solved, and reliable storage, safe sharing and effective management of education data are realized.

The present disclosure provides a Boolean formula unsatisfiability core prediction method based on hypergraph modeling. A CNF formula generated by a software and hardware formal verification problem coding in the field of electronic design automation is received from the outside, input into a hypergraph representation learning model, and modeling for solving a SAT problem corresponding to the software and hardware formal verification problem is obtained. The model is constructed in the following manner: first, SAT problem representation based on hypergraph is performed. Specifically, the CNF formula is modeled as a clause-literal hypergraph by using a SAT problem modeling method based on hypergraph and a message passing method based on hypergraph, and a clause correlation graph is further constructed to obtain problem representation. Then, a polarity-aware variable decomposition method is applied to the clause correlation graph, and the problem representation is structured and modeled. The hypergraph representation learning model is trained by using a training method based on polarity-aware consistency constraints, and is integrated with a SAT problem solver, so that the model can be used to solve the problems that the existing graph neural network-based SAT learning method has in the aspects of polarity modeling and high-order structure expression.

The application discloses a circuit input sensitivity analysis method based on Undef SAT, which comprises five steps of netlist analysis and input division, two groups of CNF clause construction, S set assignment and initial solving, first group of solution increment SAT processing and termination and result output. The method uses the incremental SAT processing mode to gradually determine the final assignment of the input variables of the L set, effectively avoids full space search, significantly reduces the search space, and improves the analysis and determination efficiency. The method constructs two groups of CNF clauses supporting irrelevant item propagation, directly processes the irrelevant input variables of the S set by using the Undef SAT solver, reduces the number of logic propagation, and thus reduces the operation time. The integrated process of the circuit input sensitivity analysis formed by the method is suitable for mainstream EDA tool chains, has good engineering applicability, and is suitable for different scenes such as logic synthesis stage, formal verification, functional equivalence checking and loop oscillation detection.

This invention belongs to the interdisciplinary field of digital twins and artificial intelligence, specifically disclosing an automatic generation method for manufacturing equipment control logic based on neural-symbolic collaboration and intermediate representation verification. This method utilizes a neural-symbolic collaboration strategy, employing four-element semantic model constraints and thought chain reasoning to transform unstructured natural language process instructions into structured hierarchical state machine (HSM) intermediate representations. Through linear temporal logic (LTL) formal verification and graph theory connectivity analysis, static security verification of the control logic is performed, effectively improving the system's temporal determinism and deadlock resistance. Based on this, the system performs dynamic physical simulation in a digital twin environment, extracting spatial coordinate deviations when mechanical interference occurs, and inversely mapping these deviations into structured error correction prompts, which are then fed back to the large language model for logic reconstruction. This invention constructs a cross-modal "generation-verification-correction" closed-loop mechanism, achieving deep integration of model cognitive intent and underlying physical space constraints, ultimately deterministically compiling the verified intermediate representation into highly reliable industrial standard control code.

This invention discloses a live-cell analysis method and system based on a large model and formal verification. The method includes context injection and intent reasoning, receiving natural language and analyzing it using a large language model to infer the required algorithm modules and output candidate configuration files. Formal logical verification involves reading the candidate configuration files and converting them into standardized logical constraint code, which is then verified by a solver. Conflict self-healing and iteration are implemented: if the solver verification fails, the conflict core is identified, and the connection method of the candidate configuration file or algorithm module is modified according to an arbitration strategy, while updating the logical constraint code until the solver verification passes. An analysis pipeline is instantiated and constructed: if the solver verification passes, an executable analysis pipeline is built based on the final determined candidate configuration files for live-cell analysis. Analysis code is generated using a large language model and logically verified using formal methods to analyze live-cell microscopic images.

Systems and methods for mathematical modeling of the hardware and software stack of commodity computer platforms are provided, enabling provable guarantees on memory, device, and program execution. This approach addresses the technical problem of reliance on system agents that rely on implicit trust in the operating environment, which can be exploited by sophisticated attackers using complex threats such as memory access exploits and code / data integrity exploits. The solution provides a proactive, mathematically-backed security solution that eliminates entire classes of cyberattacks by design, ensuring realizable guarantees on commodity computer platforms running hardware and software stack elements at the lowest operating level. This approach has significant advantages over current reactive cybersecurity methods, including reduced complexity and overhead, and increased confidence in the integrity of the system. The solution's main uses include providing mathematically-backed security and availability guarantees for critical infrastructure, financial institutions, and other organizations vulnerable to cyberattacks.

The invention relates to the technical field of block chains, and provides an EVM instruction set abstract semantic description method and device based on a theorem prover, electronic equipment and a computer program product. The method comprises the steps of obtaining a to-be-processed EVM instruction set; and converting the EVM instruction set into a corresponding abstract semantic description based on an inductive definition method in the theorem prover. According to the method, a theorem prover with high credibility is utilized, and instruction behaviors during operation of the EVM instruction set can be accurately and completely described mathematically, so that the accuracy of abstract semantic description for the EVM instruction set is improved, and a solid mathematical basis is provided for automatic reasoning and formalized verification of the smart contract.

This invention relates to a reliable translation method for synchronous dataflow languages ​​based on the 8114 criterion, belonging to the field of code generation. The invention obtains the abstract syntax tree of the Ctemp intermediate language through lexical and syntactic analysis and translation of Lustre source code; it traverses the Ctemp abstract syntax tree and designs translation methods for control flow statements and assignment statements within the tree structure; it traverses expressions within statements and designs translation methods that add type casting to ensure that statements are semantically correct while avoiding implicit type conversions; it extends the theorem on type relations in Cltype for verifying type operations; and it extends the theorem on type casting and binary operations in Ctemp semantics to achieve semantic formal verification. This invention significantly improves the compliance of C code generated by code generation tools with the GJB 8114 specification.

The invention relates to the technical field of formal verification, and provides a convolutional neural network robustness verification method and device based on abstract interpretation. The method comprises the following steps: adding preset disturbance into a plurality of input pictures to obtain corresponding disturbance images; converting the disturbance image into a range value matrix, and taking the range value matrix as an abstract element; performing abstract transformation on each network layer of the neural network to be tested to obtain a transformed network; performing neural network propagation on the abstract elements in the converted network to obtain output data; according to the labels of the multiple input pictures and the corresponding output data, the correct classification proportion of the converted network is verified so as to calculate the robustness score of the neural network to be tested, and the problem that the coverage rate and effectiveness of testing a neural network model are poor due to the fact that exhaustion traversal type testing cannot be used is solved.

The application discloses a kind of big model reinforcement learning network configuration generation methods based on verification feedback, input network phenomenon and state content are converted into semantic and action sequence by network configuration semantic analysis, based on semantic action sequence, through hybrid action space strategy generation and neural symbol collaborative reinforcement learning model, the configuration framework and parameter that meet the requirements are generated, the network configuration information generated is verified and fed back in digital twin system, formal verification and performance simulation are carried out in virtual environment, real network scene is simulated, the correctness and performance of configuration are comprehensively evaluated, and then feedback signal containing multidimensional information is generated, strategy model is modified and optimized according to digital twin verification, finally, through reward mechanism, intelligent agent is guided to adjust high-entropy configuration item, and optimization configuration generation big model.