613 results about "Formal verification" patented technology

An automated software production system is provided, in which system requirements are captured, converted into a formal specification, and validated for correctness and completeness. In addition, a translator is provided to automatically generate a complete, robust software application based on the validated formal specification, including user-interface code and error handling code.

An analytical software design system arranged to receive informal system design specifications and to convert them into verified design specifications for use in creating source code and carrying out implementation testing of the source code is described. The system comprises a verified black box specification generator arranged to process the received informal system design specifications to create formal specifications; to generate from the formal specifications mathematical models representing the system behaviour; to analyse the mathematical models to determine if they have the required behaviour; to adjust the formal specifications until the required behaviour is achieved; and to derive the required verified design specifications from the mathematical models.

An arrangement, system, and methods for creating and distributing authenticated personal information for users of network services and participants in social surveys, and in chat rooms and other forums. A trusted organization verifies that personal information presented by a user is correct, and authenticates the information in an encapsulated form as “certified profiles” within a smart card or other secure portable hardware device issued to the user Certified profiles are authenticated by digital signatures of the trusted organization and the profile users. Personal information in certified profiles can be in raw and/or in statistically-processed and abstracted form, and can be tailored by the user for specific needs to include whatever personal information is required, and to exclude all other personal information. By the use of unique aliases, it is possible for users to anonymously access restricted network sites and participate in surveys, while still satisfying recipients that supplied personal information is accurate, and for surveys that the user has not responded to the same survey more than once. Users enroll for certified profiles via trusted enrollment vendors who market the service to the public and also make hardware and software available to users for managing, maintaining, and distributing the certified profiles.

A system and method is disclosed for formal verification of software programs that advantageously translates the software, which can have bounded recursion, into a Boolean representation comprised of basic blocks and which applies SAT-based model checking to the Boolean representation.

The present invention provides a system and method to process items for sale or bid, to transmit electronic negotiations between prospective buyer and seller, and to verify the condition of the item before delivery to the buyer. The invention facilitates autonomous and remote negotiation between sellers and prospective buyers while protecting buyers from fraud and item misrepresentation. With the present invention, items can be sold individually and are not treated as standardized items that are interchangeable with similar commodity goods. The present invention also provides a waitlisting function. In addition, the functionality of traditional auction systems may be integrated with the novel features of the present invention. Furthermore, the present invention provides a system and method for conducting a reverse auction by allowing prospective buyers to list desired items.

The invention discloses improved random forest algorithm based system and method for software fault prediction. The system comprises a data processing layer, a prediction model building layer and a fault predication layer. The method includes calculating a software project attribute set used for acquiring a training model to acquire a training data set of a software prediction model, and performing equalization to the training data set; building a prediction model according to an improved random forest algorithm; screening the model according to performance limiting of accuracy rate and recall ratio; and predicting a software project according to attribute set information of the to-be-predicted software project and a trained prediction model and displaying prediction results and the prediction model. The improved random forest algorithm based system and method for software fault prediction have the advantages of high prediction accuracy rate, performance stability and high execution efficiency, can evaluate whether a final software product reaches specified quality or meets expectation of a user or not, and can guide developers to formulate distribution strategies of software testing and formal verification resources.

The invention provides a consumable verification system and a consumable verification method. The system comprises a printer, wherein the printer is provided with a consumable container; a consumable chip is arranged on the consumable container, and is provided with an electronic module and a communication interface; the electronic module stores serial number information of the consumable container; the system also comprises a verification server which is provided with a communication unit and a memory; and the memory stores configuration information and status information of the consumable container. The method comprises the following steps of: after the printer performs printing work once, transmitting the serial number information and the real-time status information to the server by using the consumable chip; and when the printer performs the next printing work, transmitting the real-time status information to the server again, and judging whether the consumable container is available by using the server, if so, returning information allowing printing, otherwise, returning error information. The invention can remotely configure and verify the consumable chip, the printer is prevented from using the consumable chip with tampered data for printing operation, and the printing quality is ensured.

A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification tool. Such automatic selection of one or more simulation states reduces the set of all simulation states to a small subset, thereby to address the state space explosion problem. Depending on the embodiment, the programmed computer uses one or more criteria provided by a library and/or by the user, in making its selection of states. Such criteria may be based on a property (assertion/checker) of the digital circuit and/or a signal generated during simulation. Furthermore, after such criteria (also called “primary criteria”) are applied, the selected states may be pruned by application of additional criteria (also called “secondary criteria”) prior to formal analysis.

A user may be willing to purchase items or participate in a pay-for service offered by a service provider. A service provider may wish to verify characteristics of the user prior to allowing transactions to take place, and may want to secure the transactions once the transactions are allowed. A credential issued to a user and a transaction application uploaded to a user device may be used to secure transactions between the user and a service provider interface, such as a webserver or a point-of-sale. The transaction application may capture real-time user data and comparing the real-time user data to prior user data stored on the credential, authenticate the service provider interface to the user and the user to the service provider interface; and establish an encrypted session between the service provider interface and the transaction application adapted to authenticate the transactions between the user and the service provider interface.

A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.

The present invention relates to a method, a computer program product and a system for performing functional formal verification. Error detection logic is verified by injecting errors in a hardware design description without any changes to the original design description. With the present invention both permanent and transient faults can be modelled, and the complete error space can be covered for all types of fault models that can be used at the RTL. The number of detected design errors is used to determine the overall coverage in relation to the number of injected errors. The error injection is prepared by adding additional circuits to an RTL netlist representation of the hardware logic design. Signal values for selected signals related to the error detection logic are compared for a modified netlist representation and for the original netlist using a formal verification tool.

The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.

A twin neural network training method for face verification comprises: a training sample set is prepared; the images in the training sample set are normalized in size and then input to the artificialneural network for training. Artificial neural network consists of two identical sub-neural networks. The training samples are divided into datasets data_p and data_p which are equal in number. The datasets data_p and data_p are sent to two sub-neural networks to extract the eigenvectors of the samples. By comparing the loss function to realize the iterative optimization of the neural network, until the iterative number reaches the set value, then jump out of the iteration, at this time the trained artificial neural network is the twin neural network for face verification; The contrast loss function represents similarity between two sets of eigenvectors.

Embodiments of an invention for verifying firmware using system memory error check logic are disclosed. In one embodiment, an apparatus includes an execution core, firmware, error check logic, non-volatile memory, comparison logic, and security logic. The error check logic is to generate, for each line of firmware, an error check value. The comparison logic is to compare stored error check values from the non-volatile memory with generated error check values from the error check logic. The security logic is to prevent the execution core from executing the firmware if the comparison logic detects a mismatch between the stored error code values and the generated error code values.

The invention discloses a system and method oriented to supermatic formal verification of a smart contract of a blockchain. By using a code converter tool, the smart contract source code of the blockchain can be automatically converted into a language interlayer code for formal verification and identification so as to be used for formal verification input; by adopting a formal method, supermatic formal safety verification can be carried out on a converted source code so as to judge whether the security attribute requirement of the smart contract is safe or not. By relatively high-degree automation, formal safety verification can be carried out on the smart contract of the blockchain, wherein an automatic code converter can be used for automatically generating a formal to-be-verified program, the automatic checking calculation strategy improves verification efficiency, and the measures can be used for greatly improving the formal verification efficiency of the smart contract and reducing the artificial degree of participation.

The invention relates to an artificial intelligence convolutional neural network face recognition system. The system comprises a shooting terminal (100), a network (200), a server (300), a convolutional neural network module (400), an artificial intelligence early warning operation system (500), a cloud computing unit (600), a comparison analysis with a cloud database face blacklist unit (700), atarget person identity determination unit (800) and a local database module (900). The method comprises the following steps: acquiring an image or video stream containing a face by using a shooting terminal through an artificial intelligence convolutional neural network face recognition system, automatically detecting and tracking the face in the image, and further performing a series of technicalprocessing related to the face on the detected face, including face detection, face key frame extraction and face verification; all-weather 24-hour uninterrupted monitoring on the periphery of the shooting terminal is realized, a user can realize information sharing, the utilization rate of information resources is improved, and the safety guarantee is increased for maintaining the stability of social security.

A face feature is extracted by a face feature extracting unit, a confidence index is extracted by a confidence index extracting unit, and then, they are outputted as a face meta-data. At a time of matching, by using the confidence index of the face meta-data, a distribution estimating unit estimates the data of a parameter and the like with regard to a posterior distribution when the confidence index is obtained. A distance calculating unit calculates a similarity between feature values. Consequently, the precision of face verification can be improved, thereby carrying out a practical face matching.

A method, product and system for implementing liveness detector for face verification. A method comprising detecting a symmetry line of the face; and verifying that the subject moved the mouth by computing a score based on values of a pair of images in the symmetry lines, wherein the score is indicative to a difference in the shape of the mouth between the pair of images. Another method comprises: verifying identity of a subject based on facial recognition and voice recognition, said verifying comprise determining there is mouth movement in an image sequence, wherein said determining comprises: in each image of the sequence, detecting a symmetry line of the face; and verifying that the subject moved the mouth, wherein said verifying comprises: computing a score based on comparison of symmetry lines of the face in different images of the set of images; and comparing the score with a threshold.