206 results about "Formal verification" patented technology

The invention relates to the field of chip verification, and provides a chip verification method, device and equipment, a medium and a chip. The method comprises the following steps: establishing a dynamic simulation verification environment of a to-be-verified design, and generating a plurality of test scenes and corresponding test excitation according to a design specification definition; sending the test excitation to a driver through a sequencer, converting the test excitation into a signal conforming to a to-be-verified design interface protocol by the driver, and transmitting the signal to the to-be-verified design; the monitor collects an input signal and an output signal of a to-be-verified design in real time, converts the input signal and the output signal into transactions, and transmits the transactions to the scoreboard; comparing the reference model with an output signal of the to-be-verified design to generate a dynamic simulation verification result; according to the dynamic simulation result, the state space is reduced, state space traversal is carried out on a design part which is not covered by dynamic simulation in the design to be verified, and a formal verification analysis result is generated; and evaluating the to-be-verified design according to the formal verification analysis result.

Systems and methods for mathematical modeling of the hardware and software stack of commodity computer platforms are provided, enabling provable guarantees on memory, device, and program execution. This approach addresses the technical problem of reliance on system agents that rely on implicit trust in the operating environment, which can be exploited by sophisticated attackers using complex threats such as memory access exploits and code / data integrity exploits. The solution provides a proactive, mathematically-backed security solution that eliminates entire classes of cyberattacks by design, ensuring realizable guarantees on commodity computer platforms running hardware and software stack elements at the lowest operating level. This approach has significant advantages over current reactive cybersecurity methods, including reduced complexity and overhead, and increased confidence in the integrity of the system. The solution's main uses include providing mathematically-backed security and availability guarantees for critical infrastructure, financial institutions, and other organizations vulnerable to cyberattacks.

The invention discloses a causal control VLA end-to-end system fusing perception and a world model, and belongs to the technical field of automatic driving. The system comprises a perception and world modeling subsystem; a reasoning and generating subsystem; a verification and collaborative learning subsystem; moreover, the perception and world modeling subsystem is composed of an environment perception module and a world model training module, the reasoning and generation subsystem is composed of a causal modeling module and a diffusion trajectory generation module, and the verification and collaborative learning subsystem is composed of a form verification module and a federal collaborative distillation module. According to the VLA end-to-end system, traditional correlation modeling of a world model is enhanced through causal modeling, so that the world model becomes more accurate; meanwhile, on the basis of traditional verification and updating of the world model, the verification and updating process of the world model generation trajectory is further enhanced through the verification and collaborative learning subsystem, so that the generated trajectory is safer and more reliable.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

A neural-symbolic hybrid system for generating binary document formats directly from natural language input comprises a binary-aware hierarchical tokenizer operating across four levels (binary bytes, structural elements, semantic content, and concepts), a constraint satisfaction engine with 64 parallel processing cores for enforcing structural integrity and mathematical consistency, format-specific processors for Excel, PowerPoint, PDF, and CAD documents, and a formal verification system generating mathematical proofs of correctness. The system includes custom AI Document Generation Processor (AIDGP) silicon spanning 600 mm2 with specialized cores providing 500 TOPS processing power. Performance characteristics include 99.7% structural accuracy, 100% format compliance, 15.3 second average generation time for complex documents, and distributed capacity of 1,000,000 documents per hour. The system eliminates intermediate conversion steps while maintaining semantic preservation through hardware-accelerated constraint satisfaction and formal verification engines ensuring structural integrity, format compliance, and security through AES-256 encryption and automated regulatory compliance across 25+ international standards.

The invention belongs to the technical field of Internet of Things security, and particularly relates to a multi-level Internet of Things equipment security management and access control method, which comprises the following steps of: performing bidirectional verification on a digital certificate and a hardware fingerprint through an edge node when equipment is accessed; calculating credibility in real time and dynamically dividing security levels by using a hybrid evaluation algorithm based on equipment operation context data; a fine-grained access strategy is generated in combination with equipment attributes and environmental risks, and cross-level collaboration is realized through a lightweight protocol; abnormal behaviors are detected in real time in the access process, and high-risk operation is blocked within milliseconds; and strategy conflict resolution and adaptive optimization are realized through formalized verification and deep reinforcement learning. According to the technical scheme, the identity authentication reliability, the authority dynamic adaptability, the strategy consistency and the threat response speed of the Internet of Things equipment are remarkably improved, and a systematic security guarantee is provided for large-scale Internet of Things applications with high security requirements.

The invention provides a method and a system for automatically checking and correcting a PCB (Printed Circuit Board) design rule, belonging to the technical field of PCB design. The method comprises the following steps of: analyzing data such as texts, images and tables in a PCB design document through a multi-modal large model, extracting a structured signal information table, automatically generating a dynamically adaptive checking rule, and automatically checking and correcting the PCB design rule. Comprising bit width check, connectivity verification and functional analysis. And the generated rule is optimized by combining a retrieval enhancement generation (RAG) technology with a verification rule base, so that the coverage is comprehensive and the accuracy is high. The system further evaluates the rule through a form verification tool, automatically corrects potential defects, and improves the quality and adaptability of the rule. According to the method, the efficiency and accuracy of PCB design inspection are remarkably improved, the manual intervention requirement is reduced, the method can be widely applied to complex electronic design scenes, and the rapid changing technology and market requirements are met.

The invention relates to the technical field of block chains and security technologies, and particularly provides a security protection detection method and system for a smart contract based on a block chain. The security indexes at least comprise a password economics security index, a dynamic behavior characteristic index, a formalized verification index and a consensus layer security index; and performing quantitative evaluation on the collected multi-dimensional security index to obtain a comprehensive security score of the target block chain, scoring the cryptoeconomics security index through a preset cryptoeconomics security index scoring model to obtain a cryptoeconomics security score, and sending the cryptoeconomics security score to the target block chain. The current comprehensive security score of the target block chain is compared with the adaptive dynamic risk threshold, and if the current comprehensive security score is higher than the adaptive dynamic risk threshold, an early warning signal is sent out, and the effect of comprehensively evaluating the block chain smart contract is achieved.

The invention provides a fuzzy mutual simulation formalized verification and modeling method based on a theorem prover, and particularly relates to a fuzzy mutual simulation equivalent model based on an uncertain fuzzy migration system by utilizing a functional language and the theorem prover, so that whether a fuzzy mutual simulation relationship exists between fuzzy systems or not is quickly acquired. Furthermore, correctness can be strictly guaranteed, and behavior equivalence of different fuzzy migration systems is effectively guaranteed.

The invention relates to the technical field of industrial control, and provides an industrial control logic intelligent generation system and method. The multi-modal input module is used for acquiring multi-modal data for a to-be-controlled process; the domain knowledge graph module is used for storing a pre-constructed knowledge graph; the preprocessing module is used for preprocessing the multi-modal data based on a pre-constructed knowledge graph; the controlled logic generation module is used for generating a logic control intermediate representation for a to-be-controlled process through a large language model according to the preprocessed multi-modal data; the formalized verification and interaction module is used for carrying out formalized verification on the logic control intermediate representation; and the target file generation and output module is used for compiling the logic control intermediate representation which is qualified through formalization verification into a control logic file aiming at the target platform. Under the constraint of the domain knowledge graph, the large language model can generate flexible and high-adaptability industrial control logic according to background knowledge to accurately adapt to different process requirements.

The invention relates to the technical field of software security, in particular to a high-credibility construction of a synchronous modeling language code generator and a formalized verification method and device thereof, electronic equipment and a medium, and the method comprises the following steps: obtaining a synchronous modeling language source program generated by the code generator; translating the synchronous modeling language source program to the abstract syntax tree; converting the abstract syntax tree into an intermediate representation, and converting the current intermediate representation into a next intermediate representation; and performing formalized verification on each transformation process until the translation process verification of all the language features of the synchronous modeling language source program is completed, and the formalized verification comprises the steps that each intermediate representation formalized definition has operation semantics meeting semantic certainty, and semantic retentivity is proved for the current intermediate representation transformation process. Therefore, the problems that related technologies only support partial language characteristics, compiling architecture design is simple, the formalized verification range is limited, and the requirements for complete modeling ability and high credibility are difficult to meet are solved.

The invention provides an engine software FADEC demand-oriented modeling analysis and test case automatic generation method, and belongs to the field of aero-engine control. According to the method, DeepSeek is used for assisting preprocessing at the system demand level, and modeling work based on a formalized table is completed; through multi-level demand model analysis, vulnerabilities existing in the demand are automatically detected; and finally, automatically generating a test case set meeting DO-178C airworthiness requirements by establishing a grammar logic architecture. The method focuses on formalized verification work of an engine software FADEC demand level, by using an executable model, defects appearing in the demand or design process can be effectively found, errors can be eliminated in time, test cases are automatically generated, and therefore rework and iteration cost in the later period of development is greatly reduced.

The invention discloses an Armv8-a assembly code-oriented formal verification method, which comprises the following steps of: analyzing an Armv8-a processor architecture and an instruction set system, extracting module components to be modeled, including an abnormal level, an execution state, a data value, a register block, a memory, an instruction set and an assembly code, and modeling each module component; determining a non-formalized requirement of the corresponding assembly instruction according to the function and the security specification of each assembly instruction in the assembly code, and then generating a formalized logic expression of each assembly instruction in combination with the defined model, so as to obtain a formalized specification; and finally, carrying out formalized verification by adopting a theorem prover. According to the method, modeling is carried out on each module component of a physical machine, then a formalized logic expression of each assembly instruction in an assembly code is generated based on a constructed model, and formalized verification of the Armv8-a assembly code is completed by using a theorem prover.

Generated instruction sequences captured from software interactions may be executed as part of formal verification of a design under test. Software-instructed commands to be performed to configure a design under test formatted according to an interface implemented by the design under test can be obtained. A sequence to perform the software-instructed commands may be generated to configure the design under test in a hardware design and verification language. The sequence may then be executed to perform the software-instructed commands to configure the design under test and then perform formal verification on the configured design under test.

The invention discloses a verification feedback-based large model reinforcement learning network configuration generation method, which comprises the following steps of: converting input network phenomena and state contents into a semantic and action sequence through network configuration semantic analysis; the method comprises the following steps: generating a configuration framework and parameters meeting requirements through a hybrid action space strategy generation and neural symbol collaborative reinforcement learning model, verifying and feeding back the generated network configuration information in a digital twin system, simulating a real network scene through formalized verification and performance simulation in a virtual environment, and establishing a network configuration model. According to the method, the correctness and the performance of configuration are comprehensively evaluated, then a feedback signal containing multi-dimensional information is generated, a strategy model is corrected and optimized according to digital twinborn verification, and finally, an intelligent agent is guided to adjust a high-entropy configuration item through a reward mechanism, and configuration is optimized to generate a large model.

The invention discloses an awareness perception quantum gravitational nerve acceleration unified computing platform and method based on formalized verification, and belongs to the field of high-performance computing, medical AI and quantum information processing. A quantum gravitational coupling neural processing unit (QGCNPU); a consciousness information integral calculation core (phi ICC); formalizing a receipt chain verifier (FRCV); and the mirror reflection symmetry correction module (MRSCM) is used for eliminating the continuous projection mistake and the discrete Boolean mistake through topological equivalence verification of a local observer and a global GodCam visual angle. The system adopts an FPGA + ASIC + quantum processor three-layer heterogeneous architecture, and supports real-time pathological modeling (precision gt; gt) of neurodegenerative diseases such as Alzheimer's disease, Parkinson's disease and ALS; 99.7%), drug target discovery (acceleration by 50 times) and consciousness state monitoring (time resolution lt; and meanwhile, the mathematical proving performance and the clinical auditing performance of the calculation process are ensured, and the requirements of the global 152 billion dollar neural science and technology market and the 89 billion dollar quantum calculation industry are met.

Embodiments of the present disclosure include a formal verification method comprising a plurality of custom generative AI-based tools configured in a bottoms up methodology to generate formal verification code using an LLM. In another embodiment, the present disclosure includes a generative AI-based tool architecture comprising an index of code examples. A query from a user is used to retrieve code examples, and the query and code examples are sent to an LLM to generate code corresponding to the query.

The invention provides a vehicle part interaction logic verification file generation method and an interaction logic verification method, and relates to the technical field of formal verification. The method comprises the following steps: acquiring multi-modal data of vehicle parts; analyzing the multi-modal data of the vehicle parts to obtain vehicle model information; according to the vehicle model information, respectively generating a vehicle part state transition path set and a linear sequential logic rule set; and generating an executable interaction logic verification file based on the vehicle component state transition path set and the linear sequential logic rule set. The vehicle model information is obtained based on the multi-modal data, the vehicle part state transition path set and the linear sequential logic rule set are automatically generated according to the vehicle model information, and the verification accuracy of interaction logic between vehicle parts is improved.

The invention provides a slice test and form verification fused runtime anomaly detection method, which comprises the following steps of: extracting a minimum code snippet related to a potential abnormal program point from a to-be-detected program by adopting a program slice; generating a test case on the basis of the minimized code snippets related to the potential abnormal points; executing the minimum code snippets containing the test cases to obtain a detection result; according to the method, through an integrated form verification and program slicing technology, known anomalies can be detected, more potential anomalies, especially anomalies caused by complex input scenes and dynamic behaviors, can be covered through automatic path analysis, the abnormal path can be recognized in advance, and the method has the advantages that the method is simple and convenient to operate and high in practicability. And postmortem analysis after dependence on actual abnormity is reduced.

The invention discloses a smart contract audit verification method and system based on a block chain, and a medium. The smart contract audit verification method comprises the steps of obtaining a to-be-audited smart contract; performing static analysis on the code of the smart contract, recording security vulnerability information, and executing a first security measure according to the security vulnerability information; dynamically analyzing the running process of the smart contract, recording first abnormal information, and executing a second security measure according to the first abnormal information; generating a test case, testing the smart contract according to the test case, recording second abnormal information, and executing a third security measure according to the second abnormal information; and performing formalized verification on the attributes of the smart contract, recording performance data, and executing performance optimization measures according to the performance data. The method can reduce the attack and abuse of the smart contract, reduces the occurrence probability of contract logic errors and potential safety hazards, and can be widely applied to the technical field of block chains.

The application discloses a kind of causal control VLA end-to-end systems of fusion perception and world model, belong to the technical field of automatic driving;The system includes: perception and world modeling subsystem;Reasoning and generation subsystem;Verification and collaborative learning subsystem;And, perception and world modeling subsystem is constituted by environment perception module and world model training module, reasoning and generation subsystem is constituted by causal modeling module and diffusion trajectory generation module, verification and collaborative learning subsystem is constituted by formal verification module and federal collaborative distillation module;The VLA end-to-end system of the application, through causal modeling, enhances the traditional correlation modeling of world model, so that the world model becomes more accurate;At the same time, on the basis of traditional verification and updating of world model, the verification and updating process of trajectory generated by world model is further strengthened through verification and collaborative learning subsystem, so that the generated trajectory is more safe and reliable.

The invention discloses an intelligent core security level software compiler formal verification method based on translation confirmation. The method comprises the following steps: constructing a semantic model of an intelligent core security level software compiler; carrying out semantic coding processing in SMT (Surface Mount Technology); and translation confirmation of the intelligent core security level software compiler. According to the method, self-defined operation and types can be defined, and new language characteristics and optimization steps are easily integrated; a new compiler component is quickly built, and the development time and difficulty are greatly reduced by multiplexing existing components and frames. According to the technical scheme, the created expected semantics can be formalized, so that the compiler conforms to the semantics, and a foundation is laid for verification of cross-platform core security.

The invention provides a formal verification method and device for state transition implementation codes and a program product, and the method comprises the steps: compiling a first state transition function implemented by a C language Switch Case statement to obtain a bit code file; obtaining a Cryptol file, wherein the Cryptol file comprises a second state transfer function which is realized by using a Cryptol programming language; acquiring a first input parameter set and a first output value set corresponding to the first state transfer function, and acquiring a second input parameter set and a second output value set corresponding to the second state transfer function; simulating state transition function symbolic execution based on the first output value set, the second output value set, the first input parameter set and the second input parameter set, converting the state transition function symbolic execution into a satisfiability model theory problem, and solving the satisfiability model theory problem through an external solver to obtain a verification result of a state transition implementation code; the problem that whether state transition is implemented correctly or not cannot be guaranteed only through a manual checking mode can be solved, and the state transition code implementation correctness is guaranteed.

The invention discloses an AI knowledge base continuous optimization system and method based on man-machine cooperation and closed-loop feedback. The continuous optimization system for the AI knowledge base comprises a multi-mode co-emotion knowledge input module, a knowledge active discovery and construction module, a layered depth inference engine, a response generation module oriented to a specific scene, an output formal verification and interpretability analysis module, a dynamic resource scheduling and reflection module and a man-machine collaborative feedback interface. A feedback data deep analysis module, a knowledge base dynamic update and conflict resolution module and a model increment optimization and security alignment module. Through the mode, the systematic system which has the capabilities of active learning, deep reasoning, self-verification and efficient man-machine cooperation and can realize continuous self-optimization of the knowledge base is provided.

The invention discloses a verification device and a verification method for a background mechanism cyclic redundancy check algorithm, and relates to the technical field of integrated circuit verification, a formalized verification automatic exhaustion input state space is introduced, calculation results of a hardware design RTL and a software golden reference model are compared, and a difference report is formed; performing simulation verification on the basis of formalized verification, constructing a competition scene of the master end and the background CRC calculation module which are located at the same communication level as the background CRC calculation module relative to slave end equipment, executing simulation verification, crosswise covering different master end function combinations, and finding whether a verification error exists or not through monitoring interruption; the comprehensive verification of the background mechanism, the calculation and the error notification function of the verification object is realized in the process from initiating the memory access to loading the memory data to outputting the data verification result. And finally, packaging the formalized verification and the simulation verification into a regression task which can be executed through parameter transmission through regression management, and converting the verification into a reliable operation automation scheme.

Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

The invention provides a chip design verification method and system, electronic equipment and a storage medium. The chip design verification method comprises the following steps: acquiring a design file of a chip and a design stage corresponding to the design file; selecting a target collaborative verification mode matched with the design stage from a plurality of collaborative verification modes; wherein the cooperative verification mode comprises a mode for verifying the design file through cooperation between logic simulation verification and form verification; the collaborative verification modes corresponding to different design stages are different, and the collaborative modes between logic simulation verification and form verification in the different collaborative verification modes are different; and verifying the design file based on the target collaborative verification mode. According to the method, logic simulation verification and formal verification work cooperatively, and respective advantages are combined for complementation, so that the efficiency and effectiveness of chip design and verification are improved.

The invention relates to the technical field of software engineering and artificial intelligence, and discloses a high-credibility programming agent system and method based on a large model and a formalization method. A high-credibility programming agent system based on a large model and a formalization method comprises an agent core module used for providing common perception, memory, decision and execution capabilities for various professional agents; the multi-agent cooperation module is constructed on the agent core module and comprises a coding agent, a form analysis agent and a form verification agent; the coding agent is responsible for generating, complementing, reconstructing and optimizing program codes based on natural language requirements or contexts. The system realizes full-process automation from demand understanding to code generation, analysis, verification and restoration through autonomous planning and multi-task execution capability of the intelligent agent, reduces manual intervention links, and remarkably shortens the development period.

The invention discloses an arbitration-based automatic driving decision-making method, system and device and a storage medium. The method comprises the steps of heterogeneous parallel sensing and planning calculation, and synchronous starting of two independent calculation assembly lines; performing unified representation and space-time alignment, and performing standardization processing on output of the two calculation assembly lines; certified security arbitration and decision making are carried out, and security verification and utility evaluation are carried out on each candidate track output by the main brain; performing control execution and global health monitoring, and sending the selected track to a vehicle controller for execution; and performing off-line closed-loop self-evolution, retraining and optimizing the model, and updating and deploying the model to a vehicle end system through OTA. According to the method, a heterogeneous double-brain system integrating an end-to-end AI model and a traditional rule model is constructed, and a certifiable safety arbitration mechanism with strict formalized verification capability is introduced, so that the absolute safety, dynamic reliability and continuous self-evolution of an automatic driving decision are ensured while the AI performance advantages are fully played.