132 results about "Basic block" patented technology

The invention provides a BLAS3 structured operator accelerated computing system based on a Hopper architecture GPU, and relates to the technical field of computers. The system comprises: a calculation unit discrimination module for determining a calculation unit used by a current operator during operation, and estimating the maximum row dimension upper bound of the current operator in a tensor core execution path; an instruction sensing block parameter determination module dynamically determines the optimal block size and number of the input matrix in real time; the block matrix loading and aligning module divides an input matrix and a matrix to be updated into sub-matrixes by taking the block size as a basic block and completes loading of the corresponding sub-matrixes; the operator kernel function execution module completes shared memory structured parallel loading and storage of a double-precision floating-point number array of a sub-matrix corresponding to the input matrix, and calls a tensor core to carry out multiply-add accumulation calculation; and the assembly line and concurrent scheduling module adds the block calculation tasks into corresponding task sets and performs multi-stream concurrent scheduling on the task sets.

The invention belongs to the field of micro-architecture design of an integrated circuit processor. The invention provides an H2P branch prediction chip circuit architecture based on BrPerceptron, a variable operation track of a program is constructed based on a context-sensitive variable tracking mechanism, a program execution path topology is constructed based on a basic block division algorithm according to the variable operation track, multi-dimensional correlation detection is performed according to the program execution path topology to judge whether an H2P branch exists or not, and if yes, the H2P branch is predicted. And when the H2P branch instruction is judged to be the H2P branch instruction, enabling the BrPerceptron predictor to output, performing multi-stage feature fusion and outputting a prediction result, and realizing high-precision prediction for the H2P branch instruction.

The invention discloses an intelligent contract vulnerability detection method based on a multi-level data dependence heterogeneous graph, and belongs to the technical field of intelligent contract security. Intelligent contract byte codes are used as input, contract byte codes are converted into operation codes, and a control-data heterogeneous graph with basic blocks as nodes is constructed; designing an in-block data dependency sub-graph, and forming multi-level data dependency with the inter-block data stream; based on the generated control-data heterogeneous graph, a feature weighted relation graph convolutional network is provided, and control flow and data flow feature weights are dynamically adjusted and optimized by using node static attributes such as dominating tree depth and the like, so that multi-modal semantic efficient aggregation is realized. According to the method, for the contract without a public source code on the block chain, vulnerability detection only for the bytecode of the intelligent contract is realized, and high detection efficiency can be achieved under the condition that the detection accuracy is guaranteed.

The invention discloses a code embedding method based on a semantic embedding vector generation model, which belongs to the technical field of computers, and comprises the following steps of: obtaining a binary code block, and performing disassembling processing and code structure analysis based on different granularities to obtain a basic block corresponding to the binary code block and a control flow diagram structure feature; performing assembly instruction linear conversion and cross-instruction-set semantic embedding conversion on the basis of the basic blocks corresponding to the binary code blocks and the structural features of the control flow graph to generate a unified binary code semantic embedding vector space corresponding to a cross-instruction-set architecture; obtaining a known vulnerability sample, and performing semantic vulnerability characterization analysis and candidate vulnerability retrieval positioning to generate a candidate vulnerability code block set; and carrying out dynamic analysis verification on the candidate vulnerability code block set and identifying a corresponding vulnerability repair state so as to output a corresponding binary vulnerability code block detection report. According to the method, high-precision semantic embedding of binary codes can be realized.

The present invention provides an operating system kernel fuzz testing method, device and equipment, which relate to the field of kernel fuzz testing technology. By obtaining the initial input and splitting the initial input to generate an input set; performing fuzz testing on the input set and obtaining the fuzz testing results; storing the fuzz testing results in a key component inference file to generate a key component inference table; generating a seed selection strategy in the seed library in combination with the key component inference table to guide seed mutation selection. By identifying and utilizing the key components in the system call sequence, the coverage of the fuzz test is improved. A correspondence between the key components in the system call sequence and the corresponding path basic blocks is established to better explore potential security vulnerabilities. According to the selection of mutation points, different mutation strategies are executed to effectively improve the existing fuzz testing method and improve the efficiency and quality of vulnerability mining.

The invention discloses a remote sensing image target detection method based on improved RT-DETR and computer equipment, and relates to the field of deep learning and target detection, and the method comprises the steps: inputting a to-be-detected remote sensing image into an optimal remote sensing image target detection model, and obtaining a recognition result of the remote sensing image; the remote sensing image target detection model comprises an improved backbone network, an improved neck network and a head network; wherein the improved backbone network is a network which is obtained by replacing a Basic Block module with a Faster Block module in a backbone network of the RT-DETR network model; the improved neck network is a network obtained by integrating an MFEP-OK module and a CGAFusion module on the basis of a neck network of an RT-DETR network model. According to the method, the detection speed is ensured, and the detection accuracy of small targets and long-tail targets in a remote sensing image target detection model is improved.

The embodiment of the invention relates to an instruction execution method and device, a processor and a related product, an MIMD framework is adopted in a GPU, a first SIMT stack and a second SIMT stack are configured for managing execution information of different branch basic blocks in the same thread bundle, and on the basis, the execution information of the different branch basic blocks in the same thread bundle can be managed through the first SIMT stack and the second SIMT stack. According to the method, the state of at least one of a first SIMT stack and a second SIMT stack is updated according to a basic block to be executed, and under the condition that the updated first SIMT stack and the updated second SIMT stack are both non-empty, instructions in all branch basic blocks are taken out respectively according to execution information of the first SIMT stack and execution information of the second SIMT stack and transmitted to an MIMD for concurrent execution. According to the method, when the execution channels of the MIMD concurrently execute the branch instructions, the resource utilization rate of the ALU can be improved, and therefore the running performance of a GPU program is improved.

The invention relates to the field of code vulnerability detection, in particular to a binary vulnerability retrieval and positioning method and system based on high-dimensional vulnerability characterization, and the method comprises the steps: firstly inputting a binary file, analyzing the structural information of the binary file, and analyzing a machine instruction; extracting binary file function information, generating a cross-platform basic block IR instruction sequence, constructing a control flow graph, and constructing a data dependency graph; splicing the program dependency graph feature vector and the basic block IR instruction sequence feature vector, and performing multi-modal feature fusion to generate a comprehensive high-dimensional vulnerability representation vector; and finally, inputting the high-dimensional vulnerability representation vector into an index for searching to obtain a plurality of nearest neighbor indexes and distances, converting the distances into similarity, filtering according to a similarity threshold to obtain a most similar vulnerability vector, and obtaining vulnerability information and vulnerability positions corresponding to the vulnerability vector. The problems that traditional binary vulnerability detection cross-platform and compiler optimization detection fails and the result reliability is low are solved.

The invention relates to the technical field of software security, and discloses an IDA microcode-based digital multimeter customized code obfuscator construction method and system, and the method comprises the steps: carrying out the obfuscation replacement of a measurement algorithm and a data processing method in a digital multimeter code based on an instruction replacement technology; confusing a control flow of the digital multimeter based on a false control flow technology, namely obtaining a calling relation of basic blocks to reconstruct an original program, and avoiding generation of an endless loop in a symbolic execution process through a method of assigning a value to an opaque predicate in advance; randomly modifying variable names, identifiers and function names of the sensitive data information of the digital multimeter based on a variable name confusion algorithm; and carrying out decompilation and code conversion on the obfuscation algorithm based on the IDA microcode, and constructing the digital multimeter customized code obfuscator based on the IDA microcode. The method can be integrated into the development environment of the digital multimeter, the safety protection level of the digital multimeter is improved, and the measurement data is prevented from being illegally stolen.

The invention discloses a cross-platform binary code block hierarchical semantic similarity detection method and a related device, and belongs to the field of code vulnerability detection.The cross-platform binary code block hierarchical semantic similarity detection method comprises the following steps that structural information of a binary file is analyzed, a machine instruction is analyzed through a hybrid disassembling engine, a basic block is extracted from the structural information of the binary file, and the basic block is extracted from the binary file; constructing a control flow graph, a data dependency graph and a function call graph; extracting instruction level semantics, basic block level semantics and function level semantics from the instruction sequence, the basic block, the control flow graph, the data dependency graph and the function call graph; according to the instruction-level semantics, the basic-block-level semantics and the function-level semantics, constructing instruction-level features, basic-block-level features and function-level features; and carrying out hierarchical similarity detection on the instruction-level features, the basic block-level features and the function-level features. The method and the related device can solve the problems of low detection efficiency and poor accuracy when a traditional vulnerability detection method is used for detecting vulnerabilities.

The invention discloses a data prefetching method and device, and relates to the technical field of computers. The data prefetching method comprises the steps that a control flow diagram and events, recorded by a PMU, of basic blocks in the control flow diagram are obtained, target paths of multiple paths in the control flow diagram are determined according to the occurrence frequency of the events of the basic blocks in the control flow diagram, and then target data corresponding to a first basic block are written into a buffer before the first basic block is executed. Wherein the sum of the occurrence frequency of all events of the basic block in the target path is greater than or equal to a first threshold value, and the target data is data with the access frequency or the access frequency greater than or equal to a second threshold value in the data needing to be accessed when the target path is executed. The sum of the occurrence times corresponding to the target path is greater than or equal to the first threshold value, so that the probability that the target path is frequently executed is relatively high, the target data determined according to the target path is written into the cache in advance, and the data access efficiency when the processor executes according to the control flow diagram can be improved.

The invention relates to the field of code vulnerability detection, in particular to a vulnerability detection method and system based on code block features. The method comprises the steps that firstly, a binary file is analyzed, and a machine instruction is analyzed through a hybrid disassembling engine; secondly, performing static linear scanning on the extracted binary file instruction, constructing a control flow graph, dividing basic blocks, extracting an operation code sequence in the basic blocks, and constructing a cross-basic-block data dependency graph and a system calling sequence called by the basic blocks; secondly, using an LSH algorithm to realize rapid filtering, performing similarity comparison on extracted basic block features and vulnerability feature library features, realizing coarse-grained matching, and screening out a matching candidate set; feature fusion is carried out on the candidate set basic block operation code sequence, the basic block data dependency graph and the system calling sequence called by the basic block, GNN fine-grained matching is carried out on the fused features, and vulnerability detection is carried out. The problems that traditional binary vulnerability detection is poor in adaptability and low in result reliability are solved.

The invention discloses a sparse attention operator acceleration method based on an NPU, and the method comprises the steps: combining a Linformer with an Ascend C programming language, and achieving an Ascend C operator for calculating the Linformer based on the NPU; according to the method, an accelerated calculation mode of combining Linformer with Flash-Attention2 is adopted, so that the whole operator can be subjected to calculation in a blocking manner; according to hardware characteristics of the mercuric chloride NPU, optimization of vector calculation is carried out, the number of instructions used by multiple vector calculations such as vector subtraction, line-by-line summation and line-by-line max calculation for calculating safety softmax is reduced, and time consumption is reduced; aiming at the problem that front and back data cannot be parallel due to more dependence, the calculation efficiency of a sparse approximate attention operator is improved by using an algorithm for constructing parallel calculation by emitting Cube in advance; basic block segmentation is carried out on matrix multiplication, and the carrying time of matrix multiplication is shortened.

A simulation method for simulating a target circuit design comprising a plurality of micro-architecture hyper-parameters. The method comprises decompiling a binary code to obtain a control flow graph comprising multiple basic blocks (101, 120); generating multiple basic block chains, BBCs, based on the plurality of basic blocks taking account of the micro-architecture hyper-parameters (102, 130); performing, for each BBC, cycle-accurate simulation (104, 150) based on the determined context (103, 140), to obtain cycle count information (150); storing the cycle count information into a database (105, 160); performing instruction-accurate simulation (106) using the binary code, to obtain instruction traces indicating executed BBC; retrieving, for each executed BBC, corresponding cycle count information from the database (107); and determining overall cycle count information of the binary code on the target circuit design by accumulating the retrieved cycle count information of the executed BBCs (108). In this way, a fast and accurate simulation can be achieved.

In various examples, static single assignment-based control flow graph traversal analysis for uninitialized variable detection system and methods are disclosed. A pre-compiler stage of a compiler system, may reconstruct source code into an SSA form IR and detect and identify uninitialized variables based on applying a variable analysis pass that traverses a CFG corresponding to the SSA form IR. A variable analysis pass may traverse through the CFG to build a defined variable map and a Phi variable map. The maps may be used to map undefined variables to basic blocks of the CFG where the undefined variables occur. The variable analysis pass may pass uninitialized variable data to a compiler error handling process. The compiler error handling process may produce an error report that traces the basic block with undefined variables to lines of the source code to assist in efficiently debugging the source code.

The invention provides an image processing method and device, electronic equipment, a storage medium and a program product, and belongs to the technical field of deep learning, and the method comprises the steps: determining a partitioning parameter based on a hardware parameter and a convolution operation parameter of a tensor kernel; performing blocking processing on a feature map corresponding to the to-be-processed image based on the blocking parameters to obtain a plurality of basic blocks; obtaining a plurality of three-dimensional tensors corresponding to the plurality of basic blocks; converting the plurality of three-dimensional tensors into a plurality of first matrix blocks adaptive to a tensor kernel based on the total element number of the three-dimensional tensors corresponding to the basic blocks; respectively inputting the plurality of first matrix blocks into a tensor kernel to obtain a plurality of second matrix blocks output by the tensor kernel; and reconstructing the plurality of second matrix blocks according to the output size of the feature map to obtain an output feature map. Through adaptive adjustment of the partitioning strategy, the waste of calculation power is reduced, and the parallel calculation capability of the tensor kernel is brought into full play, so that the calculation delay in the training and reasoning process of the convolutional neural network is reduced, and the overall operation efficiency is improved.

A simulation method for simulating a target circuit design comprising a plurality of micro-architecture hyper-parameters. The method comprises decompiling a binary code to obtain a control flow graph comprising multiple basic blocks (101, 120); generating multiple basic block chains, BBCs, based on the plurality of basic blocks taking account of the micro-architecture hyper-parameters (102, 130); performing, for each BBC, cycle-accurate simulation (104, 150) based on the determined context (103, 140), to obtain cycle count information (150); storing the cycle count information into a database (105, 160); performing instruction-accurate simulation (106) using the binary code, to obtain instruction traces indicating executed BBC; retrieving, for each executed BBC, corresponding cycle count information from the database (107); and determining overall cycle count information of the binary code on the target circuit design by accumulating the retrieved cycle count information of the executed BBCs (108). In this way, a fast and accurate simulation can be achieved.

The application discloses a patch existence detection method based on key basic blocks, which comprises the following steps: firstly, modeling the semantics of a vulnerability function, a patch function and a target function to be detected into a function static control flow graph, and performing necessary preprocessing to minimize the influence caused by compilation confusion; then, a basic block matching algorithm is proposed, and the basic block matching is performed between the vulnerability function, the patch function and the target function respectively, so as to generate a matching basic block pair set; then, the change degree of a feature basic block related to the patch is analyzed, and the top N feature basic blocks are selected as key basic blocks for effective patch existence test; finally, the key basic blocks of the patch function and the vulnerability function are searched in the target function respectively, and it is judged whether the target function is more similar to the patch function, that is, whether the vulnerability has been patched. Through the above method, it can be quickly and accurately judged whether the vulnerability in a large-scale function to be detected has been patched.

The invention discloses a lightweight program control flow obfuscation method, system and device and a medium, and the method comprises the steps: carrying out the static analysis of a program based on a program source code, recognizing all basic blocks, analyzing the execution sequence and jump relation of the basic blocks, and obtaining a control flow diagram of the program; a unique runtime state is distributed for the basic blocks by analyzing the dependency relationship among the basic blocks, and a conversion rule among the states is defined, so that a state transition model is obtained; the method comprises the following steps: dynamically generating an encryption key by using a state conversion relationship, and encrypting sensitive information in a control flow to obtain an encryption program code subjected to obfuscation protection; a current runtime state is read in a program execution process, a corresponding decryption key is generated, a plaintext address of sensitive information is restored, and executable implicit jump and variable access operation is obtained. Static analysis, especially control flow analysis, can be effectively resisted, so that source codes and algorithms of software are protected from being easily acquired or tampered.

This invention discloses a staged multi-policy instruction scheduling method and system for VLIW architecture. The method includes: basic step S1. Receiving the symbolic assembly structure (SAS); S2. Configuring three types of scheduling vision interfaces and registering corresponding scheduling policies, including a global vision interface, a loop vision interface, and a linear vision interface; S3. Executing loop vision scheduling, traversing all loop blocks, and concurrently calling the loop vision interface to generate candidate scheduling schemes; S4. Executing linear vision scheduling, after all loop blocks have been scheduled, traversing the remaining unscheduled basic blocks, and concurrently calling the linear vision interface to generate candidate schemes; S5. Performing competitive selection and register allocation on the candidate scheduling schemes generated in each stage; S6. Outputting the optimized SAS. This invention can efficiently adapt to various VLIW processor architectures, improving instruction-level parallelism and code execution efficiency.

The invention relates to the technical field of computers, and particularly provides a code optimization method and device, electronic equipment, a storage medium and a product. According to the method, the program flow graph of the to-be-optimized code is generated, section view information of the to-be-optimized code is obtained, and the section view information comprises the branch probability and the jump distance; therefore, based on the branch probability, determining a plurality of basic block chains in the program flow graph; any basic block chain comprises at least one basic block; and then, based on the branch probability and the jump distance, rearranging the plurality of basic block chains to obtain a target code. In conclusion, the technical scheme provided by the invention can effectively improve the global performance of the code, in addition, the code optimization overhead can be reduced, and the code optimization efficiency can be improved.

Embodiments of the present application disclose a method, device, equipment, medium and program product for generating an adversarial sample. The method comprises: obtaining a preset code file; determining a non-conditional jump instruction in the preset code file; modifying the non-conditional jump instruction into a reconstructed jump instruction according to a preset instruction modification rule; performing control flow flattening processing on a basic block of the preset code file; based on a result of the control flow flattening processing, inserting a preset application programming interface (API) sequence into the preset code file according to a preset rule to obtain a target code file containing a malicious code feature; inserting noise into the target code file to obtain an initial sample; and performing iteration on the initial sample according to a preset evolution algorithm to obtain an adversarial sample. The embodiments of the present application can generate a large number of malicious code adversarial samples that can evade antivirus software and sandboxes.

The present application relates to the binary function similarity detection method of strengthening instruction execution semantics, belongs to network security technical field, first through IDA obtains the assembly code basic block of binary function, secondly, the instruction features of basic block are extracted using Word2vec, specific instructions in basic block are marked according to execution semantics table simultaneously, and instruction execution semantic representation sequence is generated according to execution order, then the instruction features and instruction execution semantic representation are fused to generate basic block embedding, and binary function embedding is generated based on basic block embedding using graph embedding network, finally, binary function similarity detection is carried out using twin network, the present application proposes a basic block instruction execution semantic representation method aiming at the problem that existing basic block embedding generation method does not make full use of instruction execution semantics, strengthens instruction execution semantic features, and improves the accuracy of binary function similarity detection.

The embodiment of the invention provides a tensor instruction optimization method, tensor instruction optimization equipment and a storage medium, and relates to the technical field of artificial intelligence chips, the method comprises the following steps: sequentially traversing N tensor instructions in a target basic block, and if a target instruction on which the current traversed tensor instruction depends exists and L intermediate instructions exist between the tensor instruction and the target instruction, determining that the tensor instruction depends on the target instruction; if yes, obtaining the total extra time based on the respective extra execution time of the L intermediate instructions; if the total out-of-total time is greater than the unit execution time of the currently traversed tensor instruction, it is indicated that when the assembly line executes the currently traversed tensor instruction, a target instruction on which the currently traversed tensor instruction depends is inevitably executed, so that a dependency descriptor of the currently traversed tensor instruction is set as a first descriptor to represent a dependency-free relationship; therefore, the assembly line can directly execute the tensor instruction without waiting, so that the probability that the assembly line is blocked is reduced, idle running of hardware resources in the assembly line is reduced, and the utilization rate of the hardware resources is improved.

The invention discloses a computational efficient point cloud analysis method based on a grouping selective state space, and the method comprises the steps: firstly, a sequence extension module carries out the serialization of points along each axis, and enables a disordered point cloud to more stably adapt to the causal characteristics of Mamba without parameters; secondly, sorting prompt and position embedding are adopted to provide sorting and position information for the point sequence respectively, so that geometric semantics are better captured; thirdly, the chain type bidirectional Mama enables the forward process and the reverse process in the parallel bidirectional Mama to be connected in series, a global receptive field on a point sequence is provided, and meanwhile high-order geometric information is captured in the scanning process. And fourthly, the grouping selective state space model introduces parameter sharing among multiple dimensions into the selective state space model, so that overfitting caused by a calculation mode in the selective state space model is relieved. And 5, a sequence merging module fuses corresponding high-order interaction features obtained through causal reasoning on different sequences. And finally, packaging the flow into a basic block, and embedding the basic block into a standard codec architecture for hierarchical feature aggregation. According to the method, the accuracy of point cloud analysis based on the state space model is improved while the calculation efficiency is ensured.

The invention discloses a cross-ISA (Industrial Standard Architecture) extension program translation method based on binary rewriting, which comprises the following steps of: 1) naming an instruction set ISA of a program to be translated as an original ISA, and naming an instruction set ISA on target hardware for running original ISA extension as a target ISA; 2) performing comparative analysis on a binary file corresponding to the original ISA extension compilation and a binary file corresponding to the target ISA extension compilation to obtain an instruction needing to be translated relative to the target ISA extension in the original ISA extension, and segmenting the instruction into a plurality of program basic blocks needing to be translated; 3) allocating a jump instruction and an address space for translating and storing translated codes to each program basic block; (4) distributing the program basic blocks into the corresponding address spaces through a jump instruction to carry out static binary translation, and generating a static file; and (5) distributing a loading address for the static file by utilizing a loader according to the address distribution information in the static file, and loading the static file to a corresponding position.

Embodiments of the present application provide a tensor instruction optimization method and device and a storage medium, and relate to the technical field of artificial intelligence chips. The method comprises: sequentially traversing N tensor instructions in a target basic block; if there is a target instruction on which a currently traversed tensor instruction depends, and there are L intermediate instructions between the tensor instruction and the target instruction, obtaining total additional time based on the additional execution time of each of the L intermediate instructions; and if the total additional time is greater than the unit execution time of the currently traversed tensor instruction, it is indicated that the target instruction on which the currently traversed tensor instruction depends has been executed when the pipeline executes the currently traversed tensor instruction, so the dependency descriptor of the currently traversed tensor instruction is set to a first descriptor to represent no dependency relationship. In this way, the pipeline can directly execute the tensor instruction without waiting, thereby reducing the probability of pipeline blocking, reducing the idling of hardware resources in the pipeline, and improving the utilization rate of hardware resources.

The present application relates to a SOC verification and optimization method, apparatus, computer equipment, and medium based on instruction stream analysis, which uniformly samples subroutines of a program and extracts Basic Block sequence information in the subroutines; extracts instruction information of each Basic Block; aggregates instruction information and Basic Block sequence information to obtain an instruction sequence, and constructs an instruction semantic sequence model based on an autoregressive language model based on the instruction sequence; constructs a Basic Block program behavior representation model based on the instruction semantic sequence model and using a comparative learning method; reads several sliced ​​subroutines to be run, and obtains the semantic representation of the sliced ​​subroutines through the Basic Block program behavior representation model; constructs a subroutine similarity matrix based on the semantic representation of the sliced ​​subroutine, and performs program selection based on the subroutine similarity matrix.

This application relates to a fuzz testing visualization method, apparatus, computer device, computer-readable storage medium, and computer program product. The method includes: acquiring program information of a target test program; the target test program includes at least one function; the program information indicates the number of basic blocks contained in each function and the number of transition paths between basic blocks; generating an overall program graph corresponding to the target test program based on the program information; wherein the overall program graph includes graphical elements representing each function; each graphical element includes graphical sub-elements representing basic blocks in the corresponding function; acquiring a fuzz test log corresponding to the target test program, recording the coverage of basic blocks by the fuzz test seed during fuzz testing of the target test program; color-coding the graphical sub-elements in the overall program graph based on the fuzz test log to generate a program state graph. This method can improve fuzz testing efficiency.

Methods and apparatus for a runahead process are provided to prevent frontend stalls when executing a computer program. Methods and apparatus profile and analyze the computer program when it is compiled to extract meta-data defining hyperblocks for the computer program. The hyperblocks each encompass a respective series of basic blocks having transitions that meet a specified threshold. When the computer program is executed, the runahead process is performed for program branches. In this process, a future path of hyperblocks is predicted from each branch and the instructions corresponding to those hyperblocks are prefetched to a memory cache so that they can be readily fetched. Cycles or large call stacks are removed to enable deep runaheads, which may span about a thousand instructions.