76 results about "Basic block" patented technology

The invention provides a BLAS3 structured operator accelerated computing system based on a Hopper architecture GPU, and relates to the technical field of computers. The system comprises: a calculation unit discrimination module for determining a calculation unit used by a current operator during operation, and estimating the maximum row dimension upper bound of the current operator in a tensor core execution path; an instruction sensing block parameter determination module dynamically determines the optimal block size and number of the input matrix in real time; the block matrix loading and aligning module divides an input matrix and a matrix to be updated into sub-matrixes by taking the block size as a basic block and completes loading of the corresponding sub-matrixes; the operator kernel function execution module completes shared memory structured parallel loading and storage of a double-precision floating-point number array of a sub-matrix corresponding to the input matrix, and calls a tensor core to carry out multiply-add accumulation calculation; and the assembly line and concurrent scheduling module adds the block calculation tasks into corresponding task sets and performs multi-stream concurrent scheduling on the task sets.

The invention discloses a remote sensing image target detection method based on improved RT-DETR and computer equipment, and relates to the field of deep learning and target detection, and the method comprises the steps: inputting a to-be-detected remote sensing image into an optimal remote sensing image target detection model, and obtaining a recognition result of the remote sensing image; the remote sensing image target detection model comprises an improved backbone network, an improved neck network and a head network; wherein the improved backbone network is a network which is obtained by replacing a Basic Block module with a Faster Block module in a backbone network of the RT-DETR network model; the improved neck network is a network obtained by integrating an MFEP-OK module and a CGAFusion module on the basis of a neck network of an RT-DETR network model. According to the method, the detection speed is ensured, and the detection accuracy of small targets and long-tail targets in a remote sensing image target detection model is improved.

The embodiment of the invention relates to an instruction execution method and device, a processor and a related product, an MIMD framework is adopted in a GPU, a first SIMT stack and a second SIMT stack are configured for managing execution information of different branch basic blocks in the same thread bundle, and on the basis, the execution information of the different branch basic blocks in the same thread bundle can be managed through the first SIMT stack and the second SIMT stack. According to the method, the state of at least one of a first SIMT stack and a second SIMT stack is updated according to a basic block to be executed, and under the condition that the updated first SIMT stack and the updated second SIMT stack are both non-empty, instructions in all branch basic blocks are taken out respectively according to execution information of the first SIMT stack and execution information of the second SIMT stack and transmitted to an MIMD for concurrent execution. According to the method, when the execution channels of the MIMD concurrently execute the branch instructions, the resource utilization rate of the ALU can be improved, and therefore the running performance of a GPU program is improved.

In various examples, static single assignment-based control flow graph traversal analysis for uninitialized variable detection system and methods are disclosed. A pre-compiler stage of a compiler system, may reconstruct source code into an SSA form IR and detect and identify uninitialized variables based on applying a variable analysis pass that traverses a CFG corresponding to the SSA form IR. A variable analysis pass may traverse through the CFG to build a defined variable map and a Phi variable map. The maps may be used to map undefined variables to basic blocks of the CFG where the undefined variables occur. The variable analysis pass may pass uninitialized variable data to a compiler error handling process. The compiler error handling process may produce an error report that traces the basic block with undefined variables to lines of the source code to assist in efficiently debugging the source code.

The application discloses a patch existence detection method based on key basic blocks, which comprises the following steps: firstly, modeling the semantics of a vulnerability function, a patch function and a target function to be detected into a function static control flow graph, and performing necessary preprocessing to minimize the influence caused by compilation confusion; then, a basic block matching algorithm is proposed, and the basic block matching is performed between the vulnerability function, the patch function and the target function respectively, so as to generate a matching basic block pair set; then, the change degree of a feature basic block related to the patch is analyzed, and the top N feature basic blocks are selected as key basic blocks for effective patch existence test; finally, the key basic blocks of the patch function and the vulnerability function are searched in the target function respectively, and it is judged whether the target function is more similar to the patch function, that is, whether the vulnerability has been patched. Through the above method, it can be quickly and accurately judged whether the vulnerability in a large-scale function to be detected has been patched.

This invention discloses a staged multi-policy instruction scheduling method and system for VLIW architecture. The method includes: basic step S1. Receiving the symbolic assembly structure (SAS); S2. Configuring three types of scheduling vision interfaces and registering corresponding scheduling policies, including a global vision interface, a loop vision interface, and a linear vision interface; S3. Executing loop vision scheduling, traversing all loop blocks, and concurrently calling the loop vision interface to generate candidate scheduling schemes; S4. Executing linear vision scheduling, after all loop blocks have been scheduled, traversing the remaining unscheduled basic blocks, and concurrently calling the linear vision interface to generate candidate schemes; S5. Performing competitive selection and register allocation on the candidate scheduling schemes generated in each stage; S6. Outputting the optimized SAS. This invention can efficiently adapt to various VLIW processor architectures, improving instruction-level parallelism and code execution efficiency.

Embodiments of the present application disclose a method, device, equipment, medium and program product for generating an adversarial sample. The method comprises: obtaining a preset code file; determining a non-conditional jump instruction in the preset code file; modifying the non-conditional jump instruction into a reconstructed jump instruction according to a preset instruction modification rule; performing control flow flattening processing on a basic block of the preset code file; based on a result of the control flow flattening processing, inserting a preset application programming interface (API) sequence into the preset code file according to a preset rule to obtain a target code file containing a malicious code feature; inserting noise into the target code file to obtain an initial sample; and performing iteration on the initial sample according to a preset evolution algorithm to obtain an adversarial sample. The embodiments of the present application can generate a large number of malicious code adversarial samples that can evade antivirus software and sandboxes.

The present application relates to the binary function similarity detection method of strengthening instruction execution semantics, belongs to network security technical field, first through IDA obtains the assembly code basic block of binary function, secondly, the instruction features of basic block are extracted using Word2vec, specific instructions in basic block are marked according to execution semantics table simultaneously, and instruction execution semantic representation sequence is generated according to execution order, then the instruction features and instruction execution semantic representation are fused to generate basic block embedding, and binary function embedding is generated based on basic block embedding using graph embedding network, finally, binary function similarity detection is carried out using twin network, the present application proposes a basic block instruction execution semantic representation method aiming at the problem that existing basic block embedding generation method does not make full use of instruction execution semantics, strengthens instruction execution semantic features, and improves the accuracy of binary function similarity detection.

The invention discloses a computational efficient point cloud analysis method based on a grouping selective state space, and the method comprises the steps: firstly, a sequence extension module carries out the serialization of points along each axis, and enables a disordered point cloud to more stably adapt to the causal characteristics of Mamba without parameters; secondly, sorting prompt and position embedding are adopted to provide sorting and position information for the point sequence respectively, so that geometric semantics are better captured; thirdly, the chain type bidirectional Mama enables the forward process and the reverse process in the parallel bidirectional Mama to be connected in series, a global receptive field on a point sequence is provided, and meanwhile high-order geometric information is captured in the scanning process. And fourthly, the grouping selective state space model introduces parameter sharing among multiple dimensions into the selective state space model, so that overfitting caused by a calculation mode in the selective state space model is relieved. And 5, a sequence merging module fuses corresponding high-order interaction features obtained through causal reasoning on different sequences. And finally, packaging the flow into a basic block, and embedding the basic block into a standard codec architecture for hierarchical feature aggregation. According to the method, the accuracy of point cloud analysis based on the state space model is improved while the calculation efficiency is ensured.

The invention discloses a cross-ISA (Industrial Standard Architecture) extension program translation method based on binary rewriting, which comprises the following steps of: 1) naming an instruction set ISA of a program to be translated as an original ISA, and naming an instruction set ISA on target hardware for running original ISA extension as a target ISA; 2) performing comparative analysis on a binary file corresponding to the original ISA extension compilation and a binary file corresponding to the target ISA extension compilation to obtain an instruction needing to be translated relative to the target ISA extension in the original ISA extension, and segmenting the instruction into a plurality of program basic blocks needing to be translated; 3) allocating a jump instruction and an address space for translating and storing translated codes to each program basic block; (4) distributing the program basic blocks into the corresponding address spaces through a jump instruction to carry out static binary translation, and generating a static file; and (5) distributing a loading address for the static file by utilizing a loader according to the address distribution information in the static file, and loading the static file to a corresponding position.

Embodiments of the present application provide a tensor instruction optimization method and device and a storage medium, and relate to the technical field of artificial intelligence chips. The method comprises: sequentially traversing N tensor instructions in a target basic block; if there is a target instruction on which a currently traversed tensor instruction depends, and there are L intermediate instructions between the tensor instruction and the target instruction, obtaining total additional time based on the additional execution time of each of the L intermediate instructions; and if the total additional time is greater than the unit execution time of the currently traversed tensor instruction, it is indicated that the target instruction on which the currently traversed tensor instruction depends has been executed when the pipeline executes the currently traversed tensor instruction, so the dependency descriptor of the currently traversed tensor instruction is set to a first descriptor to represent no dependency relationship. In this way, the pipeline can directly execute the tensor instruction without waiting, thereby reducing the probability of pipeline blocking, reducing the idling of hardware resources in the pipeline, and improving the utilization rate of hardware resources.

This application relates to a fuzz testing visualization method, apparatus, computer device, computer-readable storage medium, and computer program product. The method includes: acquiring program information of a target test program; the target test program includes at least one function; the program information indicates the number of basic blocks contained in each function and the number of transition paths between basic blocks; generating an overall program graph corresponding to the target test program based on the program information; wherein the overall program graph includes graphical elements representing each function; each graphical element includes graphical sub-elements representing basic blocks in the corresponding function; acquiring a fuzz test log corresponding to the target test program, recording the coverage of basic blocks by the fuzz test seed during fuzz testing of the target test program; color-coding the graphical sub-elements in the overall program graph based on the fuzz test log to generate a program state graph. This method can improve fuzz testing efficiency.

Methods and apparatus for a runahead process are provided to prevent frontend stalls when executing a computer program. Methods and apparatus profile and analyze the computer program when it is compiled to extract meta-data defining hyperblocks for the computer program. The hyperblocks each encompass a respective series of basic blocks having transitions that meet a specified threshold. When the computer program is executed, the runahead process is performed for program branches. In this process, a future path of hyperblocks is predicted from each branch and the instructions corresponding to those hyperblocks are prefetched to a memory cache so that they can be readily fetched. Cycles or large call stacks are removed to enable deep runaheads, which may span about a thousand instructions.

The invention provides a binary program static analysis method based on a comprehensive control flow diagram. According to the scheme, the method comprises preprocessing, a control flow diagram generation module, a reverse control flow diagram generation module, target address ambiguity instruction recognition and a specific basic block path. The control flow diagram generation module obtains binary program information through preprocessing and generates a control flow diagram by using a breadth-first search algorithm. The reverse control flow diagram generation module initializes a reverse control flow diagram and generates a reverse edge by traversing the control flow diagram. A target address ambiguity instruction analysis module identifies a target address ambiguity jump or call instruction in the basic block. The specific basic block path analysis module uses a path search algorithm to obtain all paths of a specific basic block, and analyzes execution conditions of the paths through a symbolic execution technology. According to the method, the binary program can be comprehensively analyzed, the analysis efficiency and accuracy are improved, and powerful support is provided for software security and quality improvement.

Embodiments of the present application provide an exception recovery method, device and electronic equipment, which are applied to a binary translation system, the binary translation system is used for translating a source program in a client into a target program in a host, and the method comprises the following steps: in the case of an exception, determining a source instruction corresponding to a target instruction triggering the exception and a basic block in the source program, and marking a target position corresponding to the source instruction in the source program; determining an offset value corresponding to a target register according to the target position and a register delay calculation algorithm; the target register comprises registers corresponding to each instruction between a start position of the basic block and the target position and within a correction range of the register delay calculation algorithm; and correcting a value of the target register according to the offset value. Embodiments of the present application can solve problems such as incorrect register values caused by register delay optimization in the binary translation process in the case of exceptions, self-modifying code and other special cases, and improve the exception recovery efficiency.

Embodiments of the invention disclose an instruction fusion method and apparatus, an electronic device, a storage medium and a program product. The method comprises the steps of obtaining a to-be-optimized program; when it is determined that all instructions in the to-be-optimized program belong to the same basic block and the instructions with the dependency relationship in the to-be-optimized program are adjacently arranged, all continuous instruction sequences in the to-be-optimized program are obtained, to-be-fused instruction sequences are determined in all the continuous instruction sequences, and each set of to-be-fused instruction sequences is replaced with a corresponding fusion instruction; when it is determined that all the instructions in the to-be-optimized program do not belong to the same basic block or the instructions with the dependency relationship in the to-be-optimized program are not adjacently arranged, obtaining candidate instructions in the to-be-optimized program, determining to-be-fused instructions in the candidate instructions according to the fixed value-use chains corresponding to the candidate instructions, and fusing the to-be-fused instructions in the to-be-optimized program according to the determined to-be-fused instructions in the to-be-optimized program. And the target instruction sequence corresponding to each instruction to be fused is replaced with the corresponding fusion instruction, so that the program optimization efficiency and the program optimization capability are balanced.

The application discloses a kind of based on symbol execution's malicious code obfuscation technology static repair method, belong to software analysis technical field, main in solving the malicious software static escape problem when existing static analysis technique faces obfuscated malicious software.The main scheme includes the basic static analysis to the tested Android application to obtain the sensitive API list and original graph feature in the tested Android application;According to the sensitive API list obtained, write hook function to simulate sensitive API list function, generate function replacement table, use symbol execution technology to simulate running Android application, replace part of function according to function replacement table in this process, finally obtain the overall execution state information and the block information of basic block when Android application simulation executes;According to state information and block information, prune and reconstruct original graph feature to realize static repair, exclude static obfuscation information, and mine effective graph feature therein.

The invention relates to the technical field of software testing, in particular to a directional fuzzy testing method, system and device based on data transaction software branch behavior modeling and a storage medium. Executing path tracking, recording basic block jump by utilizing an instrumentation technology, and collecting path information during program running; key branch identification is carried out based on path information, the influence weight is calculated by integrating the branch execution frequency, the control dependency relationship and the path expansibility, and a high-influence branch is determined; constructing a test data generation strategy driven by reinforcement learning, setting a key branch coverage reward and a global path exploration reward, and optimizing a test data generation direction; performing input data variation based on the generated test data, positioning key bytes influencing a target branch through forward gradient analysis, and performing accurate variation; and testing data verification and feedback adjustment, evaluating a branch coverage rate and key branch triggering times, and feeding back a result to the reinforcement learning strategy dynamic adjustment parameter.

The invention discloses an LLM-based smart contract event log security analysis method and system. The method comprises the following steps: acquiring a byte code and a source code of a target smart contract, and analyzing the byte code and the source code; decompiling to generate an intermediate code based on the bytecode to construct a contract internal control flow graph (ICFG) so as to mark basic blocks and functions involving key state variable modification; constructing an event parameter dependency graph (EPDG) based on the source code to track a static data dependency path between the event parameter and the state variable; performing event completeness detection by combining LLM with ICFG so as to judge whether a corresponding event is triggered or not after the state variable is modified; event consistency detection is performed by combining LLM with EPDG, so that whether event parameters are consistent with actual state change or not is judged; optimizing an LLM reasoning process based on a multi-round questioning mechanism and a thinking chain prompting technology; and outputting a security analysis report containing the location, the type and the cause of the vulnerability.

This invention discloses a method for accelerating numerical computation software based on CPU-GPU collaboration. The method divides the program into basic blocks and uses a code analysis module to predict the runtime information of these basic blocks, including whether they are computationally intensive tasks, whether they are easily parallelized, and whether the memory copy time of the computation task is less than the CPU execution time. Based on the analysis results, basic blocks that meet the above conditions are marked as GPU modules, and the rest are CPU modules. GPU modules are compiled into GPU code for execution on the fly. If CPU modules have hotspot code, they are compiled into machine code on the fly for execution; otherwise, they are interpreted. This method employs a CPU-GPU collaborative just-in-time compilation approach, fully utilizing CPU and GPU computing resources, achieving higher execution efficiency than CPU or GPU execution alone. It also leverages the advantages of just-in-time compilation of interpreted languages, significantly improving the performance of numerical computation software.

This application discloses a tensor program performance prediction method and system based on LLVM, relating to the field of computer system performance modeling and compiler optimization technology. This invention determines the instruction type of each instruction by semantic recognition of the tensor intermediate representation and transforms the instructions into task nodes with semantic tags. By calculating the symbolic execution count and corresponding execution cost of each instruction type tag within each basic block, the program load is quantified without executing the code. Furthermore, the basic blocks are scheduled and arranged under the physical resource constraints of the target hardware, achieving deep coupling between program logic semantics and hardware physical constraints. Finally, the total predicted execution time of the entire tensor program is obtained based on the predicted execution time of each basic block and the number of times each basic block appears. This enables accurate evaluation of the execution time of a high-performance tensor kernel without running on the target hardware platform.

This application provides an OPC model training method and an OPC model training device, relating to the field of model training technology. The method includes: cutting a chip design layout file to obtain multiple basic blocks; adding noise to the multiple basic blocks to obtain multiple noisy blocks; training a graph generator based on the multiple noisy blocks and corresponding real noise; using the graph generator to generate multiple test graphs based on multiple preset noise vectors; and training the model based on the multiple test graphs to obtain an OPC model. By training the graph generator based on the multiple noisy blocks and corresponding real noise, the graph generator implicitly learns the data distribution of the graphs, that is, it learns the rules of chip design. This results in multiple test graphs generated by the graph generator having more diverse forms and conforming to design rules. The OPC model trained based on these multiple test graphs is also more accurate and reliable.

The invention provides an instruction set optimization and compilation scheduling method and system for an artificial intelligence chip, and relates to the technical field of artificial intelligence, and the method comprises the steps: carrying out the multi-level abstract modeling of a neural network calculation graph, constructing a cross-basic-block instruction movement legality judgment mechanism, and carrying out the compilation scheduling of the instruction set. And analyzing the space-time locality characteristics of the instruction sequence to establish a data multiplexing mode, pre-planning a data migration path, cooperatively mapping with the on-chip interconnection network, and finally generating a target code and dynamically adjusting. The AI chip computing efficiency can be improved, power consumption can be reduced, the resource utilization rate can be optimized, and the chip adaptability can be enhanced.

This invention discloses a method for generating formal software models based on control flow graphs and large language models. The method includes the following steps: parsing the source code to be analyzed using an abstract syntax tree and constructing a control flow graph; assigning a unique node identifier to each node in the control flow graph, corresponding to the basic blocks of the program; declaring all variables in the source program, introducing a program counter variable, constructing a state machine structure model, and generating intermediate representation code in a state machine style based on the control flow graph; using the intermediate representation code and the control flow graph, guiding the large language model to generate a formal model through constraint hint templates; performing syntax constraint verification and test case-driven closed-loop verification on the formal model, iteratively refining the formal model. This invention solves the problems of existing formal model construction in software formal verification processes being highly dependent on manual labor, having low automation, and being difficult to accurately characterize complex control structures.

The embodiment of the invention discloses a binary code optimization method and system, an electronic device, a medium and a program product, based on a function call graph and basic block control flow graphs, topological sorting is carried out on each basic block control flow graph, the code execution sequence is optimized, branch prediction errors are reduced, instruction rewriting is carried out based on the topological sorting result, and the efficiency is improved. By means of the method, accurate rewriting of key instructions can be achieved according to the characteristics of a specific system architecture (such as an ARM64 architecture), the accuracy of address calculation is guaranteed, function inline expansion (namely target function calling) is selectively conducted in the inline expansion process through strict context management, the function calling overhead is reduced, and the function calling efficiency is improved. And finally, recoding the code of which the inline expansion is completed to generate a final optimized target binary code, so that multiple means such as inline, code layout and instruction-level optimization are comprehensively utilized to realize a deep optimization effect on the binary code on the premise of keeping semantics strictly unchanged.

Systems and methods are described for scheduling instructions corresponding to a computer program. A neural instruction scheduler operates by iterating over all the basic blocks (BBs) in the directed acyclic graph (DAG). The nodes of the DAG, which represent instructions in the form of compiler IR, are tokenized such that tokens retrieve embeddings from an embedding space. These embeddings are aggregated into a single vector that represents the instructions in a latent semantic space. The embeddings are fed into a value estimator which predicts performance metrics associated with scheduling each valid instruction and compares them against one another to determine which instruction to pick next. The process of picking the next instruction can begin using the same approach. This process is autoregressively repeated for all valid instructions. Candidate instruction schedule(s) with identified ordering of instructions are output and an instruction schedule is selected to schedule each basic block.

This application provides a method and apparatus for cross-architecture binary code similarity detection, comprising: parsing a binary file, analyzing the instruction set, and obtaining function assembly code, a function symbol table, and a string table; constructing a program control flow graph with basic blocks as nodes and control dependencies between basic blocks as edges based on the function assembly instructions and the stack; constructing an assembly instruction sequence based on the program control flow graph; standardizing the instructions according to their functions and operand types; constructing a cross-architecture instruction comparison set based on the standardized instructions; identifying functionally similar instructions under different architectures based on a comparison learning task; modeling the semantic relationships between instructions using a deep learning model to generate embedded representations of the instructions; and performing similarity analysis based on the embedded vectors output by the model to generate similarity detection results. This application can effectively detect the similarity between binary files of different architectures, improving the accuracy and robustness of the detection.

The application relates to the technical field of artificial intelligence chips, in particular to a GPU instruction copy propagation method and device, a storage medium and a program product. The method comprises the following steps: obtaining a control flow graph and a work list of a target program; calculating a fixed point based on the work list and a data flow equation; identifying a thread bundle to which a basic block in the control flow graph belongs; collecting GPU instructions requiring global copy propagation in the basic blocks in each thread bundle; performing safety checking on the basic blocks in each thread bundle to obtain a first checking result; if the first checking result indicates that the checking is passed, performing copy propagation of the GPU instructions in the same thread bundle until the copy propagation is stopped when the fixed point is reached. The method can effectively improve the optimization effect of a GPU compiler.

The invention belongs to the field of CPG file generation, and particularly relates to a project-level CPG file generation method, system and device and a storage medium, and the method comprises the steps: generating an abstract syntax tree according to a screened file set, traversing nodes for generating action ranges in the abstract syntax tree, and obtaining a node relationship; establishing a dependency edge according to the abstract syntax tree and the node relationship; processing a branch structure, a loop structure and a jump structure according to the abstract syntax tree to obtain a control flow edge; traversing the abstract syntax tree and establishing a dependency edge, otherwise, storing the position of the calling block and the calling information into an import function table, establishing a calling edge, and obtaining a single CPG file according to the calling edge, the dependency edge, the control flow edge and the basic block; and generating a project-level CPG file according to the abstract syntax tree generation file index in combination with the single CPG file. The method has the advantages that structured data support is provided for static analysis of a large-scale Lua project, and the static analysis efficiency can be greatly improved.