260 results about "Basic block" patented technology

The embodiment of the invention provides a binary translation method, a binary translator, electronic equipment and a readable storage medium, and the method comprises the steps: obtaining a thread mode of a client program when an indirect jump instruction in the client program is translated; generating a target search code sequence according to the thread mode; wherein different thread modes correspond to different target search code sequences; the target search code sequence is used for searching a target jump table based on a jump target address of the indirect jump instruction to obtain a cache initial address of a translated basic block corresponding to the jump target address; and if the target search code sequence is successfully searched, skipping to a cache initial address of the translated basic block corresponding to the skipping target address. According to the embodiment of the invention, the translation of the indirect jump instruction can be optimized, and the efficiency of searching the indirect jump table is improved, so that the running efficiency of a translated program is improved.

The invention provides a BLAS3 structured operator accelerated computing system based on a Hopper architecture GPU, and relates to the technical field of computers. The system comprises: a calculation unit discrimination module for determining a calculation unit used by a current operator during operation, and estimating the maximum row dimension upper bound of the current operator in a tensor core execution path; an instruction sensing block parameter determination module dynamically determines the optimal block size and number of the input matrix in real time; the block matrix loading and aligning module divides an input matrix and a matrix to be updated into sub-matrixes by taking the block size as a basic block and completes loading of the corresponding sub-matrixes; the operator kernel function execution module completes shared memory structured parallel loading and storage of a double-precision floating-point number array of a sub-matrix corresponding to the input matrix, and calls a tensor core to carry out multiply-add accumulation calculation; and the assembly line and concurrent scheduling module adds the block calculation tasks into corresponding task sets and performs multi-stream concurrent scheduling on the task sets.

The invention provides a binary translation system applied to an X86 program, which is used for translating a source program following X86 semantics into a target program following other semantics, and comprises a data acquisition module used for acquiring the source program; the disassembling module is used for dividing a source program into a plurality of basic blocks and analyzing subsequent basic blocks corresponding to each basic block; the backward data flow analysis module is used for sequentially analyzing each instruction in each basic block from back to front so as to obtain a target definition set and a target subsequent use set corresponding to each instruction in the source program; and the translation module is used for eliminating redundant instructions of high-order zero clearing or high-order retention of the general register generated in translation. According to the technical scheme, the register state of the general register corresponding to each instruction of the source program is analyzed through the backward data flow analysis module so as to eliminate redundant instructions generated in the translation process.

A method includes creating, by at least one processor of at least one electronic device, a guided dialogue, wherein the guided dialogue includes programming blocks corresponding to queries and associated rules, and wherein the programming blocks are structured to include one or more query base blocks having associated rule blocks. The method also includes deploying, by the at least one processor, the guided dialogue at an online-accessible location, wherein a request from another electronic device to access the deployed guided dialogue causes execution of the deployed guided dialogue in response to the request. The method also includes using one or more machine learning models to enable creation of the guided dialogue based on learned patterns and outputs from other dialogues, and to continually recommend or provide refinements to the dialogue to enhance the dialogue and optimize recommendations provided by the dialogue.

The invention belongs to the technical field of applet privacy leakage detection methods, and discloses an applet privacy leakage detection method and system based on an abstract syntax tree. Decompiling the packaged file of the applet to obtain a source code file; all the logic layer JavaScript files are converted into AST by using an expression analysis library; obtaining a calling dependency graph between a page logic layer file and a tool file layer according to the file reference relationship, obtaining a field-level binding dependency graph of the page logic layer file and the tool file layer according to a data and event binding relationship of the page rendering layer and the page logic layer, and merging the two layers to obtain a global dependency graph; finally, combining the dependency graphs to generate a global dependency relationship graph; dividing the JavaSript code into a plurality of basic blocks according to the dividing rule of the boundary of the control flow, determining the type of the edge according to the information of the boundary, and obtaining a GCFG by combining the dependency graph; and inputting the GCFG into a taint-pointer analysis module, and obtaining a privacy disclosure path according to predefined sink and source libraries and a data flow propagation rule.

The invention relates to the technical field of software testing, and discloses a code coverage rate determination method and device, computer equipment and a storage medium, and the method comprises the following steps: obtaining a plurality of source code files of a firmware module of a disk array card, compiling the source code files into execution files, performing instrumentation processing on the plurality of source code files in the compiling process, and obtaining the execution files; the execution information of each source code is updated when the execution file is operated; generating basic block files corresponding to the plurality of source code files, wherein the basic block files comprise pointers pointing to execution information of the corresponding source code files; running the execution file to enable the disk array card to map execution information of the basic block file and the source code file to a host cache region; after the execution file is operated, obtaining execution information of each source code file, and writing the execution information into an execution information file; and analyzing the execution information file and the basic block file to obtain the code coverage rate of each source code file. According to the invention, the coverage rate of the software code of the disk array card can be obtained.

The invention discloses an instruction-level code optimization method and device based on template matching, a medium and equipment. According to the method, instruction-level codes serve as input, the input instruction-level codes are firstly constructed into corresponding control flow diagrams, then value ranges of active variables and register quantities are initialized based on the control flow diagrams, then variable assignment instructions and related instructions are found out from instruction sequences of basic blocks to form instruction segments to be optimized, and the instruction segments to be optimized are optimized. The method comprises the following steps of: optimizing an instruction fragment, obtaining an optimized instruction fragment through template matching, performing SMT equivalence verification on the instruction fragment before and after optimization based on an active variable and a value range of a register quantity, and finally optimizing an input instruction-level code in a manner of replacing the instruction fragment before optimization with the optimized instruction fragment which is verified to be equivalent. And finally, the optimized instruction-level code is obtained.

A method includes fetching, at a program counter value, an instruction of a basic block of code; decoding the instruction; updating a checksum value with a checksum of the instruction; and determining whether a tuple of the program counter value and the checksum value is in an approximate membership query filter (AMQ-filter).

The invention belongs to the technical field of embedded system information security, and discloses an embedded program integrity multi-granularity verification system and method based on hardware on chip. According to the method, the program integrity verification granularity is set to be an instruction level, a basic block level, a function level and a mixing level in a hardware and software mode, user operation is facilitated, and user selection is enriched; meanwhile, the storage and retrieval efficiency of the reference tag is improved based on a hash table algorithm and a stack structure; in addition, on the basis of the characteristics of a sponge structure hash function, a hash value is calculated by adopting multiple channels, so that the difficulty of destroying codes by external attacks is increased, and the time delay of hash calculation is effectively reduced; in addition, a dual verification mechanism based on a sampling value and a random number is adopted, the space occupied by reference tag storage can be reduced, errors can be found as early as possible, the inherent hysteresis of program integrity verification is relieved, and the method is suitable for safety protection and program integrity verification of an embedded system.

The present invention discloses a program static analysis method and system based on LLVM, belonging to the technical field of computer program analysis. The technical problem to be solved is that the existing program analysis technologies have low accuracy, low efficiency and limited application scope in estimating program performance characteristics and memory reuse distance distribution. The method includes: converting a source file into an LLVM IR file with source-level debugging information; traversing modules, functions, basic blocks and instructions in the LLVM IR file to obtain static trace information of a target function; constructing a basic block-level control flow graph of the LLVM IR file and annotating relevant information; identifying and annotating loop information when traversing paths to obtain an execution path with loop annotations, replacing basic blocks in the execution path with corresponding memory access information, and generating a static memory trace with loop annotations; calculating the memory access reuse distance distribution through a recursive algorithm based on the static memory trace with loop annotations.

The invention discloses an automatic design method and device for a complex special instruction of hardware, a medium and a product, and relates to special hardware design, special instruction design or instruction set extension. The method comprises the steps that an analysis program collects dynamic information; basic blocks in the program are converted into a data dependency graph based on the intermediate representation of the compiler, and seeds are extracted; adopting a genetic algorithm to obtain candidate items of full input and output limitation based on the seeds; scoring the candidate items by adopting a specially designed cost model to serve as a screening basis; the overlapping problem of candidate items is solved through maximum weighted independent set analysis; and fusing the sub-graphs corresponding to the special instruction, generating a special function unit, and completing the automatic design of the complex special instruction of the hardware. According to the method, the similarity between the basic blocks can be explored, and common and frequently executed code snippets are found from a program to serve as special instructions; searching can cover a target program to the maximum degree, and the program is fully accelerated.

The invention belongs to the field of micro-architecture design of an integrated circuit processor. The invention provides an H2P branch prediction chip circuit architecture based on BrPerceptron, a variable operation track of a program is constructed based on a context-sensitive variable tracking mechanism, a program execution path topology is constructed based on a basic block division algorithm according to the variable operation track, multi-dimensional correlation detection is performed according to the program execution path topology to judge whether an H2P branch exists or not, and if yes, the H2P branch is predicted. And when the H2P branch instruction is judged to be the H2P branch instruction, enabling the BrPerceptron predictor to output, performing multi-stage feature fusion and outputting a prediction result, and realizing high-precision prediction for the H2P branch instruction.

The embodiment of the invention provides a basic block linking method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: in the process of executing a target search code, judging whether a jump source basic block meets a de-linking condition or not; the target search code is used for searching an initial address of the translated basic block corresponding to the jump target basic block in the code cache; the jump target basic block is a basic block to which the jump source basic block is to jump; the unlinking conditions comprise that the jump target basic block crosses pages, the virtual-real address mapping relation of the jump target basic block is changed, and the jump source basic block is in a linked state; if it is determined that the jump source basic block meets the unlinking condition, basic block unlinking is carried out on the jump source basic block; and carrying out basic block linking on the unlinked jump source basic block again. According to the embodiment of the invention, the number of times of searching the jump target basic block when the direct jump instruction is executed can be reduced, and the efficiency of executing the application program by the translator is improved.

The invention relates to the technical field of Internet of Things equipment security detection, in particular to an Internet of Things equipment vulnerability detection method and system based on sensitive target guidance, and the method comprises the steps: extracting firmware key information of to-be-detected equipment; obtaining potential sensitive targets and paths in firmware of the to-be-detected equipment and basic block positions corresponding to the sensitive targets and the paths through reachable data streams in decompilation code execution; performing pruning operation on the control flow diagram in the key information according to the positions of the basic blocks corresponding to the sensitive target and the path, and obtaining a test space related to the sensitive target and the path; variation is carried out on request processing information, parameter information and control information in the test space, and the test case is guided to be executed to a sensitive target; and performing collapse variation on the sensitive function parameters in the test space, triggering the firmware vulnerability of the to-be-detected equipment in the execution process of the test case, and generating a test result. According to the method, the blindness of fuzzy testing is reduced, and the method has good adaptability to firmware analysis of embedded equipment.

According to one aspect of the present disclosure, a system-on-chip (SoC) is provided. The SoC may identify a first set of instructions associated with parallel processing by a plurality of computational units. The SoC may input the first set of instructions associated with the parallel processing by the plurality of computational units into a Gaussian mixture model (GMM). The SoC may identify a second set of instructions for the parallel processing by the plurality of computational units as an output of the GMM. The second set of instructions may include a subset of the first set of instructions.

An analysis function providing method executed by an analysis function providing device includes first analyzing a virtual machine of a script engine, and acquiring a hook point that is a part where an analysis code is inserted by applying a hook, and a virtual program counter that is a variable indicating an instruction of the virtual machine to be executed next, second analyzing an instruction set architecture that is a system of instructions of the virtual machine and acquiring a branch virtual machine instruction that is a virtual machine instruction that causes branch, and providing an analysis function by applying a hook, to the hook point of the script engine, the hook including processing of, when an exception has occurred, changing a destination pointed by the virtual program counter to a head of a basic block immediately after a basic block in which the exception has occurred.

The invention provides a PLC control task execution time prediction method and device, equipment and a medium, and the method comprises the steps: carrying out the machine instruction processing of a PLC control task, and generating a machine instruction program corresponding to the PLC control task; carrying out basic block division processing on the machine instruction program, and determining a plurality of basic blocks in the machine instruction program; generating a control flow chart corresponding to the machine instruction program based on the pointing relationship among the plurality of basic blocks; and taking the total weight value of each basic block as the weight value of each basic block in the control flow chart, performing depth-first traversal on the control flow chart to predict a target execution path corresponding to the PLC control task, and determining the actual execution time of the PLC control task based on the total weight value of the target execution path and the clock period of the processor. The execution time of the PLC control task can be accurately predicted, and the problem of unreasonable task period setting is solved.

The invention discloses an intelligent contract vulnerability detection method based on a multi-level data dependence heterogeneous graph, and belongs to the technical field of intelligent contract security. Intelligent contract byte codes are used as input, contract byte codes are converted into operation codes, and a control-data heterogeneous graph with basic blocks as nodes is constructed; designing an in-block data dependency sub-graph, and forming multi-level data dependency with the inter-block data stream; based on the generated control-data heterogeneous graph, a feature weighted relation graph convolutional network is provided, and control flow and data flow feature weights are dynamically adjusted and optimized by using node static attributes such as dominating tree depth and the like, so that multi-modal semantic efficient aggregation is realized. According to the method, for the contract without a public source code on the block chain, vulnerability detection only for the bytecode of the intelligent contract is realized, and high detection efficiency can be achieved under the condition that the detection accuracy is guaranteed.

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: when a direct jump instruction in a first basic block is translated, identifying whether a second basic block to which the direct jump instruction is to jump crosses pages or not; if it is determined that the second basic block crosses pages, a target instruction sequence is inserted in front of an unoptimized instruction sequence translated by the direct jump instruction, the target instruction sequence is used for detecting whether the direct jump instruction meets an optimization condition or not, and jumping is conducted through the link instruction sequence under the condition that the direct jump instruction is detected to meet the optimization condition; the optimization condition comprises that the virtual and real address mapping relation of the second basic block is not changed; the link instruction sequence is used for skipping to an initial address of the translated basic block corresponding to the second basic block in the code cache. According to the embodiment of the invention, the execution of the direct jump instruction is optimized under the condition that the optimization condition is satisfied, so that the program running efficiency can be improved.

The invention discloses a code embedding method based on a semantic embedding vector generation model, which belongs to the technical field of computers, and comprises the following steps of: obtaining a binary code block, and performing disassembling processing and code structure analysis based on different granularities to obtain a basic block corresponding to the binary code block and a control flow diagram structure feature; performing assembly instruction linear conversion and cross-instruction-set semantic embedding conversion on the basis of the basic blocks corresponding to the binary code blocks and the structural features of the control flow graph to generate a unified binary code semantic embedding vector space corresponding to a cross-instruction-set architecture; obtaining a known vulnerability sample, and performing semantic vulnerability characterization analysis and candidate vulnerability retrieval positioning to generate a candidate vulnerability code block set; and carrying out dynamic analysis verification on the candidate vulnerability code block set and identifying a corresponding vulnerability repair state so as to output a corresponding binary vulnerability code block detection report. According to the method, high-precision semantic embedding of binary codes can be realized.

The invention discloses a performance optimization method and device of a graphics processor, electronic equipment and a storage medium, and relates to the technical field of computers, the performance optimization method comprises the steps that basic block execution data of a target program can be dynamically collected based on instrumentation logic compiled by a static library, and performance bottlenecks are accurately positioned by analyzing the data; meanwhile, the control flow and resource allocation are optimized in combination with the characteristics of the graphic processor micro-system structure, so that the technical problems of low efficiency of the control flow, resource imbalance, low memory access efficiency and the like of the graphic processor micro-system structure level can be solved; the technical effects of improving the calculation efficiency of the graphics processor, optimizing the resource utilization rate, reducing the energy consumption and improving the overall performance of the program are achieved.

The invention provides an analysis method and system based on confused PASS in LLVM, and relates to the technical field of software protection. The method comprises the following steps: extracting a target function from a confused binary program, positioning the position of an encrypted character string in the target function, and determining decryption logic according to the position of the encrypted character string; searching a target expression in the target function, identifying expression logic through a mode matching mode, and determining character string encryption algorithm parameters based on decryption logic and the expression logic; constructing a control flow diagram according to the expression logic, identifying control variables in the control flow diagram, and generating a state conversion diagram of the control variables according to an assignment sequence of the control variables; and identifying an identifier of a useless basic block in the target function according to the state transition diagram, and determining obfuscation implementation logic of the obfuscated binary program based on the character string encryption algorithm parameter and the identifier of the useless basic block. According to the technical scheme provided by the invention, reverse derivation of the confusion implementation logic can be realized.

The present invention provides an operating system kernel fuzz testing method, device and equipment, which relate to the field of kernel fuzz testing technology. By obtaining the initial input and splitting the initial input to generate an input set; performing fuzz testing on the input set and obtaining the fuzz testing results; storing the fuzz testing results in a key component inference file to generate a key component inference table; generating a seed selection strategy in the seed library in combination with the key component inference table to guide seed mutation selection. By identifying and utilizing the key components in the system call sequence, the coverage of the fuzz test is improved. A correspondence between the key components in the system call sequence and the corresponding path basic blocks is established to better explore potential security vulnerabilities. According to the selection of mutation points, different mutation strategies are executed to effectively improve the existing fuzz testing method and improve the efficiency and quality of vulnerability mining.

The invention provides a branch conversion method and device for instruction compilation preprocessing. The method comprises the following steps: determining a basic block actually having a control dependency relationship in an IR structure to be processed; converting the conditional branch instruction in the IR structure to be processed into a comparison assignment instruction of a corresponding prediction code; and based on the comparison assignment instruction, lifting the instruction of the basic block actually having the control dependency relationship into a predicate execution instruction. According to the method, the basic blocks actually having the control dependency relationship are determined, and then branch conversion is performed on the function having the control dependency and the data dependency at the same time in the processing process of the rear end of the compiler, so that the control dependency is converted into the data dependency, and more optimization space is provided for a scheduling algorithm for improving instruction level parallelism.

The invention discloses a remote sensing image target detection method based on improved RT-DETR and computer equipment, and relates to the field of deep learning and target detection, and the method comprises the steps: inputting a to-be-detected remote sensing image into an optimal remote sensing image target detection model, and obtaining a recognition result of the remote sensing image; the remote sensing image target detection model comprises an improved backbone network, an improved neck network and a head network; wherein the improved backbone network is a network which is obtained by replacing a Basic Block module with a Faster Block module in a backbone network of the RT-DETR network model; the improved neck network is a network obtained by integrating an MFEP-OK module and a CGAFusion module on the basis of a neck network of an RT-DETR network model. According to the method, the detection speed is ensured, and the detection accuracy of small targets and long-tail targets in a remote sensing image target detection model is improved.

The invention discloses a binary translation method and device, electronic equipment and a readable storage medium. The method comprises the steps of obtaining a translation result of each basic block from a cache of a translator; when an instruction in the translation result is executed, if it is determined that the currently executed instruction is a target instruction with memory access alignment abnormity, remapping is performed according to a first memory access address included in the target instruction, a second memory access address is generated, and a memory area corresponding to the first memory access address is configured to be inaccessible; and executing memory access operation aiming at the second memory access address to access data of the second memory access address. The problem that in the prior art, execution of all other threads is stopped unconditionally, and consequently the execution efficiency of source program instruction translation is affected can be solved.

The embodiment of the invention relates to an instruction execution method and device, a processor and a related product, an MIMD framework is adopted in a GPU, a first SIMT stack and a second SIMT stack are configured for managing execution information of different branch basic blocks in the same thread bundle, and on the basis, the execution information of the different branch basic blocks in the same thread bundle can be managed through the first SIMT stack and the second SIMT stack. According to the method, the state of at least one of a first SIMT stack and a second SIMT stack is updated according to a basic block to be executed, and under the condition that the updated first SIMT stack and the updated second SIMT stack are both non-empty, instructions in all branch basic blocks are taken out respectively according to execution information of the first SIMT stack and execution information of the second SIMT stack and transmitted to an MIMD for concurrent execution. According to the method, when the execution channels of the MIMD concurrently execute the branch instructions, the resource utilization rate of the ALU can be improved, and therefore the running performance of a GPU program is improved.

The invention provides a concurrent vulnerability fuzzy test method and device supporting reproduction, and relates to the technical field of computers, the method comprises the following steps: obtaining a target program obtained by rewriting an original binary program; wherein the target program comprises a plurality of key basic blocks, and the execution sequence of the key basic blocks is used as a thread interleaving feedback signal; performing thread staggering variation based on the key basic block to generate a plurality of target test cases containing a plurality of thread staggering conditions; performing a fuzzy test based on the plurality of target test cases, and reproducing a crash scene based on execution information of the target program under the condition that the target program is triggered to crash in the fuzzy test process; wherein the execution information is obtained by recording the execution sequence of the key basic blocks in the execution process of the target program. Through the method provided by the invention, concurrent vulnerabilities can be effectively mined, and recurrent fuzz testing can be carried out.

The invention discloses a program performance analysis method and device, equipment, a storage medium and a computer program, and belongs to the field of computers. The method comprises the following steps: providing a program test interface, wherein the program test interface is used for obtaining a rendering program to be tested; obtaining program performance parameters of the rendering program in a plurality of feature collection levels, wherein the plurality of feature collection levels comprise one or more of the following levels: a drawing calling level, a shader level, a basic block level and an instruction level; and determining the performance bottleneck of the rendering program based on the obtained program performance parameters. Namely, according to the application, the program performance parameters of the rendering program at the plurality of feature acquisition levels are obtained, so that the performance bottleneck of the rendering program is determined based on the program performance parameters of the plurality of feature acquisition levels. Therefore, through hierarchical data acquisition and analysis, the efficiency of determining the performance bottleneck of the rendering program is improved.

The invention relates to the field of code vulnerability detection, in particular to a binary vulnerability retrieval and positioning method and system based on high-dimensional vulnerability characterization, and the method comprises the steps: firstly inputting a binary file, analyzing the structural information of the binary file, and analyzing a machine instruction; extracting binary file function information, generating a cross-platform basic block IR instruction sequence, constructing a control flow graph, and constructing a data dependency graph; splicing the program dependency graph feature vector and the basic block IR instruction sequence feature vector, and performing multi-modal feature fusion to generate a comprehensive high-dimensional vulnerability representation vector; and finally, inputting the high-dimensional vulnerability representation vector into an index for searching to obtain a plurality of nearest neighbor indexes and distances, converting the distances into similarity, filtering according to a similarity threshold to obtain a most similar vulnerability vector, and obtaining vulnerability information and vulnerability positions corresponding to the vulnerability vector. The problems that traditional binary vulnerability detection cross-platform and compiler optimization detection fails and the result reliability is low are solved.