210 results about "Basic block" patented technology

The invention provides a BLAS3 structured operator accelerated computing system based on a Hopper architecture GPU, and relates to the technical field of computers. The system comprises: a calculation unit discrimination module for determining a calculation unit used by a current operator during operation, and estimating the maximum row dimension upper bound of the current operator in a tensor core execution path; an instruction sensing block parameter determination module dynamically determines the optimal block size and number of the input matrix in real time; the block matrix loading and aligning module divides an input matrix and a matrix to be updated into sub-matrixes by taking the block size as a basic block and completes loading of the corresponding sub-matrixes; the operator kernel function execution module completes shared memory structured parallel loading and storage of a double-precision floating-point number array of a sub-matrix corresponding to the input matrix, and calls a tensor core to carry out multiply-add accumulation calculation; and the assembly line and concurrent scheduling module adds the block calculation tasks into corresponding task sets and performs multi-stream concurrent scheduling on the task sets.

The invention provides a binary translation system applied to an X86 program, which is used for translating a source program following X86 semantics into a target program following other semantics, and comprises a data acquisition module used for acquiring the source program; the disassembling module is used for dividing a source program into a plurality of basic blocks and analyzing subsequent basic blocks corresponding to each basic block; the backward data flow analysis module is used for sequentially analyzing each instruction in each basic block from back to front so as to obtain a target definition set and a target subsequent use set corresponding to each instruction in the source program; and the translation module is used for eliminating redundant instructions of high-order zero clearing or high-order retention of the general register generated in translation. According to the technical scheme, the register state of the general register corresponding to each instruction of the source program is analyzed through the backward data flow analysis module so as to eliminate redundant instructions generated in the translation process.

The invention belongs to the technical field of applet privacy leakage detection methods, and discloses an applet privacy leakage detection method and system based on an abstract syntax tree. Decompiling the packaged file of the applet to obtain a source code file; all the logic layer JavaScript files are converted into AST by using an expression analysis library; obtaining a calling dependency graph between a page logic layer file and a tool file layer according to the file reference relationship, obtaining a field-level binding dependency graph of the page logic layer file and the tool file layer according to a data and event binding relationship of the page rendering layer and the page logic layer, and merging the two layers to obtain a global dependency graph; finally, combining the dependency graphs to generate a global dependency relationship graph; dividing the JavaSript code into a plurality of basic blocks according to the dividing rule of the boundary of the control flow, determining the type of the edge according to the information of the boundary, and obtaining a GCFG by combining the dependency graph; and inputting the GCFG into a taint-pointer analysis module, and obtaining a privacy disclosure path according to predefined sink and source libraries and a data flow propagation rule.

The invention discloses an instruction-level code optimization method and device based on template matching, a medium and equipment. According to the method, instruction-level codes serve as input, the input instruction-level codes are firstly constructed into corresponding control flow diagrams, then value ranges of active variables and register quantities are initialized based on the control flow diagrams, then variable assignment instructions and related instructions are found out from instruction sequences of basic blocks to form instruction segments to be optimized, and the instruction segments to be optimized are optimized. The method comprises the following steps of: optimizing an instruction fragment, obtaining an optimized instruction fragment through template matching, performing SMT equivalence verification on the instruction fragment before and after optimization based on an active variable and a value range of a register quantity, and finally optimizing an input instruction-level code in a manner of replacing the instruction fragment before optimization with the optimized instruction fragment which is verified to be equivalent. And finally, the optimized instruction-level code is obtained.

A method includes fetching, at a program counter value, an instruction of a basic block of code; decoding the instruction; updating a checksum value with a checksum of the instruction; and determining whether a tuple of the program counter value and the checksum value is in an approximate membership query filter (AMQ-filter).

The invention belongs to the technical field of embedded system information security, and discloses an embedded program integrity multi-granularity verification system and method based on hardware on chip. According to the method, the program integrity verification granularity is set to be an instruction level, a basic block level, a function level and a mixing level in a hardware and software mode, user operation is facilitated, and user selection is enriched; meanwhile, the storage and retrieval efficiency of the reference tag is improved based on a hash table algorithm and a stack structure; in addition, on the basis of the characteristics of a sponge structure hash function, a hash value is calculated by adopting multiple channels, so that the difficulty of destroying codes by external attacks is increased, and the time delay of hash calculation is effectively reduced; in addition, a dual verification mechanism based on a sampling value and a random number is adopted, the space occupied by reference tag storage can be reduced, errors can be found as early as possible, the inherent hysteresis of program integrity verification is relieved, and the method is suitable for safety protection and program integrity verification of an embedded system.

The present invention discloses a program static analysis method and system based on LLVM, belonging to the technical field of computer program analysis. The technical problem to be solved is that the existing program analysis technologies have low accuracy, low efficiency and limited application scope in estimating program performance characteristics and memory reuse distance distribution. The method includes: converting a source file into an LLVM IR file with source-level debugging information; traversing modules, functions, basic blocks and instructions in the LLVM IR file to obtain static trace information of a target function; constructing a basic block-level control flow graph of the LLVM IR file and annotating relevant information; identifying and annotating loop information when traversing paths to obtain an execution path with loop annotations, replacing basic blocks in the execution path with corresponding memory access information, and generating a static memory trace with loop annotations; calculating the memory access reuse distance distribution through a recursive algorithm based on the static memory trace with loop annotations.

The invention belongs to the field of micro-architecture design of an integrated circuit processor. The invention provides an H2P branch prediction chip circuit architecture based on BrPerceptron, a variable operation track of a program is constructed based on a context-sensitive variable tracking mechanism, a program execution path topology is constructed based on a basic block division algorithm according to the variable operation track, multi-dimensional correlation detection is performed according to the program execution path topology to judge whether an H2P branch exists or not, and if yes, the H2P branch is predicted. And when the H2P branch instruction is judged to be the H2P branch instruction, enabling the BrPerceptron predictor to output, performing multi-stage feature fusion and outputting a prediction result, and realizing high-precision prediction for the H2P branch instruction.

The embodiment of the invention provides a basic block linking method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: in the process of executing a target search code, judging whether a jump source basic block meets a de-linking condition or not; the target search code is used for searching an initial address of the translated basic block corresponding to the jump target basic block in the code cache; the jump target basic block is a basic block to which the jump source basic block is to jump; the unlinking conditions comprise that the jump target basic block crosses pages, the virtual-real address mapping relation of the jump target basic block is changed, and the jump source basic block is in a linked state; if it is determined that the jump source basic block meets the unlinking condition, basic block unlinking is carried out on the jump source basic block; and carrying out basic block linking on the unlinked jump source basic block again. According to the embodiment of the invention, the number of times of searching the jump target basic block when the direct jump instruction is executed can be reduced, and the efficiency of executing the application program by the translator is improved.

The invention relates to the technical field of Internet of Things equipment security detection, in particular to an Internet of Things equipment vulnerability detection method and system based on sensitive target guidance, and the method comprises the steps: extracting firmware key information of to-be-detected equipment; obtaining potential sensitive targets and paths in firmware of the to-be-detected equipment and basic block positions corresponding to the sensitive targets and the paths through reachable data streams in decompilation code execution; performing pruning operation on the control flow diagram in the key information according to the positions of the basic blocks corresponding to the sensitive target and the path, and obtaining a test space related to the sensitive target and the path; variation is carried out on request processing information, parameter information and control information in the test space, and the test case is guided to be executed to a sensitive target; and performing collapse variation on the sensitive function parameters in the test space, triggering the firmware vulnerability of the to-be-detected equipment in the execution process of the test case, and generating a test result. According to the method, the blindness of fuzzy testing is reduced, and the method has good adaptability to firmware analysis of embedded equipment.

An analysis function providing method executed by an analysis function providing device includes first analyzing a virtual machine of a script engine, and acquiring a hook point that is a part where an analysis code is inserted by applying a hook, and a virtual program counter that is a variable indicating an instruction of the virtual machine to be executed next, second analyzing an instruction set architecture that is a system of instructions of the virtual machine and acquiring a branch virtual machine instruction that is a virtual machine instruction that causes branch, and providing an analysis function by applying a hook, to the hook point of the script engine, the hook including processing of, when an exception has occurred, changing a destination pointed by the virtual program counter to a head of a basic block immediately after a basic block in which the exception has occurred.

The invention discloses an intelligent contract vulnerability detection method based on a multi-level data dependence heterogeneous graph, and belongs to the technical field of intelligent contract security. Intelligent contract byte codes are used as input, contract byte codes are converted into operation codes, and a control-data heterogeneous graph with basic blocks as nodes is constructed; designing an in-block data dependency sub-graph, and forming multi-level data dependency with the inter-block data stream; based on the generated control-data heterogeneous graph, a feature weighted relation graph convolutional network is provided, and control flow and data flow feature weights are dynamically adjusted and optimized by using node static attributes such as dominating tree depth and the like, so that multi-modal semantic efficient aggregation is realized. According to the method, for the contract without a public source code on the block chain, vulnerability detection only for the bytecode of the intelligent contract is realized, and high detection efficiency can be achieved under the condition that the detection accuracy is guaranteed.

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: when a direct jump instruction in a first basic block is translated, identifying whether a second basic block to which the direct jump instruction is to jump crosses pages or not; if it is determined that the second basic block crosses pages, a target instruction sequence is inserted in front of an unoptimized instruction sequence translated by the direct jump instruction, the target instruction sequence is used for detecting whether the direct jump instruction meets an optimization condition or not, and jumping is conducted through the link instruction sequence under the condition that the direct jump instruction is detected to meet the optimization condition; the optimization condition comprises that the virtual and real address mapping relation of the second basic block is not changed; the link instruction sequence is used for skipping to an initial address of the translated basic block corresponding to the second basic block in the code cache. According to the embodiment of the invention, the execution of the direct jump instruction is optimized under the condition that the optimization condition is satisfied, so that the program running efficiency can be improved.

The invention discloses a code embedding method based on a semantic embedding vector generation model, which belongs to the technical field of computers, and comprises the following steps of: obtaining a binary code block, and performing disassembling processing and code structure analysis based on different granularities to obtain a basic block corresponding to the binary code block and a control flow diagram structure feature; performing assembly instruction linear conversion and cross-instruction-set semantic embedding conversion on the basis of the basic blocks corresponding to the binary code blocks and the structural features of the control flow graph to generate a unified binary code semantic embedding vector space corresponding to a cross-instruction-set architecture; obtaining a known vulnerability sample, and performing semantic vulnerability characterization analysis and candidate vulnerability retrieval positioning to generate a candidate vulnerability code block set; and carrying out dynamic analysis verification on the candidate vulnerability code block set and identifying a corresponding vulnerability repair state so as to output a corresponding binary vulnerability code block detection report. According to the method, high-precision semantic embedding of binary codes can be realized.

The invention discloses a performance optimization method and device of a graphics processor, electronic equipment and a storage medium, and relates to the technical field of computers, the performance optimization method comprises the steps that basic block execution data of a target program can be dynamically collected based on instrumentation logic compiled by a static library, and performance bottlenecks are accurately positioned by analyzing the data; meanwhile, the control flow and resource allocation are optimized in combination with the characteristics of the graphic processor micro-system structure, so that the technical problems of low efficiency of the control flow, resource imbalance, low memory access efficiency and the like of the graphic processor micro-system structure level can be solved; the technical effects of improving the calculation efficiency of the graphics processor, optimizing the resource utilization rate, reducing the energy consumption and improving the overall performance of the program are achieved.

The present invention provides an operating system kernel fuzz testing method, device and equipment, which relate to the field of kernel fuzz testing technology. By obtaining the initial input and splitting the initial input to generate an input set; performing fuzz testing on the input set and obtaining the fuzz testing results; storing the fuzz testing results in a key component inference file to generate a key component inference table; generating a seed selection strategy in the seed library in combination with the key component inference table to guide seed mutation selection. By identifying and utilizing the key components in the system call sequence, the coverage of the fuzz test is improved. A correspondence between the key components in the system call sequence and the corresponding path basic blocks is established to better explore potential security vulnerabilities. According to the selection of mutation points, different mutation strategies are executed to effectively improve the existing fuzz testing method and improve the efficiency and quality of vulnerability mining.

The invention discloses a remote sensing image target detection method based on improved RT-DETR and computer equipment, and relates to the field of deep learning and target detection, and the method comprises the steps: inputting a to-be-detected remote sensing image into an optimal remote sensing image target detection model, and obtaining a recognition result of the remote sensing image; the remote sensing image target detection model comprises an improved backbone network, an improved neck network and a head network; wherein the improved backbone network is a network which is obtained by replacing a Basic Block module with a Faster Block module in a backbone network of the RT-DETR network model; the improved neck network is a network obtained by integrating an MFEP-OK module and a CGAFusion module on the basis of a neck network of an RT-DETR network model. According to the method, the detection speed is ensured, and the detection accuracy of small targets and long-tail targets in a remote sensing image target detection model is improved.

The embodiment of the invention relates to an instruction execution method and device, a processor and a related product, an MIMD framework is adopted in a GPU, a first SIMT stack and a second SIMT stack are configured for managing execution information of different branch basic blocks in the same thread bundle, and on the basis, the execution information of the different branch basic blocks in the same thread bundle can be managed through the first SIMT stack and the second SIMT stack. According to the method, the state of at least one of a first SIMT stack and a second SIMT stack is updated according to a basic block to be executed, and under the condition that the updated first SIMT stack and the updated second SIMT stack are both non-empty, instructions in all branch basic blocks are taken out respectively according to execution information of the first SIMT stack and execution information of the second SIMT stack and transmitted to an MIMD for concurrent execution. According to the method, when the execution channels of the MIMD concurrently execute the branch instructions, the resource utilization rate of the ALU can be improved, and therefore the running performance of a GPU program is improved.

The invention provides a concurrent vulnerability fuzzy test method and device supporting reproduction, and relates to the technical field of computers, the method comprises the following steps: obtaining a target program obtained by rewriting an original binary program; wherein the target program comprises a plurality of key basic blocks, and the execution sequence of the key basic blocks is used as a thread interleaving feedback signal; performing thread staggering variation based on the key basic block to generate a plurality of target test cases containing a plurality of thread staggering conditions; performing a fuzzy test based on the plurality of target test cases, and reproducing a crash scene based on execution information of the target program under the condition that the target program is triggered to crash in the fuzzy test process; wherein the execution information is obtained by recording the execution sequence of the key basic blocks in the execution process of the target program. Through the method provided by the invention, concurrent vulnerabilities can be effectively mined, and recurrent fuzz testing can be carried out.

The invention relates to the field of code vulnerability detection, in particular to a binary vulnerability retrieval and positioning method and system based on high-dimensional vulnerability characterization, and the method comprises the steps: firstly inputting a binary file, analyzing the structural information of the binary file, and analyzing a machine instruction; extracting binary file function information, generating a cross-platform basic block IR instruction sequence, constructing a control flow graph, and constructing a data dependency graph; splicing the program dependency graph feature vector and the basic block IR instruction sequence feature vector, and performing multi-modal feature fusion to generate a comprehensive high-dimensional vulnerability representation vector; and finally, inputting the high-dimensional vulnerability representation vector into an index for searching to obtain a plurality of nearest neighbor indexes and distances, converting the distances into similarity, filtering according to a similarity threshold to obtain a most similar vulnerability vector, and obtaining vulnerability information and vulnerability positions corresponding to the vulnerability vector. The problems that traditional binary vulnerability detection cross-platform and compiler optimization detection fails and the result reliability is low are solved.

The invention relates to the technical field of software security, and discloses an IDA microcode-based digital multimeter customized code obfuscator construction method and system, and the method comprises the steps: carrying out the obfuscation replacement of a measurement algorithm and a data processing method in a digital multimeter code based on an instruction replacement technology; confusing a control flow of the digital multimeter based on a false control flow technology, namely obtaining a calling relation of basic blocks to reconstruct an original program, and avoiding generation of an endless loop in a symbolic execution process through a method of assigning a value to an opaque predicate in advance; randomly modifying variable names, identifiers and function names of the sensitive data information of the digital multimeter based on a variable name confusion algorithm; and carrying out decompilation and code conversion on the obfuscation algorithm based on the IDA microcode, and constructing the digital multimeter customized code obfuscator based on the IDA microcode. The method can be integrated into the development environment of the digital multimeter, the safety protection level of the digital multimeter is improved, and the measurement data is prevented from being illegally stolen.

The invention discloses a cross-platform binary code block hierarchical semantic similarity detection method and a related device, and belongs to the field of code vulnerability detection.The cross-platform binary code block hierarchical semantic similarity detection method comprises the following steps that structural information of a binary file is analyzed, a machine instruction is analyzed through a hybrid disassembling engine, a basic block is extracted from the structural information of the binary file, and the basic block is extracted from the binary file; constructing a control flow graph, a data dependency graph and a function call graph; extracting instruction level semantics, basic block level semantics and function level semantics from the instruction sequence, the basic block, the control flow graph, the data dependency graph and the function call graph; according to the instruction-level semantics, the basic-block-level semantics and the function-level semantics, constructing instruction-level features, basic-block-level features and function-level features; and carrying out hierarchical similarity detection on the instruction-level features, the basic block-level features and the function-level features. The method and the related device can solve the problems of low detection efficiency and poor accuracy when a traditional vulnerability detection method is used for detecting vulnerabilities.

The invention provides a fine-grained binary code similarity detection method based on code retrieval and subgraph matching, and belongs to the technical field of network security. The method comprises the following steps of: performing vectorization embedding on a binary code to be tested at a basic block level on the basis of code snippet-level fine-grained retrieval; and retrieving the embedded vector at the basic block level in an existing binary code database, thereby performing binary code matching at the basic block level. According to the method, each matched basic block is expanded to an adjacent basic block to form a sub-graph, and the matched basic blocks are used as seed nodes; and performing seed graph matching on the plurality of discontinuous sub-graphs, and judging the similarity between the binary code to be detected and the code in the binary code database, thereby completing the similarity detection of the fine-grained binary code. According to the method, the problems of low accuracy and weak generalization ability of a detection scene of traditional binary code similarity detection in complex detection scenes such as function inline and multiplexing after code modification are solved.

The invention discloses a data prefetching method and device, and relates to the technical field of computers. The data prefetching method comprises the steps that a control flow diagram and events, recorded by a PMU, of basic blocks in the control flow diagram are obtained, target paths of multiple paths in the control flow diagram are determined according to the occurrence frequency of the events of the basic blocks in the control flow diagram, and then target data corresponding to a first basic block are written into a buffer before the first basic block is executed. Wherein the sum of the occurrence frequency of all events of the basic block in the target path is greater than or equal to a first threshold value, and the target data is data with the access frequency or the access frequency greater than or equal to a second threshold value in the data needing to be accessed when the target path is executed. The sum of the occurrence times corresponding to the target path is greater than or equal to the first threshold value, so that the probability that the target path is frequently executed is relatively high, the target data determined according to the target path is written into the cache in advance, and the data access efficiency when the processor executes according to the control flow diagram can be improved.

The invention relates to the field of code vulnerability detection, in particular to a vulnerability detection method and system based on code block features. The method comprises the steps that firstly, a binary file is analyzed, and a machine instruction is analyzed through a hybrid disassembling engine; secondly, performing static linear scanning on the extracted binary file instruction, constructing a control flow graph, dividing basic blocks, extracting an operation code sequence in the basic blocks, and constructing a cross-basic-block data dependency graph and a system calling sequence called by the basic blocks; secondly, using an LSH algorithm to realize rapid filtering, performing similarity comparison on extracted basic block features and vulnerability feature library features, realizing coarse-grained matching, and screening out a matching candidate set; feature fusion is carried out on the candidate set basic block operation code sequence, the basic block data dependency graph and the system calling sequence called by the basic block, GNN fine-grained matching is carried out on the fused features, and vulnerability detection is carried out. The problems that traditional binary vulnerability detection is poor in adaptability and low in result reliability are solved.

The invention discloses a sparse attention operator acceleration method based on an NPU, and the method comprises the steps: combining a Linformer with an Ascend C programming language, and achieving an Ascend C operator for calculating the Linformer based on the NPU; according to the method, an accelerated calculation mode of combining Linformer with Flash-Attention2 is adopted, so that the whole operator can be subjected to calculation in a blocking manner; according to hardware characteristics of the mercuric chloride NPU, optimization of vector calculation is carried out, the number of instructions used by multiple vector calculations such as vector subtraction, line-by-line summation and line-by-line max calculation for calculating safety softmax is reduced, and time consumption is reduced; aiming at the problem that front and back data cannot be parallel due to more dependence, the calculation efficiency of a sparse approximate attention operator is improved by using an algorithm for constructing parallel calculation by emitting Cube in advance; basic block segmentation is carried out on matrix multiplication, and the carrying time of matrix multiplication is shortened.

A simulation method for simulating a target circuit design comprising a plurality of micro-architecture hyper-parameters. The method comprises decompiling a binary code to obtain a control flow graph comprising multiple basic blocks (101, 120); generating multiple basic block chains, BBCs, based on the plurality of basic blocks taking account of the micro-architecture hyper-parameters (102, 130); performing, for each BBC, cycle-accurate simulation (104, 150) based on the determined context (103, 140), to obtain cycle count information (150); storing the cycle count information into a database (105, 160); performing instruction-accurate simulation (106) using the binary code, to obtain instruction traces indicating executed BBC; retrieving, for each executed BBC, corresponding cycle count information from the database (107); and determining overall cycle count information of the binary code on the target circuit design by accumulating the retrieved cycle count information of the executed BBCs (108). In this way, a fast and accurate simulation can be achieved.

In various examples, static single assignment-based control flow graph traversal analysis for uninitialized variable detection system and methods are disclosed. A pre-compiler stage of a compiler system, may reconstruct source code into an SSA form IR and detect and identify uninitialized variables based on applying a variable analysis pass that traverses a CFG corresponding to the SSA form IR. A variable analysis pass may traverse through the CFG to build a defined variable map and a Phi variable map. The maps may be used to map undefined variables to basic blocks of the CFG where the undefined variables occur. The variable analysis pass may pass uninitialized variable data to a compiler error handling process. The compiler error handling process may produce an error report that traces the basic block with undefined variables to lines of the source code to assist in efficiently debugging the source code.

The invention discloses a code intermediate representation pre-training method based on semantic similarity, which is characterized in that the semantic similarity of basic blocks is formally defined, a set of basic block semantic similarity learning pipeline is designed, and semantic supervision signals can be locally provided for the basic blocks represented in the code intermediate. According to the method, the equivalence relation of input variables is assumed, a program verifier is used for verifying the equivalence relation of output variables, and the proportion of the equivalence output variables is defined as the semantic similarity of basic blocks. The basic block semantic similarity learning pipeline comprises five steps of extracting basic blocks from code intermediate representation, semantically translating basic block instructions into an intermediate verification language, sampling basic block pairs of which the similarity is to be calculated, calling a program verifier in parallel to calculate the similarity, and carrying out similarity regression learning based on mean square error loss.

The invention provides an image processing method and device, electronic equipment, a storage medium and a program product, and belongs to the technical field of deep learning, and the method comprises the steps: determining a partitioning parameter based on a hardware parameter and a convolution operation parameter of a tensor kernel; performing blocking processing on a feature map corresponding to the to-be-processed image based on the blocking parameters to obtain a plurality of basic blocks; obtaining a plurality of three-dimensional tensors corresponding to the plurality of basic blocks; converting the plurality of three-dimensional tensors into a plurality of first matrix blocks adaptive to a tensor kernel based on the total element number of the three-dimensional tensors corresponding to the basic blocks; respectively inputting the plurality of first matrix blocks into a tensor kernel to obtain a plurality of second matrix blocks output by the tensor kernel; and reconstructing the plurality of second matrix blocks according to the output size of the feature map to obtain an output feature map. Through adaptive adjustment of the partitioning strategy, the waste of calculation power is reduced, and the parallel calculation capability of the tensor kernel is brought into full play, so that the calculation delay in the training and reasoning process of the convolutional neural network is reduced, and the overall operation efficiency is improved.