The invention provides a stacked packaging structure corresponding to
wafer back power supply of chips of 2nm and below, and high-efficiency and low-loss power supply is realized through accurate correspondence of
wafer back power supply
metal contacts on a carrier plate and
chip back
metal contacts in combination with a conductive network constructed by vertical and transverse
metal blocks. According to the structure, a
signal transmission path is optimized,
signal delay and loss are remarkably reduced, and the working efficiency and performance of the
chip are improved. The stacking design makes full use of a three-dimensional space, the carrier plate, the substrate, the adapter plate and the
chip are closely integrated, and the
utilization rate of the packaging space is greatly improved. The conductive network and the
solder ball connection enhance the packaging
mechanical strength, and improve the vibration and
impact resistance. And the vertical metal blocks have conductive and supporting functions, so that the
structural stability is enhanced. The packaging size of the first chips in flip connection is reduced, the density is improved, and the pinboard provides a heightening effect, so that subsequent connection is facilitated. The chip packaging efficiency, performance and stability are comprehensively improved, and the method is suitable for the field of high-end chip packaging.