183 results about "Metallic interconnect" patented technology

A method of selectively depositing a capping layer structure on a semiconductor device structure is disclosure. The method may include; providing a partially fabricated semiconductor device structure comprising a surface including a metallic interconnect material, a metallic barrier material, and a dielectric material. The method may also include; selectively depositing a first metallic capping layer over the metallic barrier material and over the metallic interconnect material relative to the dielectric material; and selectively depositing a second metallic capping layer over the first metallic capping layer relative to the dielectric material. Semiconductor device structures including a capping layer structure are also disclosed.

A capped chip is provided which includes a chip and a cap member, the chip having a front surface and a plurality of bond pads exposed at the front surface, the cap member having a bottom surface facing the front surface of the chip and having a top surface opposite the front surface. A plurality of through holes extend from the bottom surface of the cap member to the top surface. The capped chip assembly further includes a plurality of metallic interconnects extending from the bond pads at least partially through the through holes, the metallic interconnects including stud bumps joined to the bond pads, the stud bumps contacting and engaging at least one of (i) the top surface of the cap member surrounding the through holes and (ii) inner surfaces of the through holes.

Cleaning compositions and processes for cleaning post-plasma etch residue from a microelectronic device having said residue thereon. The composition achieves highly efficacious cleaning of the residue material, including titanium-containing, copper-containing, tungsten-containing, and/or cobalt-containing post-etch residue from the microelectronic device while simultaneously not damaging the interlevel dielectric, metal interconnect material, and/or capping layers also present thereon.

One embodiment of the present invention in a method for making copper interconnects, which method includes: (a) forming a patterned insulating layer on a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least one opening; (b) depositing a barrier layer over the field and inside surfaces of the at least one opening; (c) depositing a non-conformal first copper seed layer over the barrier layer using physical vapor deposition, wherein the first seed layer is thicker than about 500 Å over the field; (d) depositing a conformal second copper seed layer over the first seed layer using chemical vapor deposition; and (e) electroplating a copper layer over the second seed layer.

A solid oxide fuel cell (SOFC) repeat unit includes an oxide electrolyte, an anode, a metallic fuel flow field, a metallic interconnect, and a metallic air flow field. The multilayer laminate is made by casting tapes of the different functional layers, laminating the tapes together and sintering the laminate in a reducing atmosphere. Solid oxide fuel cell stacks are made by applying a cathode layer, bonding the unit into a gas manifold plate, and then stacking the cells together. This process leads to superior mechanical properties in the SOFC due to the toughness of the supporting metallic layers. It also reduces contact resistances in stacking the cells since there is only one physical contact plane for each repeat unit.

A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 mu m. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 mu m<G</=100 mu m. A metallic interconnect is provided over the top faces and the gap. Preferably, the interconnect has a gradual slope over the gap.

An electrically conductive metallic interconnect in a trench or via in a dielectric is provided by depositing a first liner layer on the walls and bottom of the trench or via; removing residual contamination from the bottom of the trench or via; depositing a second liner layer in the trench; depositing a seed layer and filling the trench with electrically conductive metallic material.

Electrode materials systems for planar solid oxide fuel cells with high electrochemical performance including anode materials that provide exceptional long-term durability when used in reducing gases and cathode materials that provide exceptional long-term durability when used in oxygen-containing gases. The cathode materials comprise zinc-doped lanthanum strontium ferrite (LSZF) or an alternative ferrite, cobaltite or nickelate ceramic electrode material. The cathode material also may comprise a mixed-conducting ceria-based electrolyte material, a palladium dopant, or a combination of these. The cathode may have a bi-layer structure. A ceramic-based interfacial layer may be provided at the electrolyte/cathode interface. The multilayer cathode system and its palladium doped cathode material exhibit a high degree of tolerance to chromium contamination during operation with metallic interconnect materials.

A composition and method for removing copper-containing post-etch and/or post-ash residue from patterned microelectronic devices is described. The removal composition includes water, a water-miscible organic solvent, an amine compound, an organic acid, and a fluoride ion source. The compositions effectively remove the copper-containing post-etch residue from the microelectronic device without damaging exposed low-k dielectric and metal interconnect materials.

There is provided a method for forming a metal interlayer via, comprising: forming a seed layer on a first dielectric layer and a first metal layer embedded in the first dielectric layer; forming a mask pattern on the seed layer to expose a portion of the seed layer covering some of the first metal layer; growing a second metal layer on the exposed portion of the seed layer; removing the mask pattern and a portion of the seed layer carrying the mask pattern to expose side walls of the second metal layer, a portion of the first metal layer and the first dielectric layer; forming an insulating barrier layer on the side walls, the portion of the first metal layer and the first dielectric layer. There is also provided a method for forming a metal interconnection line. Both of them can suppress the occurrence of voids. There is further provided a metal interconnection structure comprising a contact plug, a via and a metal interconnection line, wherein the via is formed on the metal interconnection line, the metal gate and/or the contact plug.

The present invention provides a method of producing a multilayer barrier structure in a solid oxide cell stack, comprising the steps of: -providing a metal interconnect; -applying a first metal oxide layer on said metal interconnect; -applying a second metal oxide layer on top of said first metal oxide layer; -applying a third metal oxide layer on top of said second metal oxide layer; -forming a solid oxide cell stack comprising said metal interconnect having said metal oxide layers thereon; and -reacting the metal oxide in said first metal oxide layer with the metal of said metal interconnect during the SOC-stack initialisation, and a solid oxide stack comprising an anode contact layer and support structure, an anode layer, an electrolyte layer, a cathode layer, a cathode contact layer, a metallic interconnect, and a multilayer barrier structure which is obtainable by the above method and through an initialisation step, which is carried out under controlled conditions for atmosphere composition and current load, which depends on the layer composition facilitating the formation of the desired reaction products as a dense barrier layer without chromium species migrating to the air-electrode.

The present invention relates to a polishing pad which is characterized in that it is of micro rubber A-type hardness at least 80°, has closed cells of average cell diameter no more than 1000 mum, is of density in the range 0.4 to 1.1 and contains polyurethane and polymer produced from a vinyl compound. When planarizing local unevenness on a semiconductor substrate with the polishing pad relating to the present invention, the polishing rate is high, the global step height is low, dishing does not readily occur at the metallic interconnects, clogging and permanent set of the surface layer region do not readily occur and the polishing rate is stable.

One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing of one or more seed layers, which method includes steps of: (a) depositing a substantially conformal seed layer over the field and inside surfaces of the at least one opening; (b) depositing a substantially non-conformal seed layer over the substantially conformal seed layer, said substantially non-conformal seed layer being thicker than said substantially conformal seed layer over the field, wherein the substantially conformal and the substantially non-conformal seed layers do not seal the at least one opening; and (c) electroplating a metallic layer over the substantially non-conformal seed layer, wherein the electroplated metallic layer comprises a material selected from a group consisting of Cu, Ag, or alloys comprising one or more of these metals.

Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

Process for contact-connection of carbon nanotubes as part of their integration in an electric circuit, wherein the nanotubes, after they have been applied to metallic interconnects of the electric circuit, are connected to the interconnects at contact locations by electroless metallization.

The invention discloses a silicon through-hole test structure which comprises a semi-conductor substrate, a silicon through hole, insulation layers, conducting materials, a heavily doped area, a dielectric layer and metal interconnection layers, wherein the silicon through hole is located inside the semi-conductor substrate, the insulation layers are located on the side wall and the bottom surface of the silicon through hole, the conducting materials are filled into the silicon through hole and located on the surfaces of the insulation layers, the heavily doped area is arranged to surround the silicon through hole and located inside the semi-conductor substrate, the dielectric layer is located on the surface of the semi-conductor substrate, and the metal interconnection layers are located on the surface of the dielectric layer. The conducting materials in the silicon through hole is in electricity connection with a first metal interconnection layer, and the heavily doped area is in electricity connection with a second metal interconnection layer, and the conducting materials in the silicon through hole is in electricity isolation with the heavily doped area. When polarization voltages are applied across the conducting materials of the silicon through hole and the heavily doped area, and then whether the insulation layers are judged complete or not through that whether leakage currents are measured between the conducting materials and the heavily doped area or not, and the depth of the silicon through hole is judged to reach a standard value or not through a measured capacitance value between the conducting materials and the heavily doped area, and the test process is simple and convenient.

Embodiments of the present invention generally relate to a method and apparatus for planarizing a substrate by electropolishing techniques. Certain embodiments of an electropolishing apparatus include a contact ring adapted to support a substrate, a cell body adapted to hold an electropolishing solution, a fluid supply system adapted to provide the electropolishing solution to the cell body, a cathode disposed within the cell body, a power supply system in electrical communication with the contact ring and the cathode, and a controller coupled to at least the fluid supply system and the power supply system. The controller may be adapted to provide a first set of electropolishing conditions to form a boundary layer between the substrate and the electropolishing solution to an initial thickness and may be adapted to provide a second set of electropolishing conditions to control the boundary layer to a subsequent thickness less than or equal to the initial thickness.

The present invention provides a diffusion barrier useful in an integrated circuit, which serves to prevent the migration of material from a conductive layer to the underlying substrate and further provides improved adhesion of the conductive layer to the substrate. The diffusion barrier comprises a polymer which is a polyelectrolyte, having both cationic and anionic groups along its backbone chain. Preferred polyelectolyte barriers are polyethyleneimine (PEI) and polyacrylic acid (PAA). Other polyelectrolytes may be used, such as those that contain SH— OH— aromatic groups, or those that can interact with either the metal or the adjacent layers via covalent interactions and cross-linking (e.g., POMA, PSMA). The polymeric layer may be applied in two coatings, so that the amine side chains contact the dielectric (e.g. silicon) substrate and the acidic groups are adjacent to the overlying metallic interconnect (e.g. copper). The diffusion barrier may be made thin, preferably less than 5 nm thick, which is advantageous in devices having high aspect ratios.

The invention provides an image sensor and a preparation method thereof. The method comprises the steps that a photosensitive element array and a metal interconnection layer on the photosensitive element array are formed on a substrate; the substrate is flipped over, and an isolation trench is formed between adjacent photosensitive elements; a curved mirror is formed on each photosensitive elementto increase the light absorption efficiency of each photosensitive element; each isolation trench is filled to form an isolation structure; and a dielectric layer, a color filter array and a micro lens array are sequentially formed on the isolation structures and the curved mirrors. According to the image sensor and the preparation method thereof, a back-illuminated image sensor structure is used; the curved mirrors and micro-lenses are arranged on the light-receiving surfaces and the light incident surfaces of the photosensitive elements to converge the incident light onto the photosensitiveelements; the light absorption efficiency of the photosensitive elements in the image sensor is improved; the photoelectric conversion efficiency, the random noise and the signal-to-noise ratio of the image sensor are improved; and finally the imaging quality of the image sensor is improved.