42 results about "Metallic interconnect" patented technology

A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.

The present application provides a bottom layer metal interconnection line structure, at least including a test key and leads connected to the test key; the test key being composed of a plurality of metal lines connected end-to-end; the plurality of metal lines being arranged in the same plane in a winding manner, wherein at least one suspending via structure is provided at each winding point; and two leads are provided and respectively connected to ends of the metal lines located at a head end and a tail end in the test key. The present application increases a maximum root-mean-square current that the winding metal interconnection lines can withstand while improving a heat dissipation problem of the bottom layer metal interconnection lines.

The present invention relates to a metal interconnect structure containing no barrier metal and a method of manufacturing the metal interconnect structure. The method includes: filling at least a first interconnect trench with an intermetallic compound by depositing the intermetallic compound on an insulating layer having the first interconnect trench and a second interconnect trench formed in the insulating layer, the second interconnect trench being wider than the first interconnect trench; performing a planarization process of polishing the intermetallic compound until the insulating layer is exposed; and then performing a height adjustment process of polishing the intermetallic compound and the insulating layer until a height of the intermetallic compound in the first interconnect trench reaches a predetermined height.

Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one

This invention relates to the field of semiconductor power device technology, specifically to a GaN HEMT structure with an air cavity and its fabrication method. The structure includes a substrate, an epitaxial layer, a source, a drain, a gate, a composite passivation layer, and an air cavity. The composite passivation layer includes a bottom SiO2 sacrificial layer and a top SiN passivation layer. The SiO2 sacrificial layer between the gate and the source, and between the gate and the drain, is completely removed to form a global air cavity. The fabrication method involves epitaxial fabrication, active region isolation, source-drain-gate fabrication, composite passivation layer deposition, metal interconnect via etching, and wet etching of the sacrificial layer to form the air cavity, ultimately completing the metal interconnect. This invention simultaneously solves the dual technical problems of excessive parasitic capacitance and excessively long heat dissipation path caused by traditional passivation layers, significantly improving the high-frequency characteristics, thermal stability, and operational reliability of GaN HEMT devices. Moreover, the fabrication process is fully compatible with conventional GaN HEMT processes, requiring no special gate structure design, and is easy to industrialize and promote.

The utility model provides a pHEMT device. The pHEMT device comprises a substrate and a metal interconnection structure formed on the substrate. The metal interconnection structure comprises an ohmic contact layer, a first metal coating and a second metal coating which are sequentially stacked from bottom to top, the first metal coating comprises a first adhesion layer, a first metal structure layer, a second metal structure layer and a second adhesion layer which are sequentially stacked from bottom to top, the resistance value of the first metal structure layer is smaller than that of the second metal structure layer, and the hardness of the second metal structure layer is larger than that of the first metal structure layer. In the first metal coating, the second metal structure layer with higher hardness is formed to improve the surface roughness caused by the subsequent etching process and prevent the first metal structure layer from diffusing to the second adhesion layer to form aggregation points on the surface of the first metal coating. Therefore, the possibility that electroplating piebaldness is generated when the second metal coating is electroplated on the first metal coating can be reduced.

The invention provides a WAT test structure and a test method, the WAT test structure comprises a first test structure and a second test structure, and a first metal interconnection structure in the first test structure is electrically connected with a first control gate; the second metal interconnection structure in the second test structure is disconnected with the second control gate, and the structure of the second control gate is the same as that of the first control gate. In the test method, whether the failure occurs in the control gate or the metal interconnection structure can be effectively judged according to the leakage current of the first test structure and the leakage current of the second test structure.

The invention relates to the technical field of hybrid bonding, and discloses a preparation method of a hybrid bonding structure and the hybrid bonding structure.The method comprises the steps that a first wafer and a second wafer are provided, and a plurality of bonding pads and insulating layers covering the bonding pads are arranged on the wafers at intervals; depositing aluminum nitride on the insulating layer of the first wafer to form a first heat dissipation layer, and depositing aluminum nitride on the insulating layer of the second wafer to form a second heat dissipation layer; forming a plurality of first openings in the first heat dissipation layer, and forming a plurality of second openings in the second heat dissipation layer; forming a first metal interconnection structure in the plurality of first openings, and forming a second metal interconnection structure in the plurality of second openings; and carrying out bonding processing on one side, far away from the insulating layer of the first wafer, of the first heat dissipation layer and one side, far away from the insulating layer of the second wafer, of the second heat dissipation layer to obtain a hybrid bonding structure. According to the invention, the heat dissipation efficiency can be greatly improved, and heat generated by devices in the wafer can be timely dissipated.

An atmospheric pressure plasma apparatus and method are disclosed that operate with a multigas mixture to provide a high concentration of reactive neutral species for cleaning and activating the surfaces of substrates, including those with metal interconnects embedded in the substrate.

The invention provides the cleaning composition, the corrosion composition, the kit, the corrosion process and the device, the problem that the corrosion selectivity of AlN relative to AlOx is relatively low is solved, and metal materials such as copper and high-quality cobalt in a metal interconnection circuit are not damaged when a hard mask is removed; the cleaning composition comprises a metal protective agent and a nitrogen-containing heterocyclic compound, the nitrogen-containing heterocyclic compound is selected from at least one of nitrogen-containing heterocyclic compounds and nitrogen-containing heterocyclic compounds; the definition of each group is described in the specification.

The invention relates to a metal surface alloying treatment method, a metal interconnection layer side wall alloying treatment method, a metal interconnection layer and a display panel. The treatment method comprises the following steps: preparing an acidic electrolyte containing first metal ions, and carrying out electrolytic treatment on the electrolyte by taking second metal as a cathode; in the electrolytic treatment process, an inhibitor is added into the electrolyte; wherein the inhibitor comprises a thiocarboxylic acid material, and the reducibility of the second metal is higher than that of hydrogen. First metal ions are firstly deposited to form loose first metal; and a small amount of ions are also dissolved out from the second metal and are continuously subjected to atomic-level co-deposition with the ions of the first metal under the electrolysis action, a uniform alloy layer is formed, and alloying treatment of the surface of the second metal is achieved. The added inhibitor is gradually decomposed, the dielectric constant of the electrolyte is gradually reduced, and the codeposition reaction is automatically terminated when the dielectric constant is reduced to a certain value. Therefore, the method does not need high-temperature treatment, and the alloying treatment effect is controllable and stable.

This invention discloses an etching method for a back-illuminated image sensor and a back-illuminated image sensor. The etching method includes: providing a substrate, wherein an epitaxial layer with a hermetically sealed cavity and a metal interconnect layer are sequentially formed on the front side of the substrate; etching from the back side of the substrate using an etching process to open the hermetically sealed cavity along a direction perpendicular to the substrate surface and extend the bottom of the cavity downward; the etching process includes alternating etching and deposition steps; by controlling the ratio of the processing time of the etching step to the processing time of the deposition step to 0.75:1 to 1.5:1; and the flow rate ratio of the etching gas used in the etching step to the deposition gas used in the deposition step to 1:1.3 to 1:0.7, a continuously accumulated protective layer is formed at the bottom of the cavity. When the protective layer reaches a predetermined thickness or reduces the local etching rate to a preset threshold, further material etching is inhibited or prevented, so that the etching automatically stops at the required depth, and the extended bottom of the cavity is higher than the top of the metal interconnect layer.

A bonded assembly includes a first memory die including a first alternating stack of first insulating layers and first electrically conductive layers, first memory stack structures vertically extending through the first alternating stack, first metal interconnect structures embedded within first memory-die inorganic dielectric layers, and first memory-die copper bonding pads embedded within a first polymer dielectric layer, and a second memory die including a second alternating stack of second insulating layers and second electrically conductive layers, second memory stack structures vertically extending through the second alternating stack, second metal interconnect structures embedded within second memory-die inorganic dielectric layers, and second memory-die copper bonding pads embedded within a second polymer dielectric layer.

The invention relates to a metal interconnection layer and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; the dielectric laminations and the initial metal wires are alternately arranged on the substrate along a first direction parallel to the first surface; the side wall of the initial metal wire comprises a protruding part, and the protruding part is embedded in the dielectric lamination layer along the first direction; etching the dielectric laminated layer, forming a groove between the adjacent initial metal wires, and then forming a liner oxide layer covering the inner surface of the groove and the top surfaces of the initial metal wires; the bottom face of the groove is lower than the bottom face of the protruding part. Performing a surface treatment process on the exposed surface of the liner oxide layer, and at least adding a target dangling bond for increasing the coating rate on the inner surface of the groove not lower than the convex part; after an oxide layer is formed in the groove, removing the rest of the film layer with the top surface higher than the top surface of the protruding part to obtain a target metal wire; an air gap structure is arranged in the oxide layer. The technological process of the air gap structure in the metal interconnection layer can be simplified.

The invention provides a metal interconnection structure and a forming method thereof. An adhesion promoting layer in the metal interconnection structure is only located on the side wall of a groove; the adhesion promoting layer adsorbs a precursor of the first diffusion barrier layer, so that the first diffusion barrier layer is only formed on the side wall of the groove and is used for blocking metal diffusion, and metal filling is prevented from being affected by deposition of the first diffusion barrier layer at the bottom of the groove; the second diffusion barrier layer covers the first diffusion barrier layer, is used for blocking metal diffusion, and is used for supporting the first diffusion barrier layer and inhibiting the first diffusion barrier layer from cracking. The adhesion promoting layer is adopted to reduce the thickness requirement of a traditional metal barrier layer and improve the wettability of metal at the same time, the second diffusion barrier layer is made of high-entropy nitride or high-entropy alloy and plays a main role in blocking metal diffusion, the total thickness of the first diffusion barrier layer and the second diffusion barrier layer is reduced, and the process requirement of 40 nm nodes or below is met; lattice matching of the first diffusion barrier layer reduces interface stress, and metal filling defects are avoided.

The present invention relates to a solid oxide cell (SOC) stack made of single repeating units (SRU), each of which comprising: —a ceramic cell with a corrugated membrane and a sealing frame with gas distribution holes and channels, and—a flat metallic interconnect.

The problem of connecting a TSV to a BEOL metal interconnect structure without damaging the BEOL metal interconnect structure is solved by landing the TSV on a metal coupling structure formed during FEOL processing. The metal coupling structure is produced in accordance with design rules that apply to FEOL processing. The metal coupling structure may include substructures that have the composition and shape of wires in a transistor level metal interconnect and substructures that have the composition and shape of metal gate strips. The metal coupling structure may include pluralities of the substructures arrayed across the TSV landing area. The substructures that make up the metal coupling structure are connected to the BEOL metal interconnect through vias.

The invention discloses a cross-photoetching-field copper interconnection process mask plate structure. A light-transmitting area of a left side cross-photoetching-field splicing area mask plate and a light-transmitting area of a right side cross-photoetching-field splicing area mask plate are not intersected; the light-transmitting area of the mask template crossing the photoetching field splicing area on the upper side and the light-transmitting area of the mask template crossing the photoetching field splicing area on the lower side are not intersected; the union set of the light-transmitting area of the mask template crossing the photoetching field splicing area on the left side and the light-transmitting area of the mask template crossing the photoetching field splicing area on the right side is a target shape of the photoetching field-crossing copper interconnection wire; and the union set of the light-transmitting area of the mask template crossing the photoetching field splicing area on the upper side and the light-transmitting area of the mask template crossing the photoetching field splicing area on the lower side is a target shape of the copper interconnection line crossing the photoetching field. In the two exposure processes, the photoresist corresponding to the exposure area of the cross-photoetching field metal interconnection area is exposed only once, the problems that the width of a copper metal interconnection line is increased and the distance between interconnection lines is narrowed due to secondary exposure are solved, and the method has important significance on realizing cross-photoetching field metal interconnection by using a copper interconnection process.

This invention provides a metal interconnect structure and its fabrication method. The fabrication method includes: forming a first dielectric layer with vias on a bottom metal layer; forming a first metal barrier layer on the first dielectric layer, the first metal barrier layer covering the top surface of the first dielectric layer and covering the sidewalls and bottom surface of the via; forming a first protective layer on the sidewalls of the via, the first protective layer covering the first metal barrier layer on the sidewalls of the via and covering the first metal barrier layer on the edge region of the bottom surface of the via; and under the cover of the first protective layer, etching away the first metal barrier layer on the top surface of the first dielectric layer and removing the area of ​​the first metal barrier layer on the bottom surface of the via not covered by the first protective layer. This avoids metal diffusion problems caused by via etching misalignment and protects the metal barrier layer on the sidewalls of the via. In the metal interconnect structure, the metal barrier layer covers the sidewalls of the via and extends to cover the edge region of the bottom surface of the via.

A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.

A device structure may be formed by: forming dielectric layers with metal interconnect structures formed therein on a substrate; forming at least one heater element over the dielectric layers, each of the at least one heater element including a strip portion, a first terminal portion, and a second terminal portion; forming at least one heater-cover plate stack including a electrically-insulating and thermally-conductive plate including a first material and a semiconducting plate including a second material having a lower electrical resistivity than the first material over a one of the at least one heater element; and depositing and patterning a phase change material layer over the at least one heater-cover plate stack.

The invention discloses a high-density interconnected glass substrate and a manufacturing method thereof, and the high-density interconnected glass substrate comprises a glass core plate which comprises a first surface and a second surface which are oppositely arranged; the glass through hole penetrates through the glass core plate in the thickness direction, the glass through hole comprises a first opening, a second opening and a minimum hole diameter part, the hole diameter of the minimum hole diameter part is smaller than that of the first opening and that of the second opening, the first opening is connected with the first surface, the second opening is connected with the second surface, and the minimum hole diameter part is connected with the glass core plate. The minimum aperture part is positioned in the middle between the first opening and the second opening; the glass through hole further internally comprises a side wall protection part and a metal interconnection column penetrating through the glass core plate in the thickness direction, the diameter of the bottom face, located on the surface of the glass core plate, of the metal interconnection column is larger than or equal to the hole diameter of the minimum hole diameter part, and the side wall protection part is located in the area between the glass through hole and the metal interconnection column. The stress of metal and glass is buffered, and high-density interconnection and high reliability are achieved.

The invention provides a test structure and a metal electromigration failure analysis method. The test structure comprises a first to-be-tested contact hole and a second to-be-tested contact hole which are arranged at two ends of a to-be-tested metal interconnection line; the first excitation bonding pad and the first measurement bonding pad are respectively connected to a first contact hole to be measured through a first metal wire and a second metal wire; the second excitation bonding pad and the second measurement bonding pad are respectively connected to a second contact hole to be measured through a third metal lead and a fourth metal lead; the third measuring bonding pad and the fourth measuring bonding pad are connected to the metal interconnection line to be measured through a fifth metal wire and a sixth metal wire respectively; wherein the first, second, third and fourth metal wires and the metal interconnection line to be tested are positioned on different metal layers; and the fifth metal lead, the sixth metal lead and the to-be-tested metal interconnection line are positioned on the same metal layer. According to the method, the actual electromigration performance of different positions in the electromigration test structure can be comprehensively evaluated, guidance is provided for controlling Joule heat near a metal hole and a metal interconnection line, and guidance is provided for design and improvement of electromigration.

The present invention provides a metal interconnection line and a method of manufacturing the same. The method includes: providing a wafer on which a metal layer comprising an Al layer is formed; performing an ME process on the Al layer using a chlorine-containing gas, thereby removing a partial thickness of the Al layer and producing AlCl3; performing a gradient OE process on the remainder of the Al layer using the chlorine-containing gas and a fluorine-containing gas, thereby removing an undesired part of the remainder of the Al layer and forming an Al interconnection line, wherein in the gradient OE process, a proportion of the fluorine-containing gas is increased stepwise to exchange the AlCl3 for AlF3; and soaking the wafer in an NH4F solution to remove the AlF3. According to the present invention, Cl− ions remaining on the surface of the Al interconnection line from the etching processes for forming the line can be completely removed, preventing corrosion of the Al interconnection line.

This invention belongs to the field of high-temperature protective coating technology, and relates to protective coatings for the surface of SOFC metal interconnects, their preparation, and application. The composite spinel coating consists of an inner NiCr2O4 layer and an outer NiFe2O4 layer. The preparation method involves mechanically polishing, cleaning, and pre-oxidizing the metal interconnect substrate to form an oxide layer on the substrate surface; subsequently, a Ni-Cr-O layer is deposited on the substrate surface using reactive magnetron sputtering, followed by the deposition of a Ni-Fe alloy layer by magnetron sputtering to form a Ni-Cr-O / Ni-Fe composite coating; finally, heat treatment is performed to transform it into a NiCr2O4 / NiFe2O4 composite spinel coating. The prepared coating has a dense structure and a strong bond with the substrate, effectively inhibiting the outward diffusion of Cr and the inward diffusion of O, exhibiting good oxidation resistance and electrical conductivity, and can be used for the protection of the surface of metal interconnects in solid oxide fuel cells.

Via cavities can be formed through a contact-level dielectric layer by performing an anisotropic via etch process that employs a hard mask layer containing hard mask openings as a via etch mask. Sacrificial spacer liners can be formed in peripheral regions of the via cavities. The hard mask layer can be patterned into at least one discrete hard mask plate. Integrated line-and-via cavities can be formed by performing an anisotropic line etch process that employs a combination of a patterned photoresist layer and the at least one discrete hard mask plate as a line etch mask. The patterned photoresist layer, the at least one discrete hard mask plate, and the sacrificial spacer liners can be removed. Metal interconnect structures can be formed within the integrated line-and-via cavities.

The invention provides a forming method of an interconnection structure. First grooves are formed in a first sacrificial layer and a first dielectric layer; a first metal interconnection layer is formed in a first groove and on a first sacrificial layer, and the first metal interconnection layer in the first groove is separated from the first metal interconnection layer on the first sacrificial layer, so that the first sacrificial layer and the first metal interconnection layer on the first sacrificial layer can be removed together. Therefore, only the first metal interconnection layer in the first groove is reserved. And the second metal interconnection layer in the second groove is separated from the second metal interconnection layer on the second sacrificial layer, so that the second sacrificial layer and the second metal interconnection layer on the second sacrificial layer can be removed together, and only the second metal interconnection layer in the second groove is reserved; a dry etching process and a chemical mechanical grinding process do not need to be carried out on the first metal interconnection layer and the second metal interconnection layer, and the process steps are simplified.

A method for producing a package (100), wherein the method comprises: • Applying a metallic interconnect structure (102) comprising a solder or sinter material to a sacrificial support (108); • Mounting an electronic component (104) onto the metallic connecting structure (102); • Encapsulating at least part of the electronic component (104) and the metallic interconnect structure (102) with an encapsulation (106); • then removal of the sacrificial support (108) in order to expose at least part of the metallic connection structure (102); and • Formation of an intermetallic compound (112) in the metallic compound structure (102) at an interface with the sacrificial carrier (108) by means of diffusion or migration of material from the sacrificial carrier (108) into the metallic compound structure (102).