68 results about "Metallic interconnect" patented technology

Aiming at the limitation of the existing metal bump corrosion prevention technology, the invention provides an innovative process: pure silver electroplating is adopted to form a bump main body, a complete gold wrapping structure is formed on all exposed surfaces of the bump main body through secondary electroplating of pure gold, and the process can be used for accurately regulating and controlling the parameters of the secondary electroplating and the size of a secondary photoetching pattern. The exposed surface of the silver bump is uniformly wrapped by the thin gold layer, so that the problem that metal interconnection is easy to corrode in a severe environment in the traditional technology is effectively solved, and comprehensive breakthrough in corrosion resistance, electrical properties and cost effectiveness is realized through innovative silver core and gold shell layered structure design and precise process control.

A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.

The present application provides a bottom layer metal interconnection line structure, at least including a test key and leads connected to the test key; the test key being composed of a plurality of metal lines connected end-to-end; the plurality of metal lines being arranged in the same plane in a winding manner, wherein at least one suspending via structure is provided at each winding point; and two leads are provided and respectively connected to ends of the metal lines located at a head end and a tail end in the test key. The present application increases a maximum root-mean-square current that the winding metal interconnection lines can withstand while improving a heat dissipation problem of the bottom layer metal interconnection lines.

First redistribution interconnect structures having a respective uniform thickness throughout are formed on a top surface of a first adhesive layer over a first carrier wafer. Redistribution dielectric layers and additional redistribution interconnect structures are formed over the first redistribution interconnect structures to provide at least one redistribution structure. A respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure. The first redistribution interconnect structures are physically exposed by removing the first carrier wafer and the first adhesive layer. Fan-out bump structures are formed on the physically exposed first planar surfaces of the first redistribution interconnect structures.

The present invention relates to a metal interconnect structure containing no barrier metal and a method of manufacturing the metal interconnect structure. The method includes: filling at least a first interconnect trench with an intermetallic compound by depositing the intermetallic compound on an insulating layer having the first interconnect trench and a second interconnect trench formed in the insulating layer, the second interconnect trench being wider than the first interconnect trench; performing a planarization process of polishing the intermetallic compound until the insulating layer is exposed; and then performing a height adjustment process of polishing the intermetallic compound and the insulating layer until a height of the intermetallic compound in the first interconnect trench reaches a predetermined height.

The problem of connecting a TSV to a BEOL metal interconnect structure without damaging the BEOL metal interconnect structure is solved by landing the TSV on a metal coupling structure formed during FEOL processing. The metal coupling structure is produced in accordance with design rules that apply to FEOL processing. The metal coupling structure may include substructures that have the composition and shape of wires in a transistor level metal interconnect and substructures that have the composition and shape of metal gate strips. The metal coupling structure may include pluralities of the substructures arrayed across the TSV landing area. The substructures that make up the metal coupling structure are connected to the BEOL metal interconnect through vias.

A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating. wherein the composite etch stop mask layer includes a silicon nitride layer and a stressed layer. A percentage of Si—H bonds in the silicon nitride layer is greater than a percentage of Si—H bonds in the stressed layer.

Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one

This invention relates to the field of semiconductor power device technology, specifically to a GaN HEMT structure with an air cavity and its fabrication method. The structure includes a substrate, an epitaxial layer, a source, a drain, a gate, a composite passivation layer, and an air cavity. The composite passivation layer includes a bottom SiO2 sacrificial layer and a top SiN passivation layer. The SiO2 sacrificial layer between the gate and the source, and between the gate and the drain, is completely removed to form a global air cavity. The fabrication method involves epitaxial fabrication, active region isolation, source-drain-gate fabrication, composite passivation layer deposition, metal interconnect via etching, and wet etching of the sacrificial layer to form the air cavity, ultimately completing the metal interconnect. This invention simultaneously solves the dual technical problems of excessive parasitic capacitance and excessively long heat dissipation path caused by traditional passivation layers, significantly improving the high-frequency characteristics, thermal stability, and operational reliability of GaN HEMT devices. Moreover, the fabrication process is fully compatible with conventional GaN HEMT processes, requiring no special gate structure design, and is easy to industrialize and promote.

The present disclosure provides a magnetic storage bit and a manufacturing method therefor, and a magnetic memory. The magnetic storage bit comprises: an orbit layer; a magnetic tunnel junction, provided with a plurality of functional layers, wherein the plurality of functional layers have a plurality of projections on the orbit layer, the projection of the functional layer having the minimum projection area has a first length in a first direction and a second length in a second direction, the first length is at least twice the second length, the first direction is perpendicular to the second direction, the magnetic tunnel junction is located on one side of the orbit layer, and the direction of the magnetic tunnel junction towards the orbit layer is the stacking direction of the plurality of functional layers; an isolation layer; and a plurality of top electrodes, arranged at intervals in the first direction, wherein the plurality of top electrodes penetrate through an insulating layer and are in contact with the orbit layer. By making the first length of the magnetic tunnel junction at least twice the second length, the distance between the plurality of top electrodes in the magnetic storage bit and through vias of the orbit layer increases, thereby reducing the process difficulty of a metal interconnect.

A 3D microstructure is formed by bonding an upper plate (1) to a lower plate. A blind hole (120) with a high aspect ratio is formed in the upper plate (1) prior to the bonding of the plates, with a bottom extending through the thickness of the substrate (11) of the plate. The formation of the hole (120) is stopped at a predetermined distance (h) from the rear face (10) of the substrate (11). The hole is filled with metal to form a metallic pillar (120) for the purpose of creating an electrical and / or thermal metallic interconnection between the upper and lower plates after the hybrid bonding.After the upper plate (1) is flipped and bonded to the lower plate, a thinning of the rear substrate (11) of the upper plate (1) exposes the metal at the bottom of the blind hole made before the hybrid bonding. This makes the metal pillar a through-hole through the rear face of the thinned substrate (11). This pillar can constitute a through-hole via (TOV), essentially created before the plates are bonded. Figure 3.

The utility model provides a pHEMT device. The pHEMT device comprises a substrate and a metal interconnection structure formed on the substrate. The metal interconnection structure comprises an ohmic contact layer, a first metal coating and a second metal coating which are sequentially stacked from bottom to top, the first metal coating comprises a first adhesion layer, a first metal structure layer, a second metal structure layer and a second adhesion layer which are sequentially stacked from bottom to top, the resistance value of the first metal structure layer is smaller than that of the second metal structure layer, and the hardness of the second metal structure layer is larger than that of the first metal structure layer. In the first metal coating, the second metal structure layer with higher hardness is formed to improve the surface roughness caused by the subsequent etching process and prevent the first metal structure layer from diffusing to the second adhesion layer to form aggregation points on the surface of the first metal coating. Therefore, the possibility that electroplating piebaldness is generated when the second metal coating is electroplated on the first metal coating can be reduced.

The invention provides a WAT test structure and a test method, the WAT test structure comprises a first test structure and a second test structure, and a first metal interconnection structure in the first test structure is electrically connected with a first control gate; the second metal interconnection structure in the second test structure is disconnected with the second control gate, and the structure of the second control gate is the same as that of the first control gate. In the test method, whether the failure occurs in the control gate or the metal interconnection structure can be effectively judged according to the leakage current of the first test structure and the leakage current of the second test structure.

The invention relates to the technical field of hybrid bonding, and discloses a preparation method of a hybrid bonding structure and the hybrid bonding structure.The method comprises the steps that a first wafer and a second wafer are provided, and a plurality of bonding pads and insulating layers covering the bonding pads are arranged on the wafers at intervals; depositing aluminum nitride on the insulating layer of the first wafer to form a first heat dissipation layer, and depositing aluminum nitride on the insulating layer of the second wafer to form a second heat dissipation layer; forming a plurality of first openings in the first heat dissipation layer, and forming a plurality of second openings in the second heat dissipation layer; forming a first metal interconnection structure in the plurality of first openings, and forming a second metal interconnection structure in the plurality of second openings; and carrying out bonding processing on one side, far away from the insulating layer of the first wafer, of the first heat dissipation layer and one side, far away from the insulating layer of the second wafer, of the second heat dissipation layer to obtain a hybrid bonding structure. According to the invention, the heat dissipation efficiency can be greatly improved, and heat generated by devices in the wafer can be timely dissipated.

An atmospheric pressure plasma apparatus and method are disclosed that operate with a multigas mixture to provide a high concentration of reactive neutral species for cleaning and activating the surfaces of substrates, including those with metal interconnects embedded in the substrate.

The invention provides the cleaning composition, the corrosion composition, the kit, the corrosion process and the device, the problem that the corrosion selectivity of AlN relative to AlOx is relatively low is solved, and metal materials such as copper and high-quality cobalt in a metal interconnection circuit are not damaged when a hard mask is removed; the cleaning composition comprises a metal protective agent and a nitrogen-containing heterocyclic compound, the nitrogen-containing heterocyclic compound is selected from at least one of nitrogen-containing heterocyclic compounds and nitrogen-containing heterocyclic compounds; the definition of each group is described in the specification.

A guidewire driven brain-computer interface system for minimally invasive implantation is provided that includes a flexible electrode array and a plurality of flexible guidewires attached to the flexible electrode array. The flexible electrode array comprises a plurality of insulated poly-p-xylylene-C layers, metal interconnection lines and electrodes. The plurality of flexible guidewires are configured to be guided by an external mechanical force such that the flexible electrode array passes through a craniotomy field and is deployed by tracking the plurality of flexible guidewires. The flexible guidewires each include a manipulation tip and a pull wire.

The invention relates to a metal surface alloying treatment method, a metal interconnection layer side wall alloying treatment method, a metal interconnection layer and a display panel. The treatment method comprises the following steps: preparing an acidic electrolyte containing first metal ions, and carrying out electrolytic treatment on the electrolyte by taking second metal as a cathode; in the electrolytic treatment process, an inhibitor is added into the electrolyte; wherein the inhibitor comprises a thiocarboxylic acid material, and the reducibility of the second metal is higher than that of hydrogen. First metal ions are firstly deposited to form loose first metal; and a small amount of ions are also dissolved out from the second metal and are continuously subjected to atomic-level co-deposition with the ions of the first metal under the electrolysis action, a uniform alloy layer is formed, and alloying treatment of the surface of the second metal is achieved. The added inhibitor is gradually decomposed, the dielectric constant of the electrolyte is gradually reduced, and the codeposition reaction is automatically terminated when the dielectric constant is reduced to a certain value. Therefore, the method does not need high-temperature treatment, and the alloying treatment effect is controllable and stable.

The invention discloses a method for forming a TSV for a back irradiation image sensor, and the method comprises the steps: firstly carrying out the deposition of a deep groove of a TSV through hole to form a filling structure with a gap, then carrying out the etching to a metal interconnection layer, and finally growing a metal layer in the groove; and on the other hand, in a limited design area, the isolation structures adjacent to the TSV are electrically connected at the same time, so that potential control is added for the deep trench isolation structure to enhance the isolation effect, the process cost is reduced, and the reliability of the image sensor is improved at the same time.

This invention discloses an etching method for a back-illuminated image sensor and a back-illuminated image sensor. The etching method includes: providing a substrate, wherein an epitaxial layer with a hermetically sealed cavity and a metal interconnect layer are sequentially formed on the front side of the substrate; etching from the back side of the substrate using an etching process to open the hermetically sealed cavity along a direction perpendicular to the substrate surface and extend the bottom of the cavity downward; the etching process includes alternating etching and deposition steps; by controlling the ratio of the processing time of the etching step to the processing time of the deposition step to 0.75:1 to 1.5:1; and the flow rate ratio of the etching gas used in the etching step to the deposition gas used in the deposition step to 1:1.3 to 1:0.7, a continuously accumulated protective layer is formed at the bottom of the cavity. When the protective layer reaches a predetermined thickness or reduces the local etching rate to a preset threshold, further material etching is inhibited or prevented, so that the etching automatically stops at the required depth, and the extended bottom of the cavity is higher than the top of the metal interconnect layer.

A first metal interconnection pattern is formed over a substrate. A spacer layer is selectively deposited on the exposed surfaces of the first metal interconnection pattern. Subsequently, a metal overburden layer is deposited on the spacer layer. The excess portion of the metal overburden layer is removed, i.e., that portion deposited over a top surface of the metal interconnection pattern and the spacer layer. This forms a second metal interconnection pattern. The elements of the second metal interconnection pattern are located between respective elements of the first metal interconnection pattern.

A bonded assembly includes a first memory die including a first alternating stack of first insulating layers and first electrically conductive layers, first memory stack structures vertically extending through the first alternating stack, first metal interconnect structures embedded within first memory-die inorganic dielectric layers, and first memory-die copper bonding pads embedded within a first polymer dielectric layer, and a second memory die including a second alternating stack of second insulating layers and second electrically conductive layers, second memory stack structures vertically extending through the second alternating stack, second metal interconnect structures embedded within second memory-die inorganic dielectric layers, and second memory-die copper bonding pads embedded within a second polymer dielectric layer.

The invention relates to a metal interconnection layer and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; the dielectric laminations and the initial metal wires are alternately arranged on the substrate along a first direction parallel to the first surface; the side wall of the initial metal wire comprises a protruding part, and the protruding part is embedded in the dielectric lamination layer along the first direction; etching the dielectric laminated layer, forming a groove between the adjacent initial metal wires, and then forming a liner oxide layer covering the inner surface of the groove and the top surfaces of the initial metal wires; the bottom face of the groove is lower than the bottom face of the protruding part. Performing a surface treatment process on the exposed surface of the liner oxide layer, and at least adding a target dangling bond for increasing the coating rate on the inner surface of the groove not lower than the convex part; after an oxide layer is formed in the groove, removing the rest of the film layer with the top surface higher than the top surface of the protruding part to obtain a target metal wire; an air gap structure is arranged in the oxide layer. The technological process of the air gap structure in the metal interconnection layer can be simplified.

The invention provides an interconnection structure and a manufacturing method thereof, and the method comprises the steps: providing a substrate which comprises a substrate and a dielectric layer which are stacked in sequence, and forming a groove in the dielectric layer; forming a seed crystal layer on the inner surface of the groove; forming a first metallization layer on the seed crystal layer through a megasonic assisted electroplating process; a second metallization layer is formed in the trench and over the dielectric layer. Before the metal filling is formed in the groove or the through hole, the metalized layer is plated on the seed crystal layer through the megasonic-assisted electroplating process, the grain size of the plated metalized layer is more uniform and compact, the electric field distribution in the metal interconnection line is more uniform, and the electromigration phenomenon is improved.

The invention provides a metal interconnection structure and a forming method thereof. An adhesion promoting layer in the metal interconnection structure is only located on the side wall of a groove; the adhesion promoting layer adsorbs a precursor of the first diffusion barrier layer, so that the first diffusion barrier layer is only formed on the side wall of the groove and is used for blocking metal diffusion, and metal filling is prevented from being affected by deposition of the first diffusion barrier layer at the bottom of the groove; the second diffusion barrier layer covers the first diffusion barrier layer, is used for blocking metal diffusion, and is used for supporting the first diffusion barrier layer and inhibiting the first diffusion barrier layer from cracking. The adhesion promoting layer is adopted to reduce the thickness requirement of a traditional metal barrier layer and improve the wettability of metal at the same time, the second diffusion barrier layer is made of high-entropy nitride or high-entropy alloy and plays a main role in blocking metal diffusion, the total thickness of the first diffusion barrier layer and the second diffusion barrier layer is reduced, and the process requirement of 40 nm nodes or below is met; lattice matching of the first diffusion barrier layer reduces interface stress, and metal filling defects are avoided.

An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating. The composite etch stop mask layer includes a silicon nitride layer and a stressed layer. A percentage of Si—H bonds in the silicon nitride layer is greater than a percentage of Si—H bonds in the stressed layer.

The present invention relates to a solid oxide cell (SOC) stack made of single repeating units (SRU), each of which comprising: —a ceramic cell with a corrugated membrane and a sealing frame with gas distribution holes and channels, and—a flat metallic interconnect.

A die seal ring structure includes a metal interconnect structure on a substrate, in which the metal interconnect structure includes an inter-metal dielectric (IMD) layer on the substrate and a first metal interconnection disposed in the IMD layer. Preferably, a first side of the first metal interconnection includes a comb-shape portion in a top view, a second side of the first metal interconnection includes a linear line, a third side of the first metal interconnection includes a linear line, and a fourth side of the first metal interconnection includes a linear line.