103 results about "Metallic interconnect" patented technology

The invention discloses a thin film resistor device and a preparation method thereof. The preparation method comprises the following steps: forming a second insulating layer on a first metal interconnection layer and an exposed first insulating layer; forming a thin-film resistor structure in a partial region of the upper surface of the second insulating layer; forming a third insulating layer on the thin-film resistor structure and the exposed upper surface of the second insulating layer; forming a first contact hole extending from the upper surface of the third insulating layer to the first metal interconnection layer, and filling the first contact hole with first contact metal; forming a second metal interconnection layer on the upper surface of the third insulating layer; forming a fourth insulating layer on the second metal interconnection layer and the exposed third insulating layer; and forming a second contact hole extending from the upper surface of the fourth insulating layer to the second metal interconnection layer and a third contact hole extending from the upper surface of the fourth insulating layer to the thin-film resistor structure, and filling second contact metal and third contact metal in the second contact hole and the third contact hole respectively. According to the thin film resistor device and the preparation method thereof, the stability of the device can be improved.

Aiming at the limitation of the existing metal bump corrosion prevention technology, the invention provides an innovative process: pure silver electroplating is adopted to form a bump main body, a complete gold wrapping structure is formed on all exposed surfaces of the bump main body through secondary electroplating of pure gold, and the process can be used for accurately regulating and controlling the parameters of the secondary electroplating and the size of a secondary photoetching pattern. The exposed surface of the silver bump is uniformly wrapped by the thin gold layer, so that the problem that metal interconnection is easy to corrode in a severe environment in the traditional technology is effectively solved, and comprehensive breakthrough in corrosion resistance, electrical properties and cost effectiveness is realized through innovative silver core and gold shell layered structure design and precise process control.

A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.

The invention discloses a metallization method for the side wall of a cavity of a low-temperature co-fired ceramic substrate. The metallization method comprises the following steps of: sequentially performing punching treatment on each layer of green ceramic chip according to a preset cavity outline; during lamination, the hole sites on the adjacent green ceramic chips are arranged in a staggered and overlapped manner; the holes are filled with metal slurry in a solid mode, and a blank plate with solid metal points is obtained after drying and leveling treatment; each layer of blank plate is cut according to the cavity contour in sequence; the outline of the cavity is a line connected with each solid metal point on the blank plate; and laminating and pressing the cut blank plates, and co-firing to obtain the ceramic substrate with the metalized cavity side wall. The round holes are designed in the contour lines of the cavities of the green ceramic chips, then the solid metal slurry is filled in the green ceramic chip stage, and the green ceramic chips are laminated and co-fired, so that metal interconnection in all the round holes in the contour area of the substrate is realized, after the cavities are formed, the filled metal slurry is immediately exposed, and metallization of the side walls of the cavities of the substrate is completed.

The invention relates to the field of reliable interconnection between carbon nanotube fibers and metal, in particular to a method for achieving high-reliability interconnection between the carbon nanotube fibers and the metal through brazing. The method comprises the following steps: selecting a traditional tin-based brazing solder, heating a to-be-welded metal matrix to a preset temperature by using a planar heating stage in air, wetting and spreading a solder alloy on the surface of the matrix after the solder alloy is molten, putting a to-be-welded part of the pretreated carbon nanotube fiber on the surface of the molten liquid-state solder alloy, and welding the to-be-welded part of the pretreated carbon nanotube fiber; and when the solder alloy on the surface of the carbon nanotube fiber is melted, the solder alloy is quickly solidified, so that the brazed interconnection of the carbon nanotube fiber and the metal is realized. In the welding process, deionized water is sprayed to molten welding flux to achieve rapid cooling and solidification, the problem that welding cannot be achieved due to the large density difference between carbon nano tube fibers and metal is solved, and the problem that welding is not firm is solved by introducing a middle buffer layer with high bonding energy to the to-be-welded portion of the carbon nano tube fibers. And the prepared carbon nanotube fiber-metal interconnection piece has high service reliability.

The invention provides a cleaning method after through hole etching and a forming method of a metal interconnection structure, the cleaning method comprises the following steps: providing a substrate, forming a through hole used for connecting a first metal interconnection layer and metal tungsten on the substrate, the metal tungsten being a tungsten contact or a tungsten plug in a first dielectric layer, and the first dielectric layer being silicon dioxide; forming a silicon nitride layer on the surface of the through hole; carrying out first cleaning treatment by using a phosphoric acid solution, removing the silicon nitride layer and generating silicide for inhibiting etching of silicon dioxide; and carrying out secondary cleaning treatment by using a mixed solution of DHF, sulfuric acid and phosphoric acid. According to the method, silicon nitride is sequentially deposited on the surface of the through hole in advance after the through hole is completed, then the silicon nitride layer is pretreated through the phosphoric acid solution, and a product for inhibiting etching of silicon dioxide is generated while the silicon nitride is removed, so that it is guaranteed that loss of interlayer media is reduced or even completely avoided in the subsequent cleaning process.

The present application provides a bottom layer metal interconnection line structure, at least including a test key and leads connected to the test key; the test key being composed of a plurality of metal lines connected end-to-end; the plurality of metal lines being arranged in the same plane in a winding manner, wherein at least one suspending via structure is provided at each winding point; and two leads are provided and respectively connected to ends of the metal lines located at a head end and a tail end in the test key. The present application increases a maximum root-mean-square current that the winding metal interconnection lines can withstand while improving a heat dissipation problem of the bottom layer metal interconnection lines.

The present invention relates to a method for fabricating metal interconnects. The method includes: (1) providing a substrate and forming a material layer on the upper surface of the substrate; (2) forming a metal layer on the upper surface of the material layer and forming an etching barrier layer on the upper surface of the metal layer; (3) etching the metal layer outside the etching barrier layer by a dry etching process to form a thin metal layer; (4) passivating the thin metal layer by a passivation process to form a passivation layer; (5) etching the passivation layer by a wet etching process; (6) removing the etching barrier layer to leave an interconnect layer. This method can reduce the damage to the target substrate material during the dry etching process, maintain the intrinsic properties of the material, is beneficial to improving the electrical properties of the fabricated devices, and expands the application scope of metal interconnects in fragile materials such as two-dimensional materials, organic semiconductors, and perovskites.

First redistribution interconnect structures having a respective uniform thickness throughout are formed on a top surface of a first adhesive layer over a first carrier wafer. Redistribution dielectric layers and additional redistribution interconnect structures are formed over the first redistribution interconnect structures to provide at least one redistribution structure. A respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure. The first redistribution interconnect structures are physically exposed by removing the first carrier wafer and the first adhesive layer. Fan-out bump structures are formed on the physically exposed first planar surfaces of the first redistribution interconnect structures.

The present invention relates to a metal interconnect structure containing no barrier metal and a method of manufacturing the metal interconnect structure. The method includes: filling at least a first interconnect trench with an intermetallic compound by depositing the intermetallic compound on an insulating layer having the first interconnect trench and a second interconnect trench formed in the insulating layer, the second interconnect trench being wider than the first interconnect trench; performing a planarization process of polishing the intermetallic compound until the insulating layer is exposed; and then performing a height adjustment process of polishing the intermetallic compound and the insulating layer until a height of the intermetallic compound in the first interconnect trench reaches a predetermined height.

The problem of connecting a TSV to a BEOL metal interconnect structure without damaging the BEOL metal interconnect structure is solved by landing the TSV on a metal coupling structure formed during FEOL processing. The metal coupling structure is produced in accordance with design rules that apply to FEOL processing. The metal coupling structure may include substructures that have the composition and shape of wires in a transistor level metal interconnect and substructures that have the composition and shape of metal gate strips. The metal coupling structure may include pluralities of the substructures arrayed across the TSV landing area. The substructures that make up the metal coupling structure are connected to the BEOL metal interconnect through vias.

A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating. wherein the composite etch stop mask layer includes a silicon nitride layer and a stressed layer. A percentage of Si—H bonds in the silicon nitride layer is greater than a percentage of Si—H bonds in the stressed layer.

Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one

The invention provides a method for removing a metal polymer formed in a metal interconnection process, and the method comprises the steps: providing a semiconductor structure which comprises a first metal layer, an NDC layer, a USG layer, a DARC layer and a photoresist layer; etching the DARC layer, the USG layer and a part of thickness of the NDC layer along the opening of the photoresist layer to form a filling groove; etching the residual thickness of the NDC layer at the bottom of the filling groove until the first metal layer is exposed, and etching the photoresist layer, the DARC layer and the USG layer at the same time to enlarge the width of the filling groove, at the moment, forming a metal polymer on the side wall of the photoresist layer; removing the photoresist layer by adopting high-frequency source power of 500W-1500W, F-containing strong oxidizing gas and high-flow CO2 gas, and at the moment, scattering the metal polymer; the scattered metal polymer is rapidly extracted and removed; and washing the semiconductor structure after the photoresist layer is removed. According to the invention, the problem of high product defects caused by metal polymers formed in the existing metal interconnection process is solved.

According to the preparation method of the metal interconnection structure provided by the invention, the titanium nitride layer is formed twice, the first titanium nitride layer formed before the metal silicide layer is formed through high-temperature annealing for the first time and before the metal layer is deposited for the second time can well isolate the lower titanium layer, so that the titanium layer is prevented from being oxidized by contacting with oxygen; although the first titanium nitride layer may crack in the high-temperature annealing process, the second titanium nitride layer continues to be formed on the surface of the first titanium nitride layer after the high-temperature annealing and before the metal layer deposition process, and the second titanium nitride layer can effectively fill cracks formed in the first titanium nitride layer, so that in the metal layer deposition process, the first titanium nitride layer is not prone to cracking. According to the invention, the contact between deposition source gas for depositing the metal layer and the titanium layer below the titanium nitride layer can be effectively avoided, so that the generation of volcanic defects is reduced or even avoided, the electrical performance of a subsequently formed metal interconnection structure is effectively improved, and the product yield is ensured; in addition, the preparation method does not need to introduce additional process equipment, and is easy to implement.

This invention relates to the field of semiconductor power device technology, specifically to a GaN HEMT structure with an air cavity and its fabrication method. The structure includes a substrate, an epitaxial layer, a source, a drain, a gate, a composite passivation layer, and an air cavity. The composite passivation layer includes a bottom SiO2 sacrificial layer and a top SiN passivation layer. The SiO2 sacrificial layer between the gate and the source, and between the gate and the drain, is completely removed to form a global air cavity. The fabrication method involves epitaxial fabrication, active region isolation, source-drain-gate fabrication, composite passivation layer deposition, metal interconnect via etching, and wet etching of the sacrificial layer to form the air cavity, ultimately completing the metal interconnect. This invention simultaneously solves the dual technical problems of excessive parasitic capacitance and excessively long heat dissipation path caused by traditional passivation layers, significantly improving the high-frequency characteristics, thermal stability, and operational reliability of GaN HEMT devices. Moreover, the fabrication process is fully compatible with conventional GaN HEMT processes, requiring no special gate structure design, and is easy to industrialize and promote.

The present disclosure provides a magnetic storage bit and a manufacturing method therefor, and a magnetic memory. The magnetic storage bit comprises: an orbit layer; a magnetic tunnel junction, provided with a plurality of functional layers, wherein the plurality of functional layers have a plurality of projections on the orbit layer, the projection of the functional layer having the minimum projection area has a first length in a first direction and a second length in a second direction, the first length is at least twice the second length, the first direction is perpendicular to the second direction, the magnetic tunnel junction is located on one side of the orbit layer, and the direction of the magnetic tunnel junction towards the orbit layer is the stacking direction of the plurality of functional layers; an isolation layer; and a plurality of top electrodes, arranged at intervals in the first direction, wherein the plurality of top electrodes penetrate through an insulating layer and are in contact with the orbit layer. By making the first length of the magnetic tunnel junction at least twice the second length, the distance between the plurality of top electrodes in the magnetic storage bit and through vias of the orbit layer increases, thereby reducing the process difficulty of a metal interconnect.

A 3D microstructure is formed by bonding an upper plate (1) to a lower plate. A blind hole (120) with a high aspect ratio is formed in the upper plate (1) prior to the bonding of the plates, with a bottom extending through the thickness of the substrate (11) of the plate. The formation of the hole (120) is stopped at a predetermined distance (h) from the rear face (10) of the substrate (11). The hole is filled with metal to form a metallic pillar (120) for the purpose of creating an electrical and / or thermal metallic interconnection between the upper and lower plates after the hybrid bonding.After the upper plate (1) is flipped and bonded to the lower plate, a thinning of the rear substrate (11) of the upper plate (1) exposes the metal at the bottom of the blind hole made before the hybrid bonding. This makes the metal pillar a through-hole through the rear face of the thinned substrate (11). This pillar can constitute a through-hole via (TOV), essentially created before the plates are bonded. Figure 3.

The utility model provides a pHEMT device. The pHEMT device comprises a substrate and a metal interconnection structure formed on the substrate. The metal interconnection structure comprises an ohmic contact layer, a first metal coating and a second metal coating which are sequentially stacked from bottom to top, the first metal coating comprises a first adhesion layer, a first metal structure layer, a second metal structure layer and a second adhesion layer which are sequentially stacked from bottom to top, the resistance value of the first metal structure layer is smaller than that of the second metal structure layer, and the hardness of the second metal structure layer is larger than that of the first metal structure layer. In the first metal coating, the second metal structure layer with higher hardness is formed to improve the surface roughness caused by the subsequent etching process and prevent the first metal structure layer from diffusing to the second adhesion layer to form aggregation points on the surface of the first metal coating. Therefore, the possibility that electroplating piebaldness is generated when the second metal coating is electroplated on the first metal coating can be reduced.

The invention provides a WAT test structure and a test method, the WAT test structure comprises a first test structure and a second test structure, and a first metal interconnection structure in the first test structure is electrically connected with a first control gate; the second metal interconnection structure in the second test structure is disconnected with the second control gate, and the structure of the second control gate is the same as that of the first control gate. In the test method, whether the failure occurs in the control gate or the metal interconnection structure can be effectively judged according to the leakage current of the first test structure and the leakage current of the second test structure.

The invention relates to the technical field of hybrid bonding, and discloses a preparation method of a hybrid bonding structure and the hybrid bonding structure.The method comprises the steps that a first wafer and a second wafer are provided, and a plurality of bonding pads and insulating layers covering the bonding pads are arranged on the wafers at intervals; depositing aluminum nitride on the insulating layer of the first wafer to form a first heat dissipation layer, and depositing aluminum nitride on the insulating layer of the second wafer to form a second heat dissipation layer; forming a plurality of first openings in the first heat dissipation layer, and forming a plurality of second openings in the second heat dissipation layer; forming a first metal interconnection structure in the plurality of first openings, and forming a second metal interconnection structure in the plurality of second openings; and carrying out bonding processing on one side, far away from the insulating layer of the first wafer, of the first heat dissipation layer and one side, far away from the insulating layer of the second wafer, of the second heat dissipation layer to obtain a hybrid bonding structure. According to the invention, the heat dissipation efficiency can be greatly improved, and heat generated by devices in the wafer can be timely dissipated.

An atmospheric pressure plasma apparatus and method are disclosed that operate with a multigas mixture to provide a high concentration of reactive neutral species for cleaning and activating the surfaces of substrates, including those with metal interconnects embedded in the substrate.

The invention provides the cleaning composition, the corrosion composition, the kit, the corrosion process and the device, the problem that the corrosion selectivity of AlN relative to AlOx is relatively low is solved, and metal materials such as copper and high-quality cobalt in a metal interconnection circuit are not damaged when a hard mask is removed; the cleaning composition comprises a metal protective agent and a nitrogen-containing heterocyclic compound, the nitrogen-containing heterocyclic compound is selected from at least one of nitrogen-containing heterocyclic compounds and nitrogen-containing heterocyclic compounds; the definition of each group is described in the specification.

The invention relates to a bionic paper-cut-shaped epidermal electrode for dynamic electrocardiogram monitoring of a human body and a preparation method, the whole bionic paper-cut-shaped epidermal electrode is of a three-electrode single-lead multi-layer combined structure, and the bionic paper-cut-shaped epidermal electrode comprises a top polydimethylsiloxane thin film layer, an adhesion layer, a copper metal functional layer, a copper metal interconnection line and a bottom polyimide insulating layer which are arranged in sequence; the copper metal functional layer is formed by sequentially connecting four groups of subunits in series through four-side arc flexible hinges, and a deformable closed ring is formed in the copper metal functional layer; each group of subunits is composed of an N * N rigid dot array and telescopic flexible hinges connected between adjacent dots, and the telescopic flexible hinges adopt a snake belly imitating hexagonal pattern hinge form; the copper metal interconnection line is snake-shaped; the top polydimethylsiloxane thin film layer is tightly attached to and fixedly connected with one side of the adhesion layer, the copper metal functional layer is tightly attached to and fixedly connected with the other side of the adhesion layer, and the copper metal interconnection line is fixedly connected with a bonding pad of the copper metal functional layer in an adhesive mode and is tightly attached to and fixedly connected with the adhesion layer at the same time. And the bottom polyimide insulating layer is tightly attached and fixedly connected with the other side of the copper metal interconnection wire. According to the invention, a good use effect is achieved.

In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.

A guidewire driven brain-computer interface system for minimally invasive implantation is provided that includes a flexible electrode array and a plurality of flexible guidewires attached to the flexible electrode array. The flexible electrode array comprises a plurality of insulated poly-p-xylylene-C layers, metal interconnection lines and electrodes. The plurality of flexible guidewires are configured to be guided by an external mechanical force such that the flexible electrode array passes through a craniotomy field and is deployed by tracking the plurality of flexible guidewires. The flexible guidewires each include a manipulation tip and a pull wire.

The invention relates to a metal surface alloying treatment method, a metal interconnection layer side wall alloying treatment method, a metal interconnection layer and a display panel. The treatment method comprises the following steps: preparing an acidic electrolyte containing first metal ions, and carrying out electrolytic treatment on the electrolyte by taking second metal as a cathode; in the electrolytic treatment process, an inhibitor is added into the electrolyte; wherein the inhibitor comprises a thiocarboxylic acid material, and the reducibility of the second metal is higher than that of hydrogen. First metal ions are firstly deposited to form loose first metal; and a small amount of ions are also dissolved out from the second metal and are continuously subjected to atomic-level co-deposition with the ions of the first metal under the electrolysis action, a uniform alloy layer is formed, and alloying treatment of the surface of the second metal is achieved. The added inhibitor is gradually decomposed, the dielectric constant of the electrolyte is gradually reduced, and the codeposition reaction is automatically terminated when the dielectric constant is reduced to a certain value. Therefore, the method does not need high-temperature treatment, and the alloying treatment effect is controllable and stable.

The invention discloses a method for forming a TSV for a back irradiation image sensor, and the method comprises the steps: firstly carrying out the deposition of a deep groove of a TSV through hole to form a filling structure with a gap, then carrying out the etching to a metal interconnection layer, and finally growing a metal layer in the groove; and on the other hand, in a limited design area, the isolation structures adjacent to the TSV are electrically connected at the same time, so that potential control is added for the deep trench isolation structure to enhance the isolation effect, the process cost is reduced, and the reliability of the image sensor is improved at the same time.

This invention discloses an etching method for a back-illuminated image sensor and a back-illuminated image sensor. The etching method includes: providing a substrate, wherein an epitaxial layer with a hermetically sealed cavity and a metal interconnect layer are sequentially formed on the front side of the substrate; etching from the back side of the substrate using an etching process to open the hermetically sealed cavity along a direction perpendicular to the substrate surface and extend the bottom of the cavity downward; the etching process includes alternating etching and deposition steps; by controlling the ratio of the processing time of the etching step to the processing time of the deposition step to 0.75:1 to 1.5:1; and the flow rate ratio of the etching gas used in the etching step to the deposition gas used in the deposition step to 1:1.3 to 1:0.7, a continuously accumulated protective layer is formed at the bottom of the cavity. When the protective layer reaches a predetermined thickness or reduces the local etching rate to a preset threshold, further material etching is inhibited or prevented, so that the etching automatically stops at the required depth, and the extended bottom of the cavity is higher than the top of the metal interconnect layer.