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8910 results about "Photoresist" patented technology

A photoresist is a light-sensitive material used in several processes, such as photolithography and photoengraving, to form a patterned coating on a surface. This process is crucial in the electronic industry.

Method of making a cutting instrument having integrated sensors

A cutting instrument including a metal blade has a recess formed therein and a semiconductor substrate affixed to the blade in the recess. The semiconductor substrate includes at least one sensor formed thereon. The sensor formed on the semiconductor substrate may comprise at least one or an array of a strain sensors, pressure sensors, nerve sensors, temperature sensors, density sensors, accelerometers, and gyroscopes. The cutting instrument may also further include a handle wherein the blade is affixed to the handle and the semiconductor substrate is electrically coupled to the handle. The handle may then be coupled, either physically or by wireless transmission, to a computer that is adapted to display information to a person using the cutting instrument based on signals generated by one or more of the sensors formed on the semiconductor substrate. The computer or handle may also be adapted to store data based on the signals generated by one or more of the sensors. A method of making said cutting instrument includes the steps of at least one sensor being formed on a semiconductor wafer and a layer of photoresist being applied on a top side of the semiconductor wafer according to a pattern that matches the defined shape of the semiconductor substrate. The portion of the semiconductor wafer not covered by the photoresist is removed and thereafter the photoresist is removed from the semiconductor wafer, thereby leaving the semiconductor substrate having a defined shape and at least one sensor formed thereon. The semiconductor substrate having a defined shape and at least one sensor formed thereon is then affixed to a metal blade in a recess formed in said blade.
Owner:VERIMETRA

Method for integrated circuit fabrication using pitch multiplication

Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.
Owner:ROUND ROCK RES LLC

Method to selectively fill recesses with conductive metal

Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer. In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After electroplating, the resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP. Also provided is a semiconductor structure obtained by the above processes.
Owner:GLOBALFOUNDRIES INC

Method of electroless plating copper on nitride barrier

A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line. The third embodiment electroless deposits metal over a metal barrier layer that is roughen by chemical mechanical polishing. A solder bump is formed using an electroless deposition of Cu or Ni by: depositing an Al layer 220 and a barrier metal layer 230 over a substrate 10. The barrier layer 230 is polished and activated. Next, the aluminum layer 220 and the barrier metal layer 230 are patterned. A metal layer 240 is electroless deposited. Next a solder bump 250 is formed over the electroless metal layer 240.
Owner:TAIWAN SEMICON MFG CO LTD

Planarizing etch hardmask to increase pattern density and aspect ratio

Methods for manufacturing a semiconductor device in a processing chamber are provided. In one embodiment, a method includes depositing over a substrate a first base material having a first set of interconnect features, filling an upper portion of the first set of interconnect features with an ashable material to an extent capable of protecting the first set of interconnect features from subsequent processes while being easily removable when desired, planarizing an upper surface of the first base material such that an upper surface of the ashable material filled in the first set of interconnect features is at the same level with the upper surface of the first base material, providing a substantial planar outer surface of the first base material, depositing a first film stack comprising a second base material on the substantial planar outer surface of the first base material, forming a second set of interconnect features in the second base material, wherein the second set of interconnect features are aligned with the first set of interconnect features, and removing the ashable material from the first base material, thereby extending a feature depth of the semiconductor device by connecting the second set of interconnect features to the first set of interconnect features. In another embodiment, a method includes providing a base material having a first film stack deposited thereon, wherein the base material is formed over the substrate and having a first set of interconnect features filled with an amorphous carbon material, the first film stack comprising a first amorphous carbon layer deposited on a surface of the base material, a first anti-reflective coating layer deposited on the first amorphous carbon layer, and a first photoresist layer deposited on the first anti-reflective coating layer, and patterning a portion of the first photoresist layer by shifting laterally a projection of a mask on the first photoresist layer relative to the substrate a desired distance, thereby introducing into the first photoresist layer a first feature pattern to be transferred to the underlying base material, wherein the first feature pattern is not aligned with the first set of interconnect features.
Owner:APPLIED MATERIALS INC

Method for etching a trench having rounded top and bottom corners in a silicon substrate

The present invention provides straight forward methods for plasma etching a trench having rounded top corners, or rounded bottom corners, or both in a silicon substrate. A first method for creating a rounded top corner on the etched silicon trench comprises etching both an overlying silicon oxide layer and an upper portion of the silicon substrate during a "break-through" step which immediately precedes the step in which the silicon trench is etched. The plasma feed gas for the break-through step comprises carbon and fluorine. In this method, the photoresist layer used to pattern the etch stack is preferably not removed prior to the break-through etching step. Subsequent to the break-through step, a trench is etched to a desired depth in the silicon substrate using a different plasma feed gas composition. A second method for creating a rounded top corner on the etched silicon trench comprises formation of a built-up extension on the sidewall of an overlying patterned silicon nitride hard mask during etch (break-through) of a silicon oxide adhesion layer which lies between the hard mask and a silicone substrate. The built-up extension upon the silicon nitride sidewall acts as a sacrificial masking material during etch of the silicon trench, delaying etching of the silicon at the outer edges of the top of the trench. This permits completion of trench etching with delayed etching of the top corner of the trench and provides a more gentle rounding (increased radius) at the top corners of the trench. During the etching of the silicon trench to its final dimensions, it is desirable to round the bottom corners of the finished silicon trench. We have discovered that a more rounded bottom trench corner is obtained using a two-step silicon etch process where the second step of the process is carried out at a higher process chamber pressure than the first step.
Owner:APPLIED MATERIALS INC

Process for roll-to-roll manufacture of a display by synchronized photolithographic exposure on a substrate web

<heading lvl="0">Abstract of Disclosure</heading> This invention relates to an electrophoretic display or a liquid crystal display and novel processes for its manufacture. The electrophoretic display (EPD) of the present invention comprises microcups of well-defined shape, size and aspect ratio and the microcups are filled with charged pigment particles dispersed in an optically contrasting dielectric solvent. The liquid crystal display (LCD) of this invention comprises well-defined microcups filled with at least a liquid crystal composition having its ordinary refractive index matched to that of the isotropic cup material. A novel roll-to-roll process and apparatus of the invention permits the display manufacture to be carried out continuously by a synchronized photo-lithographic process. The synchronized roll-to-roll process and apparatus permits a pre-patterned photomask, formed as a continuous loop, to be rolled in a synchronized motion in close parallel alignment to a web which has been pre-coated with a radiation sensitive material, so as to maintain image alignment during exposure to a radiation source. The radiation sensitive material may be a radiation curable material, in which the exposed and cured portions form the microcup structure. In an additional process step, the radiation sensitive material may be a positively working photoresist which temporarily seals the microcups. Exposure of a selected subset of the microcups via the photomask image permits selective re-opening, filling and sealing of the microcup subset. Repetition with additional colors permits the continuous assembly of a multicolor EPD or LCD display.
Owner:E INK CALIFORNIA
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