199 results about "Mask layer" patented technology

This application relates to a semiconductor structure and a method for manufacturing the same. The manufacturing method includes: providing a substrate, including a first region and a second region; forming at least two first gate structures in the first region and a second gate structure in the second region; simultaneously forming first sidewalls on the sidewalls of the first gate structures and second sidewalls on the sidewalls of the second gate structures; forming a hard mask layer; the hard mask layer covers the second sidewalls, the second gate structures, and the substrate of the second region, and at least exposes the substrate between adjacent first sidewalls; etching the substrate between adjacent first gate structures in the first region based on the hard mask layer to form sigma trenches between adjacent first gate structures; forming a silicon-germanium layer within the sigma trenches; and chemically etching to remove the hard mask layer. This application is advantageous in improving the consistency of sidewall thickness between different device regions and effectively avoiding hard mask material residue problems, thereby effectively improving device yield.

The invention provides a semiconductor structure, which comprises a plurality of magnetic tunnel junction (MTJ) elements. Seen from a top view, the MTJ elements are arranged in an array, at least one second contact structure is located in the array arranged by the MTJ elements, and at least one first mask layer covers a top surface and two sidewalls of each MTJ element, when seen from a cross-sectional view, a sidewall of the first mask layer is aligned with a sidewall of a second metal layer which is disposed below the second contact structure.

The disclosure provides a laser, a preparation method of the laser and an optical module, and relates to the technical field of optical elements, so as to meet the demand of the optical module for high-power lasers. The laser comprises the following steps: growing an etching auxiliary layer on the surface of a wafer body of the laser, the longitudinal etching rate of the wafer body is greater than the transverse etching rate of the wafer body, the transverse etching rate of the etching auxiliary layer is greater than the transverse etching rate of the wafer body, and the wafer body comprises a quantum well layer; forming a mask layer above the etching auxiliary layer, and pre-treating the mask layer to form a BH pattern; etching the BH pattern, so that the top of the wafer body is etched into a BH mesa, the etching depth is below the quantum well layer, and the etching depth is below the quantum well layer; growing a current blocking layer on both sides of the BH mesa; removing the mask layer and the etching auxiliary layer; and forming a P-InP layer on the top of the BH mesa and the current blocking layer.

A method of preparing image job data for imaging a mask layer includes receiving at least one raster image file, preparing image job data for imaging the mask layer, the preparing comprising: including data relative to the at least one raster image file in the image job data so as to image at least one corresponding image area of the mask layer, determining a non-functional area of the mask layer outside of the at least one corresponding image area; and including filling imaging data in said image job data for imaging said non-functional area.

The application provides a method for forming a semiconductor structure, comprising the following steps: providing a SiC substrate, and forming a photoresist pattern on the back surface of the substrate; forming a mask layer on the back surface of the substrate and the photoresist pattern by a first evaporation process; removing the photoresist pattern and the mask layer covering the photoresist pattern, and retaining the mask layer with a mask window, wherein the mask window corresponds to a to-be-formed-hole area of the substrate; etching the to-be-formed-hole area of the substrate along the mask window of the mask layer, and forming a back hole in the substrate. By the above arrangement, the process window capability of the back hole stripping process can be improved, and the process steps can be simplified.

The application provides a deep silicon etching method and a semiconductor process equipment, and relates to the technical field of semiconductors. The deep silicon etching method comprises a first cycle step and a second cycle step. The first cycle step and the second cycle step both comprise an etching step for etching a silicon substrate to form a groove, a removal step for removing by-products, and a deposition step for forming a protective layer on the sidewall of the groove. The protective gas used in the deposition step of the second cycle step comprises an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than that of the deposition step of the first cycle step. The deep silicon etching method can balance the etching rate of different regions of the isolation groove, optimize the depth micro-loading effect, and improve the depth consistency of the isolation groove. Meanwhile, the deposition step does not consume the mask layer, thereby reducing the consumption of the mask layer, ensuring the effective height of the mask layer, improving the morphology precision of the formed isolation groove and AA, and improving the electrical properties and yield of the product.

This invention discloses a mercury cadmium telluride infrared detector and its fabrication method. The method innovatively employs negative photoresist and a lift-off process to grow a metal mask and define contact hole patterns. This metal mask layer serves as both an ion implantation mask and a contact hole etching mask, solving the problems of implantation region positioning deviation and size mismatch in traditional processes. It enables ultra-small cell spacing, improves the detector's photoelectric performance and array uniformity, and is suitable for the large-scale fabrication of high-density infrared detector planar arrays.

The application discloses a kind of preparation methods of wafer surface metal IO pad, belong to semiconductor manufacturing technical field.The method includes the following steps: depositing barrier layer on wafer surface;Metal layer is deposited to form on barrier layer;Mask layer is deposited on metal layer;Etching forms PAD pattern;Local chemical mechanical polishing is carried out to PAD.It is optional, including: S1, wafer pretreatment: provide the semiconductor wafer that has completed front process, clean wafer surface, remove contaminant.The application is sequentially innovated by "TiN-cold AL-dielectric mask", and the low pressure, low speed Touch-up CMP designed specially for finishing appearance is combined, the roughness of aluminum layer is reduced from source, the traditional TiN etching damage is avoided, and high-quality AL PAD top height flat, four around bonding surface smooth transition appearance can be accurately obtained.The method process has strong compatibility, high stability, can significantly improve bonding reliability, and can be applied to surface improvement of other metal pad.

A method of modifying an opening in a masking material layer provided on a substrate to achieve desired critical dimensions may include forming a plurality of openings in the masking material layer, and performing one or more ion processes on the masking material layer to enlarge or reduce one or more dimensions of the plurality of openings. A first ion process of the one or more ion processes may include directionally depositing a material layer on the masking material layer by directing a material beam at a first non-zero angle relative to a normal direction extending from a top surface of the masking material layer. A second ion process of the one or more ion processes may include performing an angled ion etch by delivering an ion beam at a second non-zero angle relative to the normal direction extending from the top surface of the masking material layer.

The embodiment of the present application provides a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate; forming a first mask layer and a second mask layer on the substrate, the first mask layer extends along a first direction, the second mask layer extends along a second direction, and the first mask layer and the second mask layer are arranged to intersect; performing a cutting process on the first mask layer to form a first sub mask layer; the second mask layer crosses a plurality of first sub mask layers, and part of the sidewall of each first sub mask layer is covered by the second mask layer; using the first sub mask layer as a mask, etching the substrate by using a first etching process to form an active region; forming an isolation structure and removing the first sub mask layer which is not covered by the second mask layer; after removing part of the first sub mask layer, forming a third mask layer, and the adjacent third mask layer and the second mask layer have a first groove; etching the active region and the isolation structure along the first groove to form a word line groove. The embodiment of the present application can improve the yield of the semiconductor structure.

This invention discloses a method for manufacturing a zero-layer alignment mark, comprising the steps of: forming a zero-layer first mask layer; photolithography defining the formation area of ​​the zero-layer alignment mark; etching the zero-layer first mask layer and a semiconductor substrate to form a first trench; forming a first material layer to completely fill the first trench, wherein the first material layer and the zero-layer first mask layer are made of different materials, and the different materials of the first material layer and the semiconductor substrate result in different optical properties; performing CMP to make the top surface of the first material layer within the first trench flush with the top surface of the zero-layer first mask layer; removing the zero-layer first mask layer; and performing epitaxial growth on the surface of the semiconductor substrate outside the first material layer to form a first epitaxial layer, wherein the top surface of the first epitaxial layer is flush with the top surface of the first material layer, and the first material layer and the bottom trench together constitute the zero-layer alignment mark. This invention can maintain the good morphology of the zero-layer alignment mark and improve its contrast.

This invention provides a method for integrating low-voltage devices in a high-voltage process. The method includes: after forming gate dielectric layers for high-voltage and medium-voltage device regions, forming a front dielectric layer covering all regions; forming a mask layer covering the medium-voltage and low-voltage device regions, exposing the input / output and high-voltage device regions; removing the exposed front dielectric layer to form the gate dielectric layer for the input / output device regions; and finally forming a mask layer to expose the low-voltage device regions, removing the surface dielectric layer to form the gate dielectric layer for the low-voltage device regions. This invention protects the low-voltage device regions through a mask layer, avoiding damage and silicon loss caused by prolonged exposure of the silicon surface and repeated etching and resist removal, reducing defect introduction, improving the height difference between the active region and the shallow trench isolation structure, and enhancing the reliability of the low-voltage devices and the local uniformity of saturated leakage current.

The application provides a preparation method of a semiconductor device, and belongs to the technical field of semiconductors. The preparation method comprises the following steps: taking a third mask layer as a mask, etching a first dielectric layer by using a first etching process and stopping on a first mask layer and a second mask layer, etching the first mask layer and the second mask layer by using a second etching process with high selectivity and stopping on an anti-reflection dielectric layer, and etching the anti-reflection dielectric layer by using a third etching process with high selectivity and stopping on a second metal layer. Through step-by-step etching and etching selectivity control, a through hole is formed on metal layers with different heights at the same time, the etching amount on the first metal layer is sufficient, the second metal layer cannot be etched through, process damage is reduced, and process precision and yield are improved.

This application provides a method for manufacturing a photovoltaic metal mesh screen, comprising: forming a mask layer with a target pattern on the second surface of a metal substrate, the target pattern including a plurality of hole patterns distributed in an effective area and at least two alignment mark patterns located outside the effective area; chemically etching the second surface of the metal substrate with the mask layer as protection to form a semi-etched hole of depth D1, while simultaneously etching the alignment mark patterns into alignment through-holes penetrating the metal substrate; removing the mask layer; and aligning the semi-etched hole positions from the first surface of the metal substrate based on the alignment through-holes, and using a laser to etch the bottom of the semi-etched hole to form an etched through-hole. The manufacturing method involved in this application optimizes the time-consuming full-process laser processing into a composite process combining chemical etching roughing and laser finishing, significantly shortening the laser processing time of a single mesh screen; reducing the manufacturing cost of a single mesh screen; and achieving high process reliability and pattern accuracy.

The application provides a preparation method of a comb structure and a MEMS micro mirror, and belongs to the field of semiconductors. The preparation method of the comb structure comprises etching a substrate with a patterned mask layer as a mask to form a comb structure, the comb structure is arranged along a first direction and extends along a second direction, the first direction and the second direction intersect each other, and the plane where the first direction and the second direction are located is parallel to the substrate, the periphery of the comb structure is formed with a compensation part, the compensation part covers the end part of the comb structure extending along the second direction, and the outer sidewall of the comb structure arranged along the first direction. The application optimizes the comb structure before removing the silicon grass structure, forms a compensation part at the end part of the comb structure, thereby protecting the comb structure through the compensation part when the silicon grass structure is removed, the critical dimension of the bottom of the edge comb tooth is not too small, and the risk of breaking the edge comb tooth is avoided.

The application provides a silicon-based three-dimensional capacitor and a manufacturing method thereof. The manufacturing method comprises the following steps: preparing a dielectric mask layer on the surface of a silicon substrate, etching a plurality of spaced-apart etching micropores on the dielectric mask layer until the silicon substrate is exposed, etching the plurality of spaced-apart etching micropores by using a deep silicon etching process to form a plurality of spaced-apart first deep holes, removing the remaining dielectric mask layer, preparing a first polysilicon layer on the silicon substrate with the plurality of spaced-apart first deep holes, etching the first polysilicon layer in the first deep holes by using a deep silicon etching process to form second deep holes in the first polysilicon layer in the first deep holes, and the bottom surface and the side surface of the second deep holes are provided with the first polysilicon layer, and growing an insulating dielectric layer, a second polysilicon layer and an electrode layer on the first polysilicon layer on the surface of the first silicon substrate and in all the spaced-apart second deep holes in sequence. The silicon-based three-dimensional capacitor prepared by the application can improve the density of the capacitor.

An optical construct includes a lens layer and optically opaque first and second mask layers. The lens layer has a first main surface including a plurality of microlenses arranged along orthogonal first and second directions. The first and second mask layers are spaced apart from the first main surface and define corresponding plurality of first and second through openings arranged along the first and second directions, respectively. The first mask layer is disposed between the structured first main surface and the second mask layer. Each microlens corresponds one-to-one with both the first and second openings. The optical construct includes an intermediate layer disposed between the structured first main surface and the first mask layer, and includes a corrugated second main surface facing and substantially registered with a corrugated third main surface of the first mask layer to define a substantially uniform spacing between the second and third main surfaces.

This disclosure provides a method for forming a semiconductor structure, including forming a dielectric stack on a substrate; forming a mask layer on the dielectric stack; forming a first opening in the mask layer to expose the dielectric stack; forming a second opening in the dielectric stack to expose the substrate, wherein the second opening communicates with the first opening; forming a fill layer in the first and second openings; removing the mask layer and the fill layer to expose the sidewalls of the dielectric stack; and forming a capacitor in the second opening of the dielectric stack. Here, the profile of the capacitor is not adversely affected, and thus the structural robustness of the capacitor can be improved.

The application discloses a video training data generation method, device and program product, relates to the technical field of artificial intelligence, and aims to solve the problem of low video training data acquisition efficiency. The method comprises the following steps: acquiring multi-modal input data of operation training in a target operation scene; and generating simulated video data of the operation training in the target operation scene with multi-modal labeled data based on the multi-modal input data and a pre-trained generative world model. The generative world model comprises a multi-modal encoding layer, a multi-modal feature fusion layer, a cross attention layer, a multi-layer perception (MLP) module, an action adaptation module, a multi-modal decoding layer, a feature-label association layer and a multi-modal output layer. The cross attention layer comprises a rotation position encoding (RoPE) module, a self-defined rule mask layer and a causal mask layer.

The embodiment of the present disclosure relates to the field of semiconductor, and provides a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate, a first dielectric layer, a second dielectric layer and a mask layer which are sequentially stacked, the material of the first dielectric layer is different from the material of the second dielectric layer, the substrate has a plurality of discrete landing pads, and the mask layer has a plurality of openings penetrating the mask layer; etching the second dielectric layer and the first dielectric layer along the openings with the mask layer as a mask until the landing pads are exposed, thereby forming a plurality of first through holes penetrating the second dielectric layer and the first dielectric layer, and each first through hole exposes a corresponding landing pad; forming a lower electrode film which at least fills the openings and the first through holes; removing the mask layer and the lower electrode film higher than the top surface of the second dielectric layer, and the remaining lower electrode film serves as a lower electrode layer. At least the etching defects of the semiconductor structure can be reduced.

The application discloses a method for improving overlay accuracy, and relates to the technical field of semiconductors, and comprises the following steps: setting overlay accuracy marks in each alignment mark area of a mask layer; calculating an overlay adjustment amount corresponding to the mask layer by a wafer pre-alignment system; the overlay adjustment amount is obtained by calculating based on measurement parameters of wafer exposure; the measurement parameters comprise symmetry and asymmetry rotation parameters and expansion parameters of an exposure unit in each direction, and the overlay adjustment amount comprises false compensation calculated by a machine table due to deformation of adjacent layer exposure areas; calculating a pre-compensation amount of the mask layer based on the set overlay accuracy marks and the measurement parameters; the pre-compensation amount is used for eliminating the false compensation in the overlay adjustment amount; and calculating an overlay adjustment value of a next exposure process based on the overlay adjustment amount and the pre-compensation amount. According to the scheme, the false compensation caused by differences between front and rear layers due to exposure is subtracted from the overlay adjustment amount output by the original wafer pre-compensation system, and the overlay accuracy is improved.

This application provides a method for avoiding slit defects in mask patterns during self-aligned dual-patterning processes, comprising: Step 1, providing a substrate, and sequentially forming an interlayer dielectric layer, an anti-reflection coating, a titanium nitride layer, a TEOS layer, and a patterned sacrificial layer on the substrate; Step 2, forming a mask layer within the gaps between the patterned sacrificial layers; Step 3, after removing the patterned sacrificial layers, performing a first etching using the mask layer as a mask until the exposed TEOS layer is removed, wherein the mask layer is not etched through during the first etching process; Step 4, performing a second etching using the TEOS layer as a mask until the exposed titanium nitride layer is removed, thereby forming the mask pattern. According to this application, the generation of slit defects can be effectively avoided, while simultaneously expanding the CD window (distance between lithographic patterns).

The application provides a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor substrate, wherein a first gate structure is formed on the semiconductor substrate; forming a hard mask layer to form a first sidewall layer and a recess; forming a filling layer in the recess, wherein a gap exists between the part of the filling layer which is higher than the semiconductor substrate and the first sidewall layer; forming a second sidewall material, wherein the second sidewall material fills the gap, and the material of the second sidewall material is silicon oxide; removing part of the thickness of the second sidewall material; forming a third sidewall material, wherein the third sidewall material covers the second sidewall material, and the material of the third sidewall material is silicon nitride; etching the second sidewall material and the third sidewall material to form a second sidewall layer and a third sidewall layer. In this way, the sidewall material with a small dielectric constant is filled into the gap between the filling layer and the gate sidewall, so that the capacitance value of the gate-contact hole (CGC) is reduced, and the device performance is improved.

Non-printing indicia on a plate formed in part or in whole from microstructures formed via exposure through openings in a masking layer form elevated or sunken structures that represent one or more alphanumeric signs, digital codes, or alignment marks. An isolated micro alignment mark may be used in conjunction with a ring of LEDs to show alignment by a characteristic illumination pattern to a high degree of accuracy. Non-printing indicia may be derived from imaging a plurality of supercells defined by a plurality of exposed pixels and unexposed pixels disposed within each supercell boundary. Each supercell may have a first number of exposed pixel clusters, each cluster having a second number of exposed pixels, adjacent clusters spaced apart by a third number of unexposed pixels, and a padding between the supercell boundary and a closest exposed pixel cluster defining a fourth number of unexposed pixels.

The application provides a processing method of a bonding substrate, a layout structure and a packaging method. A pattern structure of an alignment mark and a pattern structure of a bonding limiting piece are simultaneously formed in a first mask layer, and the alignment mark and the bonding limiting piece are simultaneously formed by using a same etching process, which is equivalent to omitting a processing flow of the bonding limiting piece, reduces process steps and is beneficial to reducing processing cost. Moreover, the bonding limiting piece is arranged in a cutting path area, and does not need to additionally occupy space of a chip area, so that effective reduction of a chip area is realized. In addition, when bonding packaging is performed, the existence of the bonding limiting piece can effectively control the extrusion degree of the substrate, avoids the situation that the bonding material is largely extruded due to over-extrusion, and guarantees the reliability of chip packaging.

The application provides a surface plasmon photolithography device and a preparation method for improving imaging aspect ratio, which can be applied to the fields of integrated circuit manufacturing and photolithography technology. The surface plasmon photolithography device comprises a metal reflection layer, an optical metamaterial photoresist layer and a mask layer which are sequentially stacked from bottom to top; wherein the optical metamaterial photoresist layer comprises a photoresist and a metal nanoparticle array embedded in the photoresist, the metal nanoparticle array comprises at least one metal nanoparticle layer, and the metal nanoparticle layer is composed of metal nanoparticles arranged periodically; the metal nanoparticle layer is arranged in parallel to the mask layer, wherein when the metal nanoparticle layer comprises a plurality of metal nanoparticle layers, the different metal nanoparticle layers are located in different planes. The application further provides a preparation method of the surface plasmon photolithography device for improving imaging aspect ratio.

The application relates to an etching method of a contact hole and a manufacturing method of a DRAM, and belongs to the technical field of semiconductors. The application solves the problems that the existing HARC etching formula only has a time etching step and does not have an EPD etching step, and the wavelength signal emitted during etching of the contact hole is too small to cause the EPD etching to be ineffective. The etching method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is formed with a conductive component; sequentially forming, from bottom to top, an etching stop layer, a layer to be etched, a first mask layer and a second mask layer above the semiconductor substrate; performing a photoetching process on the second mask layer to form a second mask layer pattern; transferring the second mask layer pattern to the first mask layer to form a first mask layer pattern; and taking the first mask layer pattern as a mask, etching the layer to be etched and the etching stop layer to form a contact hole and expose the conductive component, wherein endpoint detection EPD is adopted in etching of the layer to be etched. The HARC etching menu is realized by improving the EPD etching, and technical prejudice is overcome.

A method of fabricating a semiconductor device is disclosed. The method may include forming an etch-target layer, a mask layer, a blocking layer, and a photoresist layer, which are sequentially stacked on a substrate; forming a photoresist pattern, the forming the photoresist pattern including irradiating the photoresist layer with extreme ultraviolet (EUV) light; forming a mask layer, the forming the mask layer including etching the mask layer using the photoresist pattern as an etch mask; and forming a target pattern, the forming the target pattern including etching the etch-target layer using the mask pattern as an etch mask. The photoresist layer may include an organic metal oxide. The blocking layer may be a non-polar layer and may limit and / or prevent a metallic element in the photoresist layer from infiltrating into the mask layer.