1544 results about "Mask layer" patented technology

The invention relates to the technical field of image detection, in particular to an inorganic mineral casting detection method based on image processing, and the method comprises the following steps: obtaining an image sequence, carrying out the gray scanning, extracting a connected region, screening a closed image block, generating a candidate, building an edge path, analyzing a position change, correcting a contour, and generating a track image; evaluating the direction distribution labeling consistency to generate a mask layer, extracting a feature judgment category to generate a labeling image, and analyzing an angle difference to identify an interruption calibration position to generate a labeling layer. According to the method, the integrity of target area screening is enhanced through gray abrupt change and connected path extraction in the image sequence, spatial offset interference is eliminated through boundary trajectory stability analysis, the area judgment consistency is improved, directional discrete areas are accurately recognized through standard deviation evaluation of the pixel gradient direction, and the attribution judgment accuracy is improved; according to boundary disturbance analysis, abnormal edge expression is refined, and the image sequence information coherence utilization and abnormal feature distinguishing capability is enhanced.

The invention discloses a manufacturing method of a groove, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate, forming a first mask layer on the substrate, and etching the first mask layer by taking a photomask as a mask, so that the first mask layer covers the substrate of a first groove region, forming a second mask layer on the substrate, etching the second mask layer to enable the second mask layer to expose the first mask layer and the substrate in the second groove region, etching the substrate in the second groove region by taking the first mask layer and the second mask layer as masks to form a relatively shallow second groove, and etching the first mask layer to form a relatively shallow second groove; according to the method, the substrate of the first trench region and the substrate of the second trench region are exposed by the second mask layer, and the substrate of the first trench region and the substrate of the second trench region are etched by taking the second mask layer as a mask to form a deeper second trench and a shallower first trench, so that a shallow trench and a deep trench can be manufactured by adopting one photomask, and the manufacturing cost can be further reduced.

The invention relates to the technical field of semiconductors, in particular to a device integrated with a deep trench isolation structure and a preparation method of the device. The preparation method comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a substrate, a gate material layer stacked on the surface of the substrate and a mask layer stacked on the gate material layer, and a functional element of the semiconductor device is formed in the substrate; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates through the mask layer and the gate material layer and goes deep into the substrate; the deep trench is filled to form a deep trench isolation structure, the deep trench isolation structure comprises a filling structure, the filling structure is not higher than the surface of the substrate, and the material of the filling structure is a conductive non-metal material; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. According to the invention, the preparation process of the deep trench isolation structure can be integrated into the standard process for preparing the gate structure of devices such as a BCD, the integration process of deep trench isolation is simplified, and the preparation cost is reduced.

The present disclosure relates to the technical field of back-contact cells, and in particular, to a preparation method for a hybrid passivated back-contact cell with partial mask layer removed, comprising the following steps: S1, providing a double-sided polished silicon wafer; S2, sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer obtained in S1; S3, performing first etching on the first semiconductor layer to form second semiconductor opening areas spaced apart; S4, texturing and cleaning; S5, removing part of the mask layer to reduce the thickness D of the mask layer formed in S2; S6, forming a second semiconductor layer on the back surface obtained in S5; and S7, using laser to perform second etching on a polished area on the back surface of the silicon wafer obtained in S6, to form first semiconductor opening areas. According to the present disclosure, by removing partial thickness of the mask layer, the adhesion between the mask layer and the second semiconductor layer can be enhanced, and the passivation effect of the second semiconductor layer is improved, thereby improving the cell yield and the cell conversion efficiency; moreover, the process steps are simplified, reducing the device cost.

The invention belongs to the technical field of semiconductors, and discloses a method for manufacturing a sigma trench in a semiconductor device, which comprises the following steps of: providing a substrate which comprises a first device region and a second device region; a PMOS (P-channel Metal Oxide Semiconductor) region gate and a PMOS gate mask layer are formed on the first active region of the first device region; exposing the top of the PMOS gate mask layer outside the first device region photoresist layer; depositing a deposition silicon oxide layer on the top of the second device region and the top of the PMOS gate mask layer; removing the photoresist layer in the first device region; etching to remove the natural silicon oxide layer on the surface of the first active region, further etching silicon in the first active region, and forming a U-shaped groove in the semiconductor substrate in the first device region; and carrying out TMAH etching on the U-shaped groove to form a sigma groove. According to the invention, in the process of embedding germanium-silicon into the source and the drain, the height difference between the PMOS and the NMOS is avoided, and the subsequent process is not influenced.

The invention provides a patterned photonic crystal laser and a preparation method thereof, the laser comprises a substrate, and a first mask layer, a photonic crystal layer and a second mask layer which are sequentially deposited on the substrate, a light emitting area is etched in the central area of the second mask layer, and transparent conductive layers are deposited on the surface of the second mask layer and the light emitting area; a p-annular electrode is arranged on the surface of the transparent conductive layer on the second mask layer, and an n-annular electrode is arranged below the substrate; the photonic crystal layer is composed of a nanorod array and a polymer filled in gaps of nanorods; holes distributed in a patterned array are etched in the surface of the first mask layer, and nanorods are epitaxially grown in hole areas; the nanorod is formed by sequentially depositing a substrate contact layer, a first waveguide layer, a multi-quantum well layer, a second waveguide layer, a coating layer and a component gradient layer. According to the invention, through collaborative design optimization of all the layers, emission of laser with specific wavelength and preparation of a laser emitting laser with single longitudinal mode, narrow linewidth and stable wavelength are realized.

The invention relates to the technical field of semiconductor manufacturing, and discloses a tungsten oxide etching method, a semiconductor structure and a chip, and the method comprises the steps: forming a tungsten oxide thin film on a substrate; forming a mask layer with a target pattern on the tungsten oxide thin film; etching the tungsten oxide thin film with the mask layer by adopting mixed gas in ICP etching equipment; in the ICP etching equipment, the mixed gas comprises trifluoromethane and argon, the ratio range of the trifluoromethane in the mixed gas is 22.5%-74.1%, the flow rate of the mixed gas is 135-155 sccm, the ratio range of ICP power to bias power is 1.53: 1-3.3: 1, the depth-to-width ratio range of the tungsten oxide etching structure is 10: 1-23: 1, the inclination angle of the side wall of the tungsten oxide etching structure is 40-90 degrees, and the width of the tungsten oxide etching structure is 20-30 degrees. The technical problem that it is difficult to achieve a tungsten oxide etching structure with the nanoscale line width and the high aspect ratio in the prior art is solved.

The embodiment of the invention relates to the photovoltaic field, and provides a back contact solar cell, a preparation method thereof and a photovoltaic module, and the method comprises the steps: providing a substrate which comprises a front surface and a back surface which are opposite to each other, and the back surface comprises a first region and a non-first region; sequentially stacking a first doped conductive layer and a first mask layer on the back surface of the substrate, and removing the first mask layer corresponding to a non-first region through laser; at least removing the first doped conductive layer corresponding to the non-first region, wherein the remaining first doped conductive layer forms a first emitter; a second doped conductive layer and a second mask layer are sequentially stacked on the side, away from the first emitting electrode, of the remaining first mask layer and the non-first region, and materials of the first mask layer and the second mask layer independently comprise at least one of amorphous silicon, nanocrystalline silicon and silicon carbide; at least removing the second mask layer corresponding to the first region through laser; and at least removing the second doped conductive layer corresponding to the first region, wherein the remaining second doped conductive layer forms a second emitter.

The invention discloses an ionosphere super-resolution refining reconstruction method, device and equipment based on an improved ViT model and a storage medium, and relates to the technical field of ionosphere modeling, and the method comprises the steps: obtaining the TEC data and VTEC data of an ionosphere in a to-be-detected time period; taking the ionized layer TEC data as a low-resolution image, taking the VTEC data as a pixel true value, and generating a mask layer according to whether the pixel true value comprises an observation value or not; combining the low-resolution image, the pixel true value and the mask layer to obtain a multi-channel tensor; and taking the multi-channel tensor as input, and obtaining a global ionosphere map based on output of the improved ViT model. ViT is applied to super-resolution reconstruction of the ionosphere, dependence on the number of ground sites can be effectively reduced, the defect that the image is excessively smooth is overcome, meanwhile, the spatial resolution of the ionosphere image can be improved, and then the precision of an ionosphere model is improved.

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system, and the manufacturing method of a semiconductor structure comprises the steps: forming a first mask layer on a substrate, and forming a plurality of first openings in the first mask layer side by side; etching the substrate for the first time based on the plurality of first openings to form a plurality of first grooves arranged side by side; expanding the plurality of first openings, wherein the expanded plurality of first openings form a plurality of second openings; filling the plurality of first grooves and the plurality of second openings to form a plurality of filling structures arranged side by side; removing the first mask layer between the adjacent filling structures to form a third opening; and etching the substrate for the second time based on the third opening to form a second groove.

The invention provides a semiconductor structure and a forming method thereof. The forming method comprises the following steps: forming a stacked film layer on a substrate; forming a mask layer on the stacked film layer, wherein the mask layer comprises a mask opening; forming a spacer layer on the side wall of the mask opening; etching the stacked film layer and the substrate by taking the mask layer and the spacing layer as masks so as to form a first groove in the stacked film layer, and forming a first groove in the substrate; performing an etching process to reduce the thickness of the first semiconductor layer and respectively form a second trench and a second groove in the stacked film layer and the substrate, and forming a protection layer in the second groove; wherein in the first direction, the width of the second groove is larger than that of the first groove, and the width of the second groove is larger than that of the first groove. According to the forming method, the protection material layer can be prevented from remaining, and the stability of the performance of the formed device is improved.

To provide an analysis element and a manufacturing method thereof that can prevent an object to be analyzed from being unable to be analyzed appropriately.SOLUTION: A manufacturing method of this analysis element 100 includes the steps of forming a mask layer 20, forming a membrane layer 30, exposing a substrate 10, forming an introduction hole 13 and forming a protrusion 14 at the inlet end 13a of the introduction hole 13, and removing the protrusion 14 by wet etching the protrusion 14.SELECTED DRAWING: Figure 13

A method of manufacturing a structure having anodized parts includes: forming a bottom metal pattern with a dielectric layer thereon on a substrate, in which the dielectric layer has an opening exposing the bottom metal pattern; forming a semiconductor layer to cover the dielectric layer; forming a first metal layer on the semiconductor layer; forming a second metal layer on the first metal layer; forming a mask layer on the second metal layer to expose a portion of a top surface of the second metal layer; etching the second metal layer through the mask layer until a top surface of the first metal layer is exposed, in which an etch selectivity of the second metal layer and the first metal layer is greater than 2.0; anodizing the first metal layer through the mask layer to form an anodized segment; and removing the mask layer.

The invention discloses a cue word optimization method, a cue word optimization system, cue word optimization equipment and a cue word optimization medium for video generation. The cue word optimization method specifically comprises the following steps: guiding a user to draw a motion diagram containing a dynamic mask layer and a motion trail vector layer in an image editing interface; performing spatial matching on the verb elements and the motion trail, and generating a contradictory region thermodynamic diagram in combination with an attention mechanism; when it is detected that a conflict area exists in the conflict area thermodynamic diagram, intention analysis is carried out through a reinforcement learning strategy, and a multi-dimensional optimization scheme is generated; and performing iterative verification on the corrected motion diagrams, and if the verification is passed, inputting the initial image and the multiple groups of motion diagrams into a multi-modal large language model to generate final cue words containing scene adaptation parameters. According to the invention, through integration of multi-source information such as images, semantic texts and motion diagrams and combination of technologies such as space matching, reinforcement learning and physical model analysis, accurate cue words containing scene adaptation parameters are generated, and the quality and precision of video generation are significantly improved.

A method for forming a high aspect ratio (HAR) structure during a HAR etch process, the method comprises sequentially or simultaneously exposing the substrate to a vapor of an etchant including one or more hydrofluorocarbon or fluorocarbon compounds or one or more hydrogen-containing molecules and an additive compound, the substrate having a film disposed thereon and a patterned mask layer disposed on the film; activating a plasma to produce activated one or more hydrofluorocarbon or fluorocarbon compounds or activated one or more hydrogen-containing molecules and an activated additive compound; and allowing an etching reaction to proceed between the film uncovered by the patterned mask layer and the activated hydrofluorocarbon or fluorocarbon compounds or the activated one or more hydrogen-containing molecules and the activated additive compound to selectively etch the film from the patterned mask layer, thereby forming the HAR patterned structure.

The invention provides a surface-emitting gallium nitride VCSEL laser chip and an epitaxial defect suppression preparation method thereof, and relates to the technical field of laser chips, the surface-emitting gallium nitride VCSEL laser chip comprises a substrate, a low-temperature nucleating layer, a high-temperature recovery layer, a stress regulation type nano mask composite defect blocking layer, an n-type nitride DBR reflector, an active region, a polarization enhanced tunnel junction and the like, the defect blocking layer adopts an in-situ silicon nitride nano-porous mask layer to be matched with an aluminum gallium nitride / gallium nitride stress compensation superlattice layer, through pulse type lateral epitaxial overgrowth annihilation penetrating dislocation, and the n-type nitride DBR reflector adopts an AlInN / GaN lattice matching material system to be combined with a hydrogen etching interruption modification technology, so that thick film growth with zero cracks and high reflectivity is realized; a polarization enhanced tunneling junction is used at the top to replace ITO, and the hole tunneling probability is enhanced by piezoelectric polarization in InGaN, so that efficient current injection with low working voltage and no absorption loss is realized, the dislocation density and the device voltage are remarkably reduced, and the yield of an epitaxial wafer and the photoelectric conversion efficiency are improved.

The invention provides a method for forming a groove and semiconductor process equipment. The method comprises the following steps: providing a film layer to be etched; the to-be-etched film layer comprises a substrate and a mask layer located on the surface of one side of the substrate, the mask layer is provided with a mask opening, and the mask opening exposes a partial region of the substrate; introducing etching gas into the process chamber to excite the etching gas to generate plasma; loading N pieces of lower electrode power to the lower electrode of the process chamber in sequence to enable the plasma to etch the exposed area of the substrate to form a target groove; wherein the power of the N lower electrodes increases progressively, and N is an integer greater than or equal to 2. By adopting the method provided by the invention, the target groove with good side wall morphology and high aspect ratio can be obtained.

Techniques and systems are provided for image generation. For instance, a process can include rendering an image of a scene, the scene including a first virtual object associated with a first physical object that moves independently of the scene, identifying a first set of pixels associated with the first virtual object in the image of the scene, generating a mask layer based on the first set of pixels, the mask layer indicating locations of the first set of pixels in the image, and transmitting the mask layer and the image to a display.

A manufacturing method for a semiconductor device. The method comprises: forming a first carbon film (103) on a semiconductor substrate to serve as a mask layer; using a silicon-containing photoresist material to form a patterned photoresist layer (104) on the first carbon film (103); etching the first carbon film (103) using the patterned photoresist layer (104) as a mask; and after a corresponding pattern is transferred onto the first carbon film (103), carbonizing the photoresist layer (104), so as to convert the photoresist layer (104) into a second carbon film (105).

The invention provides a manufacturing method of a sigma trench, which comprises the following steps: providing a substrate, forming a gate oxide layer and a gate structure on the substrate, the gate structure comprising a gate, a first mask layer and a second mask layer which are sequentially formed on the gate oxide layer; etching for the first time by taking the second mask layer as a mask until the second mask layer is removed, forming a first groove in the substrate on two sides of the gate structure, and gathering polymers generated by etching the second mask layer in the etching process on the gate oxide layer on the side wall of the first groove and a junction area of the gate oxide layer, the gate and the substrate as an etching protection layer; and performing second etching by taking the first mask layer as a mask, protecting the substrate covered by the etching protection layer from lateral etching by the etching protection layer, and forming a sigma-like groove in the first groove. According to the method, the etching protection layer is formed on the side wall of the first groove through the polymer generated by the second mask layer in the first etching process, the area is prevented from being excessively etched, serious lateral pushing of the area is avoided, and therefore the shape of the groove can be adjusted and controlled more easily.

A method for forming an interconnection structure for a semiconductor device and an interconnection structure is disclosed. The method includes forming a conductive layer on an insulating layer and etching the conductive layer to form a first conductive line. Thereafter, a spacer is formed on a side wall of a first end portion of the first conductive line. The method further includes forming a second conductive line, parallel to the first conductive line, having a second end portion, wherein a side wall of the second end portion is arranged to abut the spacer such that the first and the second metal line are extending along the same line and separated by the spacer. A recess is formed in the second metal line, extending along a portion of the second metal line, and a second mask layer is arranged in the recess.

The invention relates to a solar cell and a manufacturing method thereof, and a photovoltaic module, and the manufacturing method comprises the steps: providing a substrate, a first surface comprises first regions and non-first regions which are alternately disposed in a first direction, the non-first regions comprise interval regions and second regions, and the interval regions are located between the adjacent first regions and second regions; forming a first mask layer on the first surface, and at least removing the first mask layer corresponding to the first region; a first passivation contact layer is formed on the first area and the side, away from the second surface, of the first mask layer, at least the first passivation contact layer and the first mask layer corresponding to the non-first area are removed, the first area and the second area are located on the same first plane, and the first plane is parallel to the plane where the substrate is located; and forming a second passivation contact layer on the first passivation contact layer and one side, far away from the second surface, of the non-first region, and at least removing the second passivation contact layer corresponding to the first region and the spacer region. The performance of the solar cell can be improved.

The invention discloses a chip-embedded TGV glass substrate and a manufacturing method thereof. The method comprises the following steps: providing a glass core plate; forming a temporary metal mask layer on the first surface of the glass core plate; performing pattern transfer and etching on the temporary metal mask layer; performing dry etching on the glass core plate in the second pattern area to form a first TGV hole; etching the glass core plate in the first pattern area and the second pattern area through a dry method to form a second TGV hole and deepen the depth of the first TGV hole; removing the temporary metal mask layer, performing metallization to form a first conductive through hole and a second conductive through hole, and manufacturing a first rewiring layer; grinding the second surface of the glass core plate until the first conductive through hole is exposed; etching the glass core plate through a dry method to form a cavity until the second conductive through hole is exposed; providing a chip, and embedding the chip into the cavity; therefore, no-damage cavity processing is realized, and the problems of surface damage, dimensional deviation, lateral erosion, microcracks or surface roughening and the like of the substrate are effectively avoided.

The invention discloses an image sensor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The image sensor comprises a substrate which is divided into a plurality of active regions by a shallow trench isolation structure; the photodiode, the charge storage region and the floating diffusion region are arranged in the substrate at intervals; the global transmission grid is arranged between the photodiode and the charge storage region and comprises a first branch arranged on the active region and a second branch arranged on the shallow trench isolation structure; the transfer gate is arranged between the charge storage region and the floating diffusion region and comprises a first gate arranged on the active region and a second gate arranged on the shallow trench isolation structure; the first mask layer is arranged on the global transmission gate and the transfer gate, and the second mask layer is arranged on the first mask layer on the first branch and the first gate; the shading structure covers the first subsection, the charge storage area and part of the transfer grid electrode. According to the image sensor and the manufacturing method thereof, the parasitic light response is improved, and the manufacturing yield is improved.

The invention relates to the technical field of agricultural unmanned aerial vehicle data processing, in particular to an agricultural unmanned aerial vehicle pod sensor data processing method and system which are used for correcting image data abnormity caused by spraying operation. Synchronously acquiring image data acquired by an optical sensor and vibration data acquired by a vibration sensor and generated by the spraying system during working; determining a characteristic vibration frequency according to the vibration data, and performing frequency domain filtering processing on the image data based on the characteristic vibration frequency to generate intermediate image data of which the vibration blur is eliminated; by synchronously acquiring the image and the vibration data, correcting the vibration blur by using the vibration data, identifying and confirming the lens liquid drop by using the spectral characteristics and the position fixity, and generating the mask layer to shield the liquid drop area, the problems of missed judgment and misjudgment of the liquid drop as a disease caused by the vibration blur are solved.

The invention relates to the technical field of photoelectric device manufacturing, in particular to an inverted-structure Micro-LED device and a preparation method thereof. Comprising the following steps: S1, acquiring a substrate, and forming a mesa structure on the upper surface of the substrate; s2, forming a p electrode structure on the mesa structure, and forming an n electrode structure on the substrate at a position spaced from the mesa structure; s3, coating a photoresist; s4, carrying out exposure treatment, and carrying out drying treatment and developing treatment on the exposed substrate; s5, carrying out multiple times of etching treatment on the substrate, and after each time of etching treatment is completed, carrying out cooling treatment on the substrate so as to form a conical structure on the substrate; and S6, removing the mask layer, and inversely connecting the substrate to the PCB substrate through the p electrode structure and the n electrode structure to obtain the device. The light beam is totally reflected for multiple times in the conical structure, so that the divergence angle of the light beam is obviously reduced, and the light emitting angle of the device is obviously reduced.

The present application relates to a method of providing a deposition mask, a method of providing a display panel and a deposition mask. The method of providing a mask comprises: providing a first mask layer facing a second mask layer; in the second mask layer, providing a first opening corresponding to a deposition opening of the mask; providing an auxiliary layer, the auxiliary layer facing the first mask layer and the second mask layer being located therebetween and covering the first opening; in the auxiliary layer, providing a second opening corresponding to the first opening and exposing the first mask layer to outside the auxiliary layer; in the first mask layer, by using the auxiliary layer as a mask, providing a third opening corresponding to the first opening and the second opening; and separating the auxiliary layer from the first mask layer and the second mask layer to provide a deposition mask having the first mask layer containing the third opening and the second mask layer containing the first opening.

The invention provides a multi-target person image face replacement and skin color coordination method and system, and relates to the technical field of artificial intelligence image processing, and the method comprises the steps: receiving a source face image and a target image sequence containing a plurality of target persons; performing character detection on each target image, and retaining a character detection frame of which the confidence is higher than a threshold value; cutting the figure area based on the detection frame and expanding pixel redundancy to form an expanded cut image including a head and an adjacent skin area; zooming all the expanded and cut images to a uniform resolution ratio and then splicing the expanded and cut images into an optimized long image; and performing semantic segmentation on the optimized long graph, generating a multi-layer mask comprising a core mask layer, an extension mask layer and a coordination mask layer, and performing adaptive edge processing. Through a preprocessing strategy, multi-layer mask control, a style guiding mechanism and a skin color and illumination coordination technology, the quality, efficiency and practicability of a face changing result are improved.

The invention provides a low-driving-voltage trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, performing ion implantation, and forming a masking layer, a P-type well region, a P-type base region, a P-type source region and an N-type source region; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the N-type source region, metal is deposited, and a source electrode metal layer is formed; re-forming a barrier layer, etching the barrier layer to form a through hole, etching the drift layer to the upper side surface of the masking layer, and depositing to form an insulating dielectric layer; and forming a barrier layer again, etching the barrier layer to form a through hole, etching the insulating dielectric layer to form a groove, depositing metal, forming a gate metal layer, removing the barrier layer, completing preparation, reducing the driving voltage of the device, and reducing the driving loss of the device. The device reliability is improved.

A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming a first sacrificial layer and a second sacrificial layer; forming a first mask layer and a second mask layer, wherein the first mask layer covers the first sacrificial layer, the second mask layer covers the second sacrificial layer; forming a first width controlling element on a lateral surface of the first mask layer and a second width controlling element on a lateral surface of the second mask layer; removing the first mask layer and the second mask layer; and patterning the metallization layer to form a first word line between the first sacrificial layer and the second sacrificial layer, wherein a dimension of the first word line depends on a dimension of the first width controlling element.