1911 results about "Mask layer" patented technology

The invention relates to the technical field of image detection, in particular to an inorganic mineral casting detection method based on image processing, and the method comprises the following steps: obtaining an image sequence, carrying out the gray scanning, extracting a connected region, screening a closed image block, generating a candidate, building an edge path, analyzing a position change, correcting a contour, and generating a track image; evaluating the direction distribution labeling consistency to generate a mask layer, extracting a feature judgment category to generate a labeling image, and analyzing an angle difference to identify an interruption calibration position to generate a labeling layer. According to the method, the integrity of target area screening is enhanced through gray abrupt change and connected path extraction in the image sequence, spatial offset interference is eliminated through boundary trajectory stability analysis, the area judgment consistency is improved, directional discrete areas are accurately recognized through standard deviation evaluation of the pixel gradient direction, and the attribution judgment accuracy is improved; according to boundary disturbance analysis, abnormal edge expression is refined, and the image sequence information coherence utilization and abnormal feature distinguishing capability is enhanced.

The invention discloses a manufacturing method of a groove, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate, forming a first mask layer on the substrate, and etching the first mask layer by taking a photomask as a mask, so that the first mask layer covers the substrate of a first groove region, forming a second mask layer on the substrate, etching the second mask layer to enable the second mask layer to expose the first mask layer and the substrate in the second groove region, etching the substrate in the second groove region by taking the first mask layer and the second mask layer as masks to form a relatively shallow second groove, and etching the first mask layer to form a relatively shallow second groove; according to the method, the substrate of the first trench region and the substrate of the second trench region are exposed by the second mask layer, and the substrate of the first trench region and the substrate of the second trench region are etched by taking the second mask layer as a mask to form a deeper second trench and a shallower first trench, so that a shallow trench and a deep trench can be manufactured by adopting one photomask, and the manufacturing cost can be further reduced.

The invention discloses a preparation method of a solar cell and the solar cell, and belongs to the photovoltaic field. The preparation method of the solar cell comprises the following steps: forming an alkali-resistant film layer on the front surface of a silicon substrate; forming a first tunneling layer and a first doping layer on the back surface of the silicon substrate; removing the first doping layer, the first tunneling layer and a part of the silicon substrate outside the first region; forming a second tunneling layer and a second doping layer on the back surface, wherein the doping types of the second doping layer and the first doping layer are opposite; removing the second doping layer, the second tunneling layer and a part of the silicon substrate outside the second region; removing the mask layer; and forming a first electrode in contact with the first doped layer in the first region, and forming a second electrode in contact with the second doped layer in the second region. According to the invention, the mask layer protects the front surface in the subsequent polishing process and the like, so that a thinner original silicon wafer can be selected, the two doping layers can be accurately divided and isolated on the back surface, and the purposes of reducing the cost, improving the process yield and improving the cell performance are achieved.

The invention provides a germanium-silicon groove preparation method, which comprises the following steps of: forming a PMOS (P-channel Metal Oxide Semiconductor) gate structure and an NMOS (N-channel Metal Oxide Semiconductor) gate structure on a semiconductor substrate, arranging a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer in hard mask layers of the PMOS gate structure and the NMOS gate structure, exposing the second silicon nitride layer through a gate side wall, and covering a germanium-silicon mask layer, a patterned photoresist protection NMOS gate structure is formed, the germanium-silicon mask layer exposed in the PMOS region is etched, a groove is formed, and at least part of the second silicon nitride layer is reserved at the top of the PMOS gate to protect the silicon oxide layer; according to the method, the first silicon nitride layer and the germanium-silicon mask layer are etched, germanium-silicon deposition is carried out, and the residual second silicon nitride layer and the germanium-silicon mask layer are removed together through wet etching, so that the height difference of the hard mask layer caused by the conventional process of the PMOS gate and the NMOS gate is eliminated, the process load is avoided, the process steps are simplified, and the process cost is reduced.

The invention relates to the technical field of semiconductors, in particular to a device integrated with a deep trench isolation structure and a preparation method of the device. The preparation method comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a substrate, a gate material layer stacked on the surface of the substrate and a mask layer stacked on the gate material layer, and a functional element of the semiconductor device is formed in the substrate; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates through the mask layer and the gate material layer and goes deep into the substrate; the deep trench is filled to form a deep trench isolation structure, the deep trench isolation structure comprises a filling structure, the filling structure is not higher than the surface of the substrate, and the material of the filling structure is a conductive non-metal material; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. According to the invention, the preparation process of the deep trench isolation structure can be integrated into the standard process for preparing the gate structure of devices such as a BCD, the integration process of deep trench isolation is simplified, and the preparation cost is reduced.

The invention discloses a method for improving the micro LED mesa morphology by using multilayer masks and segmented etching, and belongs to the technical field of semiconductor processing technologies. The method comprises the following steps: firstly, depositing a SiO2 mask layer on the surface of an epitaxial layer, and then obtaining a photoresist through hole structure through spin coating, exposure and development; then, a chromium metal film layer is deposited and then lifted away from the photoresist, and a patterned chromium metal film layer is prepared; taking the patterned chromium metal film layer as a mask, and etching to prepare a patterned SiO2 mask layer; etching the patterned chromium metal film layer and the upper region of the epitaxial layer by using an etching gas with a high Cl2 / BCl3 flow ratio, and etching the patterned SiO2 mask layer and the lower region of the epitaxial layer by using an etching gas with a low Cl2 / BCl3 flow ratio; by adjusting the time of the two etching processes and the flow parameters of the etching gas, the time point when the chromium metal film layer is consumed can be controlled, and the effects of controlling the up-down diameter of the table top and controlling the etching angle are achieved.

The present disclosure relates to the technical field of back-contact cells, and in particular, to a preparation method for a hybrid passivated back-contact cell with partial mask layer removed, comprising the following steps: S1, providing a double-sided polished silicon wafer; S2, sequentially forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer obtained in S1; S3, performing first etching on the first semiconductor layer to form second semiconductor opening areas spaced apart; S4, texturing and cleaning; S5, removing part of the mask layer to reduce the thickness D of the mask layer formed in S2; S6, forming a second semiconductor layer on the back surface obtained in S5; and S7, using laser to perform second etching on a polished area on the back surface of the silicon wafer obtained in S6, to form first semiconductor opening areas. According to the present disclosure, by removing partial thickness of the mask layer, the adhesion between the mask layer and the second semiconductor layer can be enhanced, and the passivation effect of the second semiconductor layer is improved, thereby improving the cell yield and the cell conversion efficiency; moreover, the process steps are simplified, reducing the device cost.

The invention belongs to the technical field of semiconductors, and discloses a method for manufacturing a sigma trench in a semiconductor device, which comprises the following steps of: providing a substrate which comprises a first device region and a second device region; a PMOS (P-channel Metal Oxide Semiconductor) region gate and a PMOS gate mask layer are formed on the first active region of the first device region; exposing the top of the PMOS gate mask layer outside the first device region photoresist layer; depositing a deposition silicon oxide layer on the top of the second device region and the top of the PMOS gate mask layer; removing the photoresist layer in the first device region; etching to remove the natural silicon oxide layer on the surface of the first active region, further etching silicon in the first active region, and forming a U-shaped groove in the semiconductor substrate in the first device region; and carrying out TMAH etching on the U-shaped groove to form a sigma groove. According to the invention, in the process of embedding germanium-silicon into the source and the drain, the height difference between the PMOS and the NMOS is avoided, and the subsequent process is not influenced.

The invention provides an asymmetric trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the silicon carbide substrate to form a drift layer; performing ion implantation to form a freewheeling region; forming a barrier layer, etching, carrying out ion implantation, and forming a masking layer, a P-type well region and an N-type source region; re-forming a barrier layer, etching, etching the drift layer and the masking layer to form a groove, and oxidizing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the follow current region, metal is deposited, and a source electrode metal layer is formed; according to the invention, the body diode conduction loss of the device can be effectively reduced, the reverse recovery speed of the device can be improved, and the gate reliability and the source large current impact reliability of the device can be improved.

The invention discloses a preparation method of a solar cell and the solar cell. The preparation method comprises the following steps: removing a second mask layer on a first surface and a side surface of a silicon substrate by adopting a chained acid etching process; removing the second tunneling passivation structures on the first surface and the side surface of the silicon substrate by adopting a chained alkali etching process; and removing the second tunneling passivation structures in the first region and the third region of the second surface of the silicon substrate by adopting a groove type etching process, and forming a suede light trapping structure on the third region of the second surface of the silicon substrate and the first surface, and removing the first mask layer in the first area and the second mask layer in the second area on the second surface of the silicon substrate. According to the preparation method of the solar cell and the solar cell, the cell preparation process can be optimized, the environment is protected, the texture surface quality is improved, and the cell efficiency is improved.

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure. The preparation method comprises the following steps: providing a substrate; forming an isolation layer on the substrate; forming a first metal structure layer with a specific structure on the isolation layer; forming a natural oxide layer on the first metal structure layer; forming a protective layer on the natural oxide layer; a mask layer is formed on the protective layer, the protective layer and the natural oxide layer are etched downwards with the mask layer as a mask, and a reserved overlapping structure position is formed; forming a subsequent oxide layer on the first metal structure layer corresponding to the reserved overlapping structure position under a preset condition; and forming a second metal layer on the subsequent oxide layer, etching the second metal layer to form an overlapping structure, and taking the protection layer as an etching stop layer to protect the first metal structure layer when the second metal layer is etched. According to the invention, the first metal structure layer at the non-overlapping structure can be effectively prevented from being damaged when the second metal layer is etched, and the reliability problem is avoided.

The invention provides a patterned photonic crystal laser and a preparation method thereof, the laser comprises a substrate, and a first mask layer, a photonic crystal layer and a second mask layer which are sequentially deposited on the substrate, a light emitting area is etched in the central area of the second mask layer, and transparent conductive layers are deposited on the surface of the second mask layer and the light emitting area; a p-annular electrode is arranged on the surface of the transparent conductive layer on the second mask layer, and an n-annular electrode is arranged below the substrate; the photonic crystal layer is composed of a nanorod array and a polymer filled in gaps of nanorods; holes distributed in a patterned array are etched in the surface of the first mask layer, and nanorods are epitaxially grown in hole areas; the nanorod is formed by sequentially depositing a substrate contact layer, a first waveguide layer, a multi-quantum well layer, a second waveguide layer, a coating layer and a component gradient layer. According to the invention, through collaborative design optimization of all the layers, emission of laser with specific wavelength and preparation of a laser emitting laser with single longitudinal mode, narrow linewidth and stable wavelength are realized.

The invention relates to the technical field of semiconductor manufacturing, and discloses a tungsten oxide etching method, a semiconductor structure and a chip, and the method comprises the steps: forming a tungsten oxide thin film on a substrate; forming a mask layer with a target pattern on the tungsten oxide thin film; etching the tungsten oxide thin film with the mask layer by adopting mixed gas in ICP etching equipment; in the ICP etching equipment, the mixed gas comprises trifluoromethane and argon, the ratio range of the trifluoromethane in the mixed gas is 22.5%-74.1%, the flow rate of the mixed gas is 135-155 sccm, the ratio range of ICP power to bias power is 1.53: 1-3.3: 1, the depth-to-width ratio range of the tungsten oxide etching structure is 10: 1-23: 1, the inclination angle of the side wall of the tungsten oxide etching structure is 40-90 degrees, and the width of the tungsten oxide etching structure is 20-30 degrees. The technical problem that it is difficult to achieve a tungsten oxide etching structure with the nanoscale line width and the high aspect ratio in the prior art is solved.

The invention provides an EML laser and a preparation method of an air bridge, belongs to the technical field of optical communication lasers, and is used for solving the problem that the stray capacitance of connecting metal between a waveguide electrode and a PAD electrode of the EML laser is too large. The preparation method of the air bridge process of the EML comprises the following steps: growing a mask layer on the surface of an epitaxial InP wafer, photoetching to form a ridge waveguide pattern, etching the mask layer by adopting ICP (Inductively Coupled Plasma), and removing photoresist; etching the ohmic contact layer by adopting ICP (Inductively Coupled Plasma) and removing the mask layer; gluing and photoetching the surface of the wafer to form a pier pattern; adopting ICPCVD to grow a dielectric film at low temperature; gluing and photoetching the surface of the wafer to form a dielectric film bridge pattern; carrying out ICP etching on the dielectric film and removing the bridge and pier photoresist to form a dielectric film bridge; and performing wet etching on the InP epitaxial layer to the etching stop layer. According to the method, the dielectric film bridge is built at the connecting metal between the waveguide electrode and the PAD electrode, the low dielectric constant characteristic of air is utilized, the distance between the metal and the quantum well is greatly increased, the stray capacitance of the EML is reduced, and the bandwidth is improved.

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first work function adjustment material layer is formed over the gate dielectric layer, an adhesion enhancement layer is formed on the first work function adjustment material layer, a mask layer including an antireflective organic material layer is formed on the adhesion enhancement layer, and the adhesion enhancement layer and the first work function adjustment material layer are patterned by using the mask layer as an etching mask. The adhesion enhancement layer has a higher adhesion strength to the antireflective organic material layer than the first work function adjustment material layer.

The invention discloses a trench-type power semiconductor device with a gate protrusion structure and a preparation method thereof. The preparation method comprises the following steps: depositing an epitaxial layer on a silicon substrate; sequentially preparing a silicon dioxide cushion layer, a first mask layer and a second mask layer on the epitaxial layer; etching to form a gate trench; forming a gate oxide layer; depositing grid polycrystalline silicon; removing the grid polycrystalline silicon on the surface of the first mask layer through chemical mechanical grinding; etching to remove the first mask layer, and adjusting the morphology of the grid polycrystalline silicon on the silicon platform region; forming a body region and a source region through ion implantation; and preparing a source region contact hole and a tungsten bolt. According to the invention, the grid protrusion structure is formed in the preparation process of the groove type power semiconductor device, the problem that the channel electric leakage is increased after the polycrystalline silicon is etched is solved, the grid resistance is reduced by increasing the cross sectional area of the grid polycrystalline silicon, the switching speed and the linear region capability are improved, and the device performance is optimized.

The embodiment of the invention relates to the photovoltaic field, and provides a back contact solar cell, a preparation method thereof and a photovoltaic module, and the method comprises the steps: providing a substrate which comprises a front surface and a back surface which are opposite to each other, and the back surface comprises a first region and a non-first region; sequentially stacking a first doped conductive layer and a first mask layer on the back surface of the substrate, and removing the first mask layer corresponding to a non-first region through laser; at least removing the first doped conductive layer corresponding to the non-first region, wherein the remaining first doped conductive layer forms a first emitter; a second doped conductive layer and a second mask layer are sequentially stacked on the side, away from the first emitting electrode, of the remaining first mask layer and the non-first region, and materials of the first mask layer and the second mask layer independently comprise at least one of amorphous silicon, nanocrystalline silicon and silicon carbide; at least removing the second mask layer corresponding to the first region through laser; and at least removing the second doped conductive layer corresponding to the first region, wherein the remaining second doped conductive layer forms a second emitter.

The invention discloses an ionosphere super-resolution refining reconstruction method, device and equipment based on an improved ViT model and a storage medium, and relates to the technical field of ionosphere modeling, and the method comprises the steps: obtaining the TEC data and VTEC data of an ionosphere in a to-be-detected time period; taking the ionized layer TEC data as a low-resolution image, taking the VTEC data as a pixel true value, and generating a mask layer according to whether the pixel true value comprises an observation value or not; combining the low-resolution image, the pixel true value and the mask layer to obtain a multi-channel tensor; and taking the multi-channel tensor as input, and obtaining a global ionosphere map based on output of the improved ViT model. ViT is applied to super-resolution reconstruction of the ionosphere, dependence on the number of ground sites can be effectively reduced, the defect that the image is excessively smooth is overcome, meanwhile, the spatial resolution of the ionosphere image can be improved, and then the precision of an ionosphere model is improved.

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system, and the manufacturing method of a semiconductor structure comprises the steps: forming a first mask layer on a substrate, and forming a plurality of first openings in the first mask layer side by side; etching the substrate for the first time based on the plurality of first openings to form a plurality of first grooves arranged side by side; expanding the plurality of first openings, wherein the expanded plurality of first openings form a plurality of second openings; filling the plurality of first grooves and the plurality of second openings to form a plurality of filling structures arranged side by side; removing the first mask layer between the adjacent filling structures to form a third opening; and etching the substrate for the second time based on the third opening to form a second groove.

The invention provides a method for forming an embedded source-drain region. The method comprises the following steps of: covering a semiconductor layer and a gate stack structure to form a sacrificial layer; covering the side wall of the gate stack structure with a sacrificial layer to form an auxiliary side wall; and covering the first device region with a patterned mask layer, etching the second device region by taking the auxiliary side wall and the sacrificial layer as masks to form a sigma trench extending to enter the lower part of the gate stack structure, and simultaneously thinning the sacrificial layer covering the top surface of the gate stack structure of the second device region. According to the forming method, the etching loss of the gate stack structure of the corresponding device region can be reduced, the height difference of the isolation side walls between the PMOS region and the NMOS region is reduced or eliminated, the influence of different etching loads on the subsequent process is avoided, and the process stability is improved on the premise that the process cost and the process complexity are not improved.

A disposable facemask is provided having a filter body with an opening sized to cover the nose and mouth of a wearer. The filter body further includes an outer mask layer and an inner mask layer, and one or more intermediate layers disposed between the outer and inner mask layers. At least one of the intermediate layers is a nonwoven web layer including thermoplastic filaments formed from a random copolymer, or a random copolymer blended with a homopolymer.

The invention provides a semiconductor structure and a forming method thereof. The forming method comprises the following steps: forming a stacked film layer on a substrate; forming a mask layer on the stacked film layer, wherein the mask layer comprises a mask opening; forming a spacer layer on the side wall of the mask opening; etching the stacked film layer and the substrate by taking the mask layer and the spacing layer as masks so as to form a first groove in the stacked film layer, and forming a first groove in the substrate; performing an etching process to reduce the thickness of the first semiconductor layer and respectively form a second trench and a second groove in the stacked film layer and the substrate, and forming a protection layer in the second groove; wherein in the first direction, the width of the second groove is larger than that of the first groove, and the width of the second groove is larger than that of the first groove. According to the forming method, the protection material layer can be prevented from remaining, and the stability of the performance of the formed device is improved.

The invention discloses a vacancy-based controllable doping p-type two-dimensional transistor and a preparation method thereof, and mainly solves the problem that accurate controllable doping is difficult to realize in the prior art. According to the scheme, the device comprises an insulating substrate, a two-dimensional material channel layer, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode, wherein the source electrode and the drain electrode are located at the two ends of the two-dimensional material channel layer; the gate dielectric layer is located on the two-dimensional material channel layer and the source and drain electrodes; the method comprises the following steps: depositing a thick mask layer, thinning the mask layer part through photoetching and etching to form a patterned thin layer, bombarding a two-dimensional material and a two-dimensional material under a mask plate thin layer through treated mask layer ions to form a surface vacancy, removing a mask plate, exposing the two-dimensional material in an oxygen flow, and oxidizing to form surface charge transfer doping. According to the invention, under the condition that the two-dimensional material is not damaged and the performance is not influenced, partitioned controllable doping is realized, and the conductivity of the two-dimensional transistor is effectively improved.

The invention relates to the technical field of metal electrodes, and discloses a metal electrode, a preparation method and an optoelectronic device. The invention discloses a preparation method of a metal electrode. The preparation method comprises the following steps: S1, preparing a mask layer on a substrate of which the surface is covered with a transparent conductive film; s2, performing laser grooving on the surface of the mask layer to expose the metal seed layer; s3, a metal conducting layer is prepared on the metal seed layer through electroplating, and a metal electrode is obtained; wherein the substrate is selected from one of glass, a flexible material, ceramic, metal, a wafer and mica. The preparation method of the metal electrode provided by the invention is short in process, simple to operate, wide in mask layer selection range, strong in electrode adhesion, high in electrode processing precision, high in designability, simple in electroplating mode, strong in electroplating liquid adaptability, low in cost and high in production efficiency, and the corrosion resistance of the transparent conductive film can be improved.

The present application discloses an image stitching method for a stitching product, which includes: step 1: providing a chip design layout of the stitching product; step 2: designing a mask layout according to the chip design layout, including: step 21: setting unit mask images; step 22: merging logic images or cutting path images of adjacent areas between unit regions together to set corresponding peripheral mask images; step 23: merging the same peripheral mask images into one; step 24: constituting a mask layer by using the unit mask images and each peripheral mask image, and forming the mask layout on a mask; step 3: performing repeated exposure to form the stitching product. The present application can reduce the number of mask images, the number of times of exposure and the time of exposure.

To provide an analysis element and a manufacturing method thereof that can prevent an object to be analyzed from being unable to be analyzed appropriately.SOLUTION: A manufacturing method of this analysis element 100 includes the steps of forming a mask layer 20, forming a membrane layer 30, exposing a substrate 10, forming an introduction hole 13 and forming a protrusion 14 at the inlet end 13a of the introduction hole 13, and removing the protrusion 14 by wet etching the protrusion 14.SELECTED DRAWING: Figure 13

A method of manufacturing a structure having anodized parts includes: forming a bottom metal pattern with a dielectric layer thereon on a substrate, in which the dielectric layer has an opening exposing the bottom metal pattern; forming a semiconductor layer to cover the dielectric layer; forming a first metal layer on the semiconductor layer; forming a second metal layer on the first metal layer; forming a mask layer on the second metal layer to expose a portion of a top surface of the second metal layer; etching the second metal layer through the mask layer until a top surface of the first metal layer is exposed, in which an etch selectivity of the second metal layer and the first metal layer is greater than 2.0; anodizing the first metal layer through the mask layer to form an anodized segment; and removing the mask layer.

The invention provides a preparation method of a novel second-class superlattice infrared detector, and belongs to the field of infrared detectors. The problems that an inorganic film layer of an existing II-type superlattice infrared detector usually contains large stress and cracks are prone to occurring are solved. Comprising the following steps: depositing an inorganic mask layer on an epitaxial layer; coating photoresist on the inorganic mask layer, and developing to form patterned photoresist; performing etching on the inorganic mask layer to form a through hole structure; forming a mesa patterning photoresist above the inorganic mask layer of the through hole structure; forming a mesa pattern on the inorganic mask layer of the through hole structure; etching the epitaxial layer, and forming a patterned epitaxial layer below the inorganic mask layer of the through hole structure; depositing an inorganic passivation layer; photoetching trepanning or etching trepanning is carried out on the table top, and the inorganic mask layer and the inorganic passivation layer of the through hole structure are etched; the method is used for preparing the infrared detector.

The invention discloses a cue word optimization method, a cue word optimization system, cue word optimization equipment and a cue word optimization medium for video generation. The cue word optimization method specifically comprises the following steps: guiding a user to draw a motion diagram containing a dynamic mask layer and a motion trail vector layer in an image editing interface; performing spatial matching on the verb elements and the motion trail, and generating a contradictory region thermodynamic diagram in combination with an attention mechanism; when it is detected that a conflict area exists in the conflict area thermodynamic diagram, intention analysis is carried out through a reinforcement learning strategy, and a multi-dimensional optimization scheme is generated; and performing iterative verification on the corrected motion diagrams, and if the verification is passed, inputting the initial image and the multiple groups of motion diagrams into a multi-modal large language model to generate final cue words containing scene adaptation parameters. According to the invention, through integration of multi-source information such as images, semantic texts and motion diagrams and combination of technologies such as space matching, reinforcement learning and physical model analysis, accurate cue words containing scene adaptation parameters are generated, and the quality and precision of video generation are significantly improved.

A method for forming a high aspect ratio (HAR) structure during a HAR etch process, the method comprises sequentially or simultaneously exposing the substrate to a vapor of an etchant including one or more hydrofluorocarbon or fluorocarbon compounds or one or more hydrogen-containing molecules and an additive compound, the substrate having a film disposed thereon and a patterned mask layer disposed on the film; activating a plasma to produce activated one or more hydrofluorocarbon or fluorocarbon compounds or activated one or more hydrogen-containing molecules and an activated additive compound; and allowing an etching reaction to proceed between the film uncovered by the patterned mask layer and the activated hydrofluorocarbon or fluorocarbon compounds or the activated one or more hydrogen-containing molecules and the activated additive compound to selectively etch the film from the patterned mask layer, thereby forming the HAR patterned structure.