100 results about "Fine pitch" patented technology

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The invention discloses a solder paste defect detection method based on machine vision, relates to the technical field of printed circuit board detection, and aims at the challenge of solder paste printing quality detection in superfine-pitch high-reliability manufacturing, high-precision three-dimensional point cloud data is collected and an attitude matrix is marked through laser triangle-grating interference dual-mode imaging and board micro-vibration sensing; constructing an adaptive reference surface based on the point cloud and real-time fitting warping curved surface parameters, executing local height remapping, and eliminating the influence of micro warping; calculating a warping composite slope index and a glare texture robust index by using the height matrix, and adjusting a confidence threshold of the boundary enhanced convolutional network to realize real contour segmentation of adjacent pads; dynamically updating imaging parameters, accumulating real scene samples, and optimizing the adaptive ability of the model; and cross-shift knowledge reuse is realized through the shared model library. According to the invention, the volume measurement consistency and the first pass yield of the ultra-fine pitch bonding pad can be improved, and the process debugging time is shortened.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

To provide a probe card which makes an interval between probe pins correspond to a fine pitch of an inspection object.SOLUTION: A probe card for probing electrical characteristics of an inspection object includes: a plurality of probe pins in which a probe tip is formed at one side so as to contact the inspection object, and which extend from the one side to the other side; a wafer which is integrally joined to the plurality of probe pins in a state that at least a part of the plurality of probe pins are inserted thereinto, and which is constituted so that the probe tip is exposed to the outside; a film which is disposed so as to overlap with the wafer at one side, and which is connected to the other side of the plurality of probe pins; and a circuit substrate which is disposed so as to overlap with the other side of the film at least in part, and which is constituted to receive a probing signal from the plurality of probe pins via the film. An interval (pitch) between the plurality of probe pins has been expanded at the other side relative to the one side.SELECTED DRAWING: Figure 1

The invention discloses a superfine pitch bonding wire chopper structure with a side wire incoming function and a using method thereof, and relates to the technical field of semiconductor packaging, the superfine pitch bonding wire chopper structure comprises a workbench, a lifting platform, a lifting counting mechanism, a switching mechanism, a pay-off pipe, a chopper mechanism and a smoke suction mechanism, and the lifting platform is slidably arranged between the workbench and a mounting frame; the lifting counting mechanism is arranged on the mounting frame, the switching mechanism is arranged on the lifting table, the chopper mechanism is arranged on the lifting table, and the smoke suction mechanism is arranged on the lifting table. By means of the arrangement mode that the lifting counting mechanism, the switching mechanism, the pay-off pipe, the chopper mechanism and the smoke suction mechanism are matched, after the designated number of times is reached, the chopper is switched through the switching mechanism, bonding quality reduction caused by abrasion is avoided, the switched chopper is cleaned, and the bonding quality is improved. And meanwhile, the smoke suction mechanism can suck cleaned impurities and possibly generated smoke, smoke and chippings are effectively collected, manual intervention is reduced in the whole process, and the production efficiency is improved.

The invention relates to a laser bonding interconnection process, which comprises the following steps of: 1, selecting a substrate and a chip with a certain specification, cleaning the substrate and the chip, and then pre-treating the substrate and the chip; step 2, using a chip absorption and laser emission integrated device with a light-transmitting and high-temperature-resistant material to absorb a chip from the right above, placing an interconnection material between the chip and the substrate as an interconnection layer, and aligning the chip and the substrate to form an interconnection structure of the chip, the interconnection material and the substrate; thirdly, protective gas is introduced, proper laser parameters are selected through the device, pressure and ultrasound are applied, and the welding time is controlled to weld the interconnection structure; and step 4, cooling at room temperature to obtain the interconnection structure. Comprising fine pitch interconnection and chip die bonding, realizes interconnection with better performance, higher efficiency and lower cost, meets advanced packaging requirements, and is used for solving the technical problems.

The present invention provides a circuit board that facilitates the implementation of a fine pitch in a structure in which multiple bonding parts are arranged for electrical connection. The circuit board according to the present embodiment comprises: an insulating layer; pad parts disposed on the insulating layer; and bonding parts disposed on the pad parts, wherein the bonding parts are arranged so as to surround respective pad parts.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The utility model discloses a glass lens binding jig, which relates to the technical field of glass lens cold working, and comprises a left base and a right base, a left bushing is fixedly arranged at the side end part of the left base, a right bushing is fixedly arranged at the side end part of the right base, at least two guide plugs are fixedly arranged at the side end part of the right base, and the guide plugs are inserted into the left bushing and the right bushing. The shape of one end of the left lining and the shape of one end of the right lining are matched with the shape of the lens, the lens can be better fixed in the machining process, it is guaranteed that the position of the lens is stable in the machining process, the base made of the copper material can guarantee connection firmness and stability, the lining made of the bakelite material is relatively soft, and the service life of the lens is prolonged. The optical surface of the lens can be prevented from being scratched in the machining process, the left base and the right base are connected and fixed to machining equipment through the positioning seam allowances and the fine threads in the left base and the right base, and when the left lining and the right lining need to be folded, the guide plug can be inserted into the positioning hole, and it is ensured that the left lining and the right lining can be tightly attached.

To provide a printed circuit board capable of realizing patterns and pads having fine pitches, preventing defects in the patterns and the pads while using a low-cost process, and improving the reliability.SOLUTION: The present disclosure relates to a printed circuit board including a core layer, a plurality of first wirings arranged on the core layer, a first pad arranged on the core layer and including an adjacent portion arranged substantially parallel to adjacent wirings among the plurality of first wirings and an open portion arranged substantially non-parallel to the adjacent wirings among the plurality of first wirings, and a first build-up insulating layer arranged on the core layer and covering at least a portion of the plurality of first wirings and the first pad, and the core layer includes an insulating material substantially different from the first build-up insulating layer.SELECTED DRAWING: Figure 5b

A method to create flexible mutli-conductor cables include fabricating wiring on silicon-on-insulator wafers with lithographic fabrication techniques followed by thinning some sections of the wafer with a silicon etch. Exemplary cables can have fine pitch and low thermal conductivity enabling high density superconducting interconnects between different temperature stages in cryogenic platforms or between superconducting circuits oriented perpendicular to each other. Also presented herein are methods for making and using exemplary cables.

Disclosed is a polishing composition for a semiconductor process, including polishing particles, iron ions, and an iron ion stabilizer, in which the iron ion stabilizer comprises two or more carboxyl groups and the polishing composition has electrical conductivity of 200 μS / cm to 800 μS / cm. The polishing composition may polish a substrate surface including a tungsten pattern film having a fine pitch more smoothly.

The invention discloses a chemical tin solution for a flexible printed circuit board, and belongs to the technical field of circuit boards. The chemical tin solution comprises stannous mono-sulphate, methanesulfonic acid, a reducing agent, thiourea, a complexing agent, phytic acid, disodium ethylene diamine tetraacetate, an active agent, lanthanum chloride and a fluorine-substituted benzimidazole protective agent. Compared with the prior art, a hydrophobic network constructed by the fluorine-substituted benzimidazole protective agent effectively blocks environmental moisture permeation, the salt mist resistance and the tin immersion thickness of a chemical tin solution are improved, the grain boundary structure is synergistically optimized through the rare earth metal additive and the composite complexing agent, the compactness and the uniformity of a plating layer are remarkably improved, and the corrosion resistance of the plating layer is improved. And the fine-pitch wiring requirement is met. In addition, uniform nucleation of tin ions can be promoted, growth of tin whiskers is inhibited, a high-flatness coating is achieved, local micropores and cracks are reduced, and the method has high reliability and good application prospects.

Pitch particles may be produced by a grinding process, in which pitch fines may be recovered and recycled to a grinding apparatus as a pitch melt. Such methods may comprise: providing a petroleum pitch having a first softening temperature; grinding the petroleum pitch in a grinding apparatus below the first softening temperature to produce a plurality of pitch particles and a plurality of pitch fines; separating the pitch particles from the pitch fines; heating the pitch fines at a temperature above the first softening temperature to produce a pitch melt; and combining the pitch melt with the petroleum pitch in the grinding apparatus. The pitch melt hardens in the grinding apparatus and is reground. The pitch particles may be further stabilized by heating at a treatment temperature below the first softening temperature in an environment comprising about 1 mol % to about 20 mol % oxygen to form stabilized pitch particles.

The utility model belongs to the technical field of motor shells, and particularly relates to a roller motor shell, which comprises a motor end cover and a motor shell, the motor end cover is provided with an external fine pitch thread, the motor shell is provided with an internal thread groove, and the external fine pitch thread is in threaded connection with the internal thread groove. An assembly follow-up clamping module and a rotary locking module are arranged between the motor end cover and the motor shell; after the threads are assembled, the reset column head automatically pushes the locking column head to enter the inner side of the thread stripping limiting seat under the extrusion force generated by the twisted motor shell, and the rotation directions of the motor end cover and the motor shell are limited by the locking column head and the thread stripping limiting seat, so that the motor end cover and the motor shell are ensured not to generate thread stripping under the rotation action of the roller motor; due to the fact that the spiral lines of the outer fine-pitch threads and the inner thread grooves are arranged in the same direction as the rotating direction of the electric roller, when the motor operates, the shell can be fastened under the acting force generated when the roller motor rotates.

The invention provides a substrate for a semiconductor package and a semiconductor package including the same, wherein high-frequency communication can be realized, and a direct electroless gold plating (DEG) plating layer without a fine pitch corresponding nickel plating layer is formed on the substrate.

Technologies for a vertically interconnected glass layer architecture is disclosed. In the illustrative embodiment, an integrated circuit component includes several integrated circuit dies and a glass layer. Integrated circuit dies are positioned both above and below the glass layer. The glass layer has a bridge die embedded in a cavity. The bridge die provides interconnects between the various dies and to other components off of the integrated circuit component. The glass layer can enable three-dimensional heterogeneous integration, allowing for fine pitch connections between dies.

A method of manufacturing a packaging substrate according to the present disclosure comprises a resist pattern layer forming step of forming a resist pattern layer on a base substrate comprising a core layer and a metal base layer formed on the core layer. The resist pattern layer forming step comprises a lamination process of laminating a resist layer on the base substrate and an exposure process of selectively exposing the resist layer. The resist pattern layer comprises pattern holes having a diameter of 20 μm or less. The resist layer comprises a negative resist. An exposure dose of the exposure process is from 170 mJ / cm2 to 215 mJ / cm2.In this case, hole patterns having a fine pitch may be more accurately and densely formed in an insulating layer.

The present disclosure relates to solder-based hybrid bonding for fine pitch and thin BLT interconnects. A semiconductor device assembly includes a first semiconductor device including a first substrate having a front side surface, a plurality of solder bumps on the front side surface of the first substrate, and a first polymer layer on the front side surface. The semiconductor device assembly also includes a second semiconductor device including a second substrate having a back side surface, a plurality of TSVs protruding from the back side surface of the second substrate, and a second polymer layer on the back side surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer, and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

The application provides a packaging substrate and a manufacturing method thereof. The application sets a film column in the first window of the protective layer, and sets a metal layer on the film column after secondary film pressing, so as to obtain a bump. Since the bump is obtained by setting the metal layer on the film column instead of being directly electroplated in the first window, the thickness and height of the metal layer formed by electroplating can be reduced due to the existence of the film column, that is, the difficulty of electroplating and the probability of skip plating are reduced, so that a bump with a finer pitch and a higher aspect ratio can be manufactured, and the uniformity of the metal layer can be improved.

An electronic substrate may be fabricated to include a fine pitch dielectric layer having an upper surface, a coarse pitch dielectric layer on the upper surface of the fine pitch dielectric layer, and at least one hybrid conductive via extending through the fine pitch dielectric layer and the coarse pitch dielectric layer. The hybrid conductive via is fabricated such that a portion thereof that extends through the fine pitch dielectric layer is smaller than a portion extending through the coarse pitch dielectric layer, which results in a stepped configuration, wherein a portion of the hybrid conductive via abuts the upper surface of the fine pitch dielectric layer. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection therebetween.

The application discloses a kind of non-directional laser sintering interconnection processes, comprising the following steps: step one, select appropriate substrate and chip, and after the substrate and the chip are cleaned, it is pretreated;Step two, interconnection material is placed in chip and substrate as interconnection layer, so that it forms the interconnection structure of chip, interconnection material and substrate;Step three, protective gas is passed, appropriate laser parameters are selected using laser welding machine, and the irradiation direction of laser beam is set, while pressure and ultrasonic are applied and welding time is controlled to weld the interconnection structure;Step four, after cooling at room temperature, the interconnection structure is obtained.Non-directional laser sintering interconnection process, including fine-pitch interconnection and chip die bonding, can reduce the occurrence of substrate warping phenomenon, meet the requirements of advanced packaging, and solve the above technical problems.

To bond multiple dies together at a fine pitch required to achieve a desired interconnect density.SOLUTION: A microelectronic assembly 100 includes: a first layer having dies 114-1 and 114-2 surrounded by an insulating material 133; a second layer on the first layer having conductive paths 196 through a dielectric material, the conductive paths 196 including a conductive trace and a conductive via having an inverted-trapezoid shape; and a third layer on the second layer having a glass layer and a conductive through-glass via (TGV 110), wherein the conductive TGV 110 is electrically coupled to the conductive paths 196, and the dies 114-1 and 114-2 are electrically coupled to the conductive TGV 110 by the conductive paths 196.SELECTED DRAWING: Figure 1A

Disclosed is a polishing composition for a semiconductor process, including polishing particles, iron ions, and an iron ion stabilizer, in which the iron ion stabilizer comprises two or more carboxyl groups and the polishing composition has electrical conductivity of 200 µS / cm to 800 µS / cm. The polishing composition may polish a substrate surface including a tungsten pattern film having a fine pitch more smoothly.

The invention relates to the technical field of printed circuit board manufacturing, and discloses a method for preparing a refined fine pitch single-sided thick copper circuit board based on a screen printing process, which comprises the following steps of: cutting a single-sided copper-clad plate into a plate material for production when the copper thickness of the single-sided copper-clad plate is 2 ounces; with the conveying direction of subsequent machining of the plate as the reference, the line perpendicular to the conveying direction in the original line is defined as a transverse line, and the line parallel to the conveying direction is defined as a vertical line; according to the requirement that the target line width / line distance is smaller than or equal to 0.15 mm for fine and fine distance, size pre-compensation is conducted on an original line pattern, the compensation amount of a transverse line is 0.025 mm, and the compensation amount of a vertical line is 0.035 mm; and coating anti-etching ink by adopting a silk-screen process, accurately laminating the film drawn with the compensated circuit pattern with a plate material, carrying out silk-screen treatment, and then carrying out curing, etching and film removal treatment. The method has the effect of solving the problem in the prior art that fine and fine pitch lines of 0.15 mm and below are difficult to realize stably and in batches by adopting a silk-screen process on a thick copper single-sided board.

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Panel-level high performance computing (HPC) computing architectures and methods of making the same are disclosed. Panel architectures with and without glass cores include dielectric layers with interconnect structures (vias, conductive traces) to convert die-level output pins arranged at fine pitches to panel-level output pins arranged at thicker pitches. Local interconnects and local interconnect components provide electrical communication between integrated circuit dies in the panel. The coreless panel architecture may include a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer may have interconnect structures and local interconnect features. Panel embodiments having a glass core or glass reinforcement layer may include waveguides and channels through which liquid coolant passes, and may also include photonic integrated circuits. Panel-level manufacturing techniques may implement panels having dimensions larger (e.g., greater than 300 mm) than components manufactured using wafer-level manufacturing techniques.

Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.

To provide an insert module for an electronic component, including: a pitch adjuster configured to allow an electronic component requiring a test to be seated thereon, and including one side electrically connected to connection pins of the electronic component and another side provided with electrical contact means at a second pitch wider than a first pitch of the connection pins; and a holder configured to be able to hold the seated electronic component.SOLUTION: The insert module for an electronic component and a test tray including the same are capable of accurate contact corresponding to a fine pitch of the electronic component, and can maintain precise contact during a test, thereby capable of improving the accuracy of the test.SELECTED DRAWING: Figure 2

A probe card for use in circuit probe testing and methods of fabrication thereof. The probe card includes a circuit board, an interposer structure that is mounted to the circuit board, and a probe structure mounted to the interposer structure and including a probe substrate, a redistribution layer over the probe substrate, and a plurality of probe pins over the redistribution layer. The interposer structure may include a plurality of elastically-deformable interposer pins electrically connecting the circuit board to the probe substrate. The center-to-center spacing (i.e., pin pitch) between the interposer pins may be greater than the center-to-center spacing (i.e., a second pin pitch) between the probe pins. A probe card in accordance with various embodiments may enable circuit probe testing of a device-under-test with a pitch between adjacent probe pins that is less than 50 μm.