28 results about "Fine pitch" patented technology

The present invention provides a circuit board that facilitates the implementation of a fine pitch in a structure in which multiple bonding parts are arranged for electrical connection. The circuit board according to the present embodiment comprises: an insulating layer; pad parts disposed on the insulating layer; and bonding parts disposed on the pad parts, wherein the bonding parts are arranged so as to surround respective pad parts.

Pitch particles may be produced by a grinding process, in which pitch fines may be recovered and recycled to a grinding apparatus as a pitch melt. Such methods may comprise: providing a petroleum pitch having a first softening temperature; grinding the petroleum pitch in a grinding apparatus below the first softening temperature to produce a plurality of pitch particles and a plurality of pitch fines; separating the pitch particles from the pitch fines; heating the pitch fines at a temperature above the first softening temperature to produce a pitch melt; and combining the pitch melt with the petroleum pitch in the grinding apparatus. The pitch melt hardens in the grinding apparatus and is reground. The pitch particles may be further stabilized by heating at a treatment temperature below the first softening temperature in an environment comprising about 1 mol % to about 20 mol % oxygen to form stabilized pitch particles.

Technologies for a vertically interconnected glass layer architecture is disclosed. In the illustrative embodiment, an integrated circuit component includes several integrated circuit dies and a glass layer. Integrated circuit dies are positioned both above and below the glass layer. The glass layer has a bridge die embedded in a cavity. The bridge die provides interconnects between the various dies and to other components off of the integrated circuit component. The glass layer can enable three-dimensional heterogeneous integration, allowing for fine pitch connections between dies.

A method of manufacturing a packaging substrate according to the present disclosure comprises a resist pattern layer forming step of forming a resist pattern layer on a base substrate comprising a core layer and a metal base layer formed on the core layer. The resist pattern layer forming step comprises a lamination process of laminating a resist layer on the base substrate and an exposure process of selectively exposing the resist layer. The resist pattern layer comprises pattern holes having a diameter of 20 μm or less. The resist layer comprises a negative resist. An exposure dose of the exposure process is from 170 mJ / cm2 to 215 mJ / cm2.In this case, hole patterns having a fine pitch may be more accurately and densely formed in an insulating layer.

The application provides a packaging substrate and a manufacturing method thereof. The application sets a film column in the first window of the protective layer, and sets a metal layer on the film column after secondary film pressing, so as to obtain a bump. Since the bump is obtained by setting the metal layer on the film column instead of being directly electroplated in the first window, the thickness and height of the metal layer formed by electroplating can be reduced due to the existence of the film column, that is, the difficulty of electroplating and the probability of skip plating are reduced, so that a bump with a finer pitch and a higher aspect ratio can be manufactured, and the uniformity of the metal layer can be improved.

The invention relates to the technical field of printed circuit board manufacturing, and discloses a method for preparing a refined fine pitch single-sided thick copper circuit board based on a screen printing process, which comprises the following steps of: cutting a single-sided copper-clad plate into a plate material for production when the copper thickness of the single-sided copper-clad plate is 2 ounces; with the conveying direction of subsequent machining of the plate as the reference, the line perpendicular to the conveying direction in the original line is defined as a transverse line, and the line parallel to the conveying direction is defined as a vertical line; according to the requirement that the target line width / line distance is smaller than or equal to 0.15 mm for fine and fine distance, size pre-compensation is conducted on an original line pattern, the compensation amount of a transverse line is 0.025 mm, and the compensation amount of a vertical line is 0.035 mm; and coating anti-etching ink by adopting a silk-screen process, accurately laminating the film drawn with the compensated circuit pattern with a plate material, carrying out silk-screen treatment, and then carrying out curing, etching and film removal treatment. The method has the effect of solving the problem in the prior art that fine and fine pitch lines of 0.15 mm and below are difficult to realize stably and in batches by adopting a silk-screen process on a thick copper single-sided board.

A wire bonding method for forming a vertical wire interconnect structure includes the steps of: forming a wire bond at a bonding pad on a substrate using a wire bonding tool; removing the wire bonding tool from the bonding pad to extend a segment of bonding wire between the wire bonding tool and the wire bond; pressing a point on the section of the bonding wire between the capillary tube and the spherical wire bonding against a part of the wire bonding by using a wire bonding tool so as to form a weakened part of the bonding wire; and straightening the section of bonding wire by moving the wire bonding tool, and enabling the bonding wire to be broken at the weakening part to form the vertical wire interconnection structure.

An integrated circuit package provides a high bandwidth interconnect between wafers using a very high density interconnect using a silicon bridge or a multi-layer flex between wafers. In some embodiments, more than one wafer may be mounted and connected with a rigid silicon bridge onto a common substrate. This common substrate can be matched, with respect to their coefficients of thermal expansion (CTE), to the silicon wafer. The CTE matched substrate can reduce the thermal mechanical stress on the wafers and the rigid silicon bridge interconnect. In some embodiments, a thinned silicon bridge is utilized to interconnect wafers which are mounted on separate glass substrates. The thinned bridge would allow for mechanical compliance between the wafers. In some embodiments, the wafers can be mounted onto separate glass substrates and attached with a fine pitch multi-layer flex structure which provides compliance between the wafers.

Vertical die to die (D2D) interconnected chiplets on a glass core. The chiplets are two different integrated circuit dies, often considered “hot” dies, and called top dies herein. The glass core includes a cavity. An active I / O die is in the cavity to provide the D2D communication, its top surface flush with the upper surface of the glass core. Two different sized micro-bumps are used, the first micro-bumps have a smaller pitch (e.g., “fine pitch”) and are to attach the top dies to the top surface. The second micro-bumps are larger than the first (e.g., “coarse pitch”), and are to attach the top dies to the upper surface of the glass core. An organic build, and solder ball backside may be fabricated on the lower surface of the glass core.

A vertical die-to-die (D2D) interconnect chiplet on a glass core is disclosed. The chiplet consists of two distinct integrated circuit dies, often considered "hot" dies and referred to herein as the top die. The glass core includes a cavity. An active I / O die is located within the cavity to provide D2D communication, its top surface being flush with the top surface of the glass core. Two microbumps of different sizes are used; the first microbump has a smaller pitch (e.g., "fine pitch") and is used to attach the top die to the top surface. The second microbump is larger than the first microbump (e.g., "coarse pitch") and is used to attach the top die to the upper surface of the glass core. Organic components and solder ball backsides can be fabricated on the lower surface of the glass core.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The utility model provides a high density packaging structure based on an interconnection bridge and an adapter plate, comprising a substrate, a first chip, a second chip, an interconnection bridge and an adapter plate, the first chip and the second chip are both provided with a plurality of micro welding spots, the first chip and the second chip are respectively welded and bonded with the corresponding adapter plates through part of the micro welding spots so as to form longitudinal interconnection with the adapter plates, the adapter plates and the substrate form longitudinal interconnection through welding balls, the first chip and the second chip are connected with the interconnection bridge through part of the micro welding spots, and the interconnection bridge is connected with the substrate through part of the micro welding spots. Transverse high-density interconnection is formed through the interconnection bridge, high-density fine-pitch lines which are transversely interconnected are integrated in the interconnection bridge, and the line width / line pitch is smaller than the line width / line pitch of the substrate. According to the utility model, the problems of complex process, high manufacturing difficulty and the like of embedding a substrate into an interconnection bridge during high-density interconnection between chips at present are solved.

In integrated circuit packages, a coaxial pair of signals are routed through a plated through hole between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods and apparatuses where signals are routed within a concentric reference conductor within traditional package substrates. Methods for forming a hole in the core substrate material through which the coaxial pair of signals is passed on a fine pitch.

The present invention relates to a method for manufacturing a probe, and more particularly, to a method for manufacturing a probe and a probe, which can finely adjust the pitch between pins by superposing the probe pins and can freely form the length and shape of the probe pins. A method for manufacturing a probe according to an embodiment of the present invention includes a first photoresist forming step, a first elastic layer forming step, a hollow forming step, a first pin forming step, a second elastic layer superimposing step, a layer superimposing step, a second photoresist forming step, and a sacrificial layer removing step. The present invention also provides a probe manufactured by performing the steps of the manufacturing method. According to the present invention, a probe having a fine pitch can be manufactured, a probe capable of simultaneously inspecting a plurality of devices can be provided, and the shape of a probe pin can be easily and freely formed. In addition, since the probe pins are vertically formed and wiring is easy, more probe pins can be formed in the same area, so that the density of the probe pins can be improved, and the probe pins can be easily connected to a probe station.

Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first via is through the core, where the first via comprise a conductive material, and a film over the first surface of the core, where the film is an adhesive. In an embodiment, a second via is through the film, where the second via comprises a conductive material, where the second via contacts the first via. In an embodiment, a centerline of the second via is aligned with a centerline of the first via. In an embodiment, a buildup layer is over the film.

Provided is an anisotropic conductive film that, whether in a case where axes of each terminal of a terminal row are aligned side by side in the same direction or in a case of a fan-out type in which they are radiated, ensures a good conduction state by sandwiching each terminal with sufficient conductive particles and makes the capture state of the conductive particles at each terminal uniform, and even if terminals of a fine pitch are connected, prevents the occurrence of short circuits. This anisotropic conductive film (10A) has conductive particles (2) disposed in an insulating resin layer (3). In the xy plane of the anisotropic conductive film (10A) viewed from above, the zigzag-shaped arrangement R in which the arrangement Rb in which the conductive particles (2) are arranged at a positive slope and the arrangement Rc in which the conductive particles (2) are arranged at a negative slope are repeatedly arranged at a predetermined interval in the y direction is arranged at a predetermined pitch in the x direction while periodically changing the position in the y direction. The conductive particles thereby become a pseudo-random type regular arrangement (1A).

This invention provides a printed circuit board that allows for electrical connection to the underside when embedding electronic components such as interconnect bridges, ensuring stability and reliability even when connections are made at a fine pitch, thereby improving the performance and efficiency of semiconductor packages while efficiently managing manufacturing costs. [Solution] The present invention relates to a printed circuit board comprising an insulator, a cavity penetrating a portion of the insulator and having a bottom surface, a plurality of wiring layers each disposed within the insulator, an electronic component at least partially disposed within the cavity, and a sealing material covering at least a portion of the insulator and the electronic component and filling at least a portion of the cavity, wherein one of the plurality of wiring layers includes a pad that is at least partially exposed from the insulator through the cavity, the electronic component is connected to the pad via a connecting member, and the pad contains a nanotwin metal.

The present invention discloses a plug-in module for testing a tray, the plug-in module comprising: a pitch adjuster configured to position an electronic device thereon and comprising a first side electrically connected to a connection pin of the electronic device and a second side provided with an electrical contact means, the second spacing of the electrical contact means is wider than the first spacing of the connection pins; and a holder configured to hold the disposed electronic device. According to the present disclosure, the insert module for a test tray and the test tray including the same can perform accurate contact corresponding to a fine pitch of electronic devices, and maintain accurate contact during a test, thereby improving accuracy of the test.

The present application relates to a kind of double-sided heterogeneous integrated panel level packaging method based on embedded substrate, preparation substrate with cavity and bonding support carrier, after embedding control chip and power chip, front plastic package and through panel level packaging process copper column rewire, back carrier removal leads to bonding, plastic package.The present application will panel level packaging process and lead bonding process be independently executed by the spatial separation design of substrate front and back, eliminate the incompatible problem existing in the two processes in the scheme, break through the core bottleneck that the two are difficult to integrate in traditional technology;Panel level packaging process of substrate front guarantees the high density and low parasitic characteristic of power transmission, lead bonding process of substrate back can flexibly meet the pin lead-out demand of control chip high pin number, fine pitch, the advantages of two processes are complementary, break through the limitation of single packaging technology in density promotion, improve packaging processing stability and yield, optimize electrical transmission performance and improve thermal management effect.

This invention relates to the field of electronic packaging materials technology, specifically to a semiconductor flux composition and its preparation method. The composition comprises: a film-forming agent, a composite activation system, a high-boiling-point composite solvent, and composite functional additives. The composite activation system is a gradient temperature-responsive halogen-free activation system, composed of a long-chain dibasic organic acid, a hydroxyl-containing polybasic organic acid, and an organic amine activator in a specific ratio. The flux composition of this invention is halogen-free and environmentally friendly, possesses gradient-controllable activation performance, exhibits excellent high-temperature deoxidation ability, and shows extremely low corrosion to metal pads. It is suitable for ultra-fine pitch semiconductor interconnect processes below 30μm, with a solder joint void ratio ≤2% and a surface insulation resistance ≥10 Ω·cm. 14 Ω meets the requirements of high-reliability semiconductor applications such as wafer-level packaging, flip-chip, and 2.5D / 3D advanced packaging. Its fabrication method is simple and controllable, making it suitable for industrial production.

The application discloses a kind of softness printed circuit board with chemical tin solution, belong to the technical field of circuit board.The chemical tin solution includes stannous sulfate, methyl sulfonic acid, reducing agent, thiourea, complexing agent, phytic acid, ethylenediaminetetraacetic acid disodium, active agent, lanthanum chloride and fluorine-substituted benzimidazole protective agent.Compared with prior art, the hydrophobic network constructed by fluorine-substituted benzimidazole protective agent of the application effectively blocks the penetration of environmental humidity, improves the salt fog resistance and tin thickness of the chemical tin solution, optimizes the grain boundary structure by synergistic effect of rare earth metal additive and composite complexing agent, significantly improves the compactness and uniformity of the coating, meets the fine pitch wiring requirement.In addition, the application can also promote the uniform nucleation of tin ions, inhibit the growth of tin whiskers, achieve high flatness coating, reduce local micropores and cracks, and has high reliability and good application prospect.

An exemplary device and method that provides sub-10-um fine pitch interconnection between (i) a protruding pillar structure with Cu (e.g., nano-twinned Cu) on one surface having a B-stageable / Photo imageable polymer and (ii) a corresponding concave landing pad with Cu (e.g., nano-twinned Cu) on the other surface also having a same B-stageable / Photo imageable polymer, to provide for insertions for Cu-Cu bonding and B-stageable / Photo imageable polymers bonding. The Cu-Cu bonding and polymer bonding can facilitate a seamless bond interface at a low bonding temperature of 150° C. or even at room temperature (RT) with cleaned and improved surfaces.

The present application relates to the field of printed circuit board manufacturing, more particularly, to a printed circuit board manufacturing method integrating multiple surface treatments and a printed circuit board. The method comprises: S100, manufacturing a multi-layer board; S200, exposing a electroplated hard gold area through a first selective exposure, plating nickel and gold-cobalt alloy to form a hard gold layer; S300, forming an outer layer circuit; S400, exposing a thick gold plating area through a second selective exposure, chemically plating nickel and gold to form a thick gold plating layer; S500, exposing a nickel-palladium-gold plating area through a third selective exposure, chemically plating nickel, palladium and gold to form a nickel-palladium-gold plating layer; S600, forming and testing; S700, exposing a silver plating area through a fourth selective exposure, chemically plating silver to form a silver plating layer; S800, final inspection and delivery. Through four selective exposures, the electroplated hard gold, thick gold plating, nickel-palladium-gold plating and silver plating are sequentially integrated on the same printed circuit board, so that the printed circuit board has the functions of wear-resistant plugging, gold wire bonding, fine pitch soldering and high-frequency signal transmission.

A method of manufacturing a packaging substrate according to the present disclosure manufactures a packaging substrate by including a preparation step of providing a base substrate including a core layer and an insulating layer disposed on the core layer and a plasma step of plasma-treating an upper surface of the insulating layer. In the plasma step, an inert gas is applied as a process gas, and a plasma process condition index (Ipp value) defined by the following Equation 1 is 80 seconds or greater. A developed interfacial area ratio (Sdr value) of the upper surface of the insulating layer after completion of the plasma step is 50% or less. [Equation 1] Ipp=Rsb*H In Equation 1, Rsb is a ratio of bias power to source power applied during the plasma step, and His a processing time of the plasma step. In such a case, a redistribution layer having a fine pitch on the core layer may be more precisely implemented.

Vertical die-to-die (D2D) interconnected chiplets on a glass core. The chiplets are two distinct integrated circuit dies, often referred to as "hot" dies and here called the top dies. The glass core contains a cavity. An active I / O die resides within the cavity to provide D2D communication, with its top face flush with the top surface of the glass core. Two differently sized microcontact bumps are used: the first microcontact bumps have a smaller pitch (e.g., "fine pitch") and serve to attach the top dies to the top face; the second microcontact bumps are larger than the first (e.g., "coarse pitch") and serve to attach the top dies to the top surface of the glass core. An organic build-up and solder ball backing may be fabricated on the bottom surface of the glass core.

The present invention provides a substrate and printed circuit board containing a nano-twin metal layer that can easily accommodate fine pitches such as microbumps and offer superior reliability. [Solution] The present invention relates to a substrate comprising a substrate, a seed layer disposed on the substrate, and a nanotwin metal layer disposed on the seed layer, wherein the seed layer comprises a randomly oriented crystal structure, a crystal structure preferentially oriented on the (200) plane and / or a crystal structure preferentially oriented on the (220) plane, and a printed circuit board formed using the same.

The embodiment of the invention provides a probe card with a fine pitch adjusting function, and relates to the technical field of semiconductor testing, the probe card comprises an upper guide plate, a first lower guide plate and a plurality of probe units, the upper guide plate is provided with a plurality of groups of No.1 jacks; the first lower guide plate is provided with second insertion holes corresponding to the first insertion holes, the upper portions of the multiple needle units are inserted into the first insertion holes correspondingly and supported on one side of the inner surface of the upper guide plate, and the lower portions of the multiple needle units are inserted into the second insertion holes correspondingly and supported on one side of the inner surface of the upper guide plate. A guide module used for adjusting the distance between the lower ends of the adjacent needle units is arranged below the first lower guide plate. According to the invention, the micro-spacing between the needle units can be realized, and the micro-spacing between the needle units can be formed to be finer.

A semiconductor device has a substrate and an electrical component disposed over a first surface of the substrate. A first encapsulant is deposited over the first surface of the substrate. A second encapsulant is deposited over a second surface of the substrate with a via formed in the second encapsulant. A conductive material containing a graphene core shell is deposited in the via in the second encapsulant to form a conductive post. The graphene core shell can have a copper core with a graphene coating formed over the copper core. The conductive material has a matrix to embed the graphene core shell. The conductive material can have a plurality of cores covered by graphene and the graphene is interconnected within the conductive material to form an electrical path. The conductive material can have thermoset material or polymer or composite epoxy type matrix to embed the graphene core shell.