69 results about "Fine pitch" patented technology

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The invention discloses a solder paste defect detection method based on machine vision, relates to the technical field of printed circuit board detection, and aims at the challenge of solder paste printing quality detection in superfine-pitch high-reliability manufacturing, high-precision three-dimensional point cloud data is collected and an attitude matrix is marked through laser triangle-grating interference dual-mode imaging and board micro-vibration sensing; constructing an adaptive reference surface based on the point cloud and real-time fitting warping curved surface parameters, executing local height remapping, and eliminating the influence of micro warping; calculating a warping composite slope index and a glare texture robust index by using the height matrix, and adjusting a confidence threshold of the boundary enhanced convolutional network to realize real contour segmentation of adjacent pads; dynamically updating imaging parameters, accumulating real scene samples, and optimizing the adaptive ability of the model; and cross-shift knowledge reuse is realized through the shared model library. According to the invention, the volume measurement consistency and the first pass yield of the ultra-fine pitch bonding pad can be improved, and the process debugging time is shortened.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The invention discloses a superfine pitch bonding wire chopper structure with a side wire incoming function and a using method thereof, and relates to the technical field of semiconductor packaging, the superfine pitch bonding wire chopper structure comprises a workbench, a lifting platform, a lifting counting mechanism, a switching mechanism, a pay-off pipe, a chopper mechanism and a smoke suction mechanism, and the lifting platform is slidably arranged between the workbench and a mounting frame; the lifting counting mechanism is arranged on the mounting frame, the switching mechanism is arranged on the lifting table, the chopper mechanism is arranged on the lifting table, and the smoke suction mechanism is arranged on the lifting table. By means of the arrangement mode that the lifting counting mechanism, the switching mechanism, the pay-off pipe, the chopper mechanism and the smoke suction mechanism are matched, after the designated number of times is reached, the chopper is switched through the switching mechanism, bonding quality reduction caused by abrasion is avoided, the switched chopper is cleaned, and the bonding quality is improved. And meanwhile, the smoke suction mechanism can suck cleaned impurities and possibly generated smoke, smoke and chippings are effectively collected, manual intervention is reduced in the whole process, and the production efficiency is improved.

The present invention provides a circuit board that facilitates the implementation of a fine pitch in a structure in which multiple bonding parts are arranged for electrical connection. The circuit board according to the present embodiment comprises: an insulating layer; pad parts disposed on the insulating layer; and bonding parts disposed on the pad parts, wherein the bonding parts are arranged so as to surround respective pad parts.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

The utility model discloses a glass lens binding jig, which relates to the technical field of glass lens cold working, and comprises a left base and a right base, a left bushing is fixedly arranged at the side end part of the left base, a right bushing is fixedly arranged at the side end part of the right base, at least two guide plugs are fixedly arranged at the side end part of the right base, and the guide plugs are inserted into the left bushing and the right bushing. The shape of one end of the left lining and the shape of one end of the right lining are matched with the shape of the lens, the lens can be better fixed in the machining process, it is guaranteed that the position of the lens is stable in the machining process, the base made of the copper material can guarantee connection firmness and stability, the lining made of the bakelite material is relatively soft, and the service life of the lens is prolonged. The optical surface of the lens can be prevented from being scratched in the machining process, the left base and the right base are connected and fixed to machining equipment through the positioning seam allowances and the fine threads in the left base and the right base, and when the left lining and the right lining need to be folded, the guide plug can be inserted into the positioning hole, and it is ensured that the left lining and the right lining can be tightly attached.

A method to create flexible mutli-conductor cables include fabricating wiring on silicon-on-insulator wafers with lithographic fabrication techniques followed by thinning some sections of the wafer with a silicon etch. Exemplary cables can have fine pitch and low thermal conductivity enabling high density superconducting interconnects between different temperature stages in cryogenic platforms or between superconducting circuits oriented perpendicular to each other. Also presented herein are methods for making and using exemplary cables.

The invention discloses a chemical tin solution for a flexible printed circuit board, and belongs to the technical field of circuit boards. The chemical tin solution comprises stannous mono-sulphate, methanesulfonic acid, a reducing agent, thiourea, a complexing agent, phytic acid, disodium ethylene diamine tetraacetate, an active agent, lanthanum chloride and a fluorine-substituted benzimidazole protective agent. Compared with the prior art, a hydrophobic network constructed by the fluorine-substituted benzimidazole protective agent effectively blocks environmental moisture permeation, the salt mist resistance and the tin immersion thickness of a chemical tin solution are improved, the grain boundary structure is synergistically optimized through the rare earth metal additive and the composite complexing agent, the compactness and the uniformity of a plating layer are remarkably improved, and the corrosion resistance of the plating layer is improved. And the fine-pitch wiring requirement is met. In addition, uniform nucleation of tin ions can be promoted, growth of tin whiskers is inhibited, a high-flatness coating is achieved, local micropores and cracks are reduced, and the method has high reliability and good application prospects.

Pitch particles may be produced by a grinding process, in which pitch fines may be recovered and recycled to a grinding apparatus as a pitch melt. Such methods may comprise: providing a petroleum pitch having a first softening temperature; grinding the petroleum pitch in a grinding apparatus below the first softening temperature to produce a plurality of pitch particles and a plurality of pitch fines; separating the pitch particles from the pitch fines; heating the pitch fines at a temperature above the first softening temperature to produce a pitch melt; and combining the pitch melt with the petroleum pitch in the grinding apparatus. The pitch melt hardens in the grinding apparatus and is reground. The pitch particles may be further stabilized by heating at a treatment temperature below the first softening temperature in an environment comprising about 1 mol % to about 20 mol % oxygen to form stabilized pitch particles.

The utility model belongs to the technical field of motor shells, and particularly relates to a roller motor shell, which comprises a motor end cover and a motor shell, the motor end cover is provided with an external fine pitch thread, the motor shell is provided with an internal thread groove, and the external fine pitch thread is in threaded connection with the internal thread groove. An assembly follow-up clamping module and a rotary locking module are arranged between the motor end cover and the motor shell; after the threads are assembled, the reset column head automatically pushes the locking column head to enter the inner side of the thread stripping limiting seat under the extrusion force generated by the twisted motor shell, and the rotation directions of the motor end cover and the motor shell are limited by the locking column head and the thread stripping limiting seat, so that the motor end cover and the motor shell are ensured not to generate thread stripping under the rotation action of the roller motor; due to the fact that the spiral lines of the outer fine-pitch threads and the inner thread grooves are arranged in the same direction as the rotating direction of the electric roller, when the motor operates, the shell can be fastened under the acting force generated when the roller motor rotates.

Technologies for a vertically interconnected glass layer architecture is disclosed. In the illustrative embodiment, an integrated circuit component includes several integrated circuit dies and a glass layer. Integrated circuit dies are positioned both above and below the glass layer. The glass layer has a bridge die embedded in a cavity. The bridge die provides interconnects between the various dies and to other components off of the integrated circuit component. The glass layer can enable three-dimensional heterogeneous integration, allowing for fine pitch connections between dies.

A method of manufacturing a packaging substrate according to the present disclosure comprises a resist pattern layer forming step of forming a resist pattern layer on a base substrate comprising a core layer and a metal base layer formed on the core layer. The resist pattern layer forming step comprises a lamination process of laminating a resist layer on the base substrate and an exposure process of selectively exposing the resist layer. The resist pattern layer comprises pattern holes having a diameter of 20 μm or less. The resist layer comprises a negative resist. An exposure dose of the exposure process is from 170 mJ / cm2 to 215 mJ / cm2.In this case, hole patterns having a fine pitch may be more accurately and densely formed in an insulating layer.

The present disclosure relates to solder-based hybrid bonding for fine pitch and thin BLT interconnects. A semiconductor device assembly includes a first semiconductor device including a first substrate having a front side surface, a plurality of solder bumps on the front side surface of the first substrate, and a first polymer layer on the front side surface. The semiconductor device assembly also includes a second semiconductor device including a second substrate having a back side surface, a plurality of TSVs protruding from the back side surface of the second substrate, and a second polymer layer on the back side surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer, and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

The application provides a packaging substrate and a manufacturing method thereof. The application sets a film column in the first window of the protective layer, and sets a metal layer on the film column after secondary film pressing, so as to obtain a bump. Since the bump is obtained by setting the metal layer on the film column instead of being directly electroplated in the first window, the thickness and height of the metal layer formed by electroplating can be reduced due to the existence of the film column, that is, the difficulty of electroplating and the probability of skip plating are reduced, so that a bump with a finer pitch and a higher aspect ratio can be manufactured, and the uniformity of the metal layer can be improved.

The application discloses a kind of non-directional laser sintering interconnection processes, comprising the following steps: step one, select appropriate substrate and chip, and after the substrate and the chip are cleaned, it is pretreated;Step two, interconnection material is placed in chip and substrate as interconnection layer, so that it forms the interconnection structure of chip, interconnection material and substrate;Step three, protective gas is passed, appropriate laser parameters are selected using laser welding machine, and the irradiation direction of laser beam is set, while pressure and ultrasonic are applied and welding time is controlled to weld the interconnection structure;Step four, after cooling at room temperature, the interconnection structure is obtained.Non-directional laser sintering interconnection process, including fine-pitch interconnection and chip die bonding, can reduce the occurrence of substrate warping phenomenon, meet the requirements of advanced packaging, and solve the above technical problems.

To bond multiple dies together at a fine pitch required to achieve a desired interconnect density.SOLUTION: A microelectronic assembly 100 includes: a first layer having dies 114-1 and 114-2 surrounded by an insulating material 133; a second layer on the first layer having conductive paths 196 through a dielectric material, the conductive paths 196 including a conductive trace and a conductive via having an inverted-trapezoid shape; and a third layer on the second layer having a glass layer and a conductive through-glass via (TGV 110), wherein the conductive TGV 110 is electrically coupled to the conductive paths 196, and the dies 114-1 and 114-2 are electrically coupled to the conductive TGV 110 by the conductive paths 196.SELECTED DRAWING: Figure 1A

The invention relates to the technical field of printed circuit board manufacturing, and discloses a method for preparing a refined fine pitch single-sided thick copper circuit board based on a screen printing process, which comprises the following steps of: cutting a single-sided copper-clad plate into a plate material for production when the copper thickness of the single-sided copper-clad plate is 2 ounces; with the conveying direction of subsequent machining of the plate as the reference, the line perpendicular to the conveying direction in the original line is defined as a transverse line, and the line parallel to the conveying direction is defined as a vertical line; according to the requirement that the target line width / line distance is smaller than or equal to 0.15 mm for fine and fine distance, size pre-compensation is conducted on an original line pattern, the compensation amount of a transverse line is 0.025 mm, and the compensation amount of a vertical line is 0.035 mm; and coating anti-etching ink by adopting a silk-screen process, accurately laminating the film drawn with the compensated circuit pattern with a plate material, carrying out silk-screen treatment, and then carrying out curing, etching and film removal treatment. The method has the effect of solving the problem in the prior art that fine and fine pitch lines of 0.15 mm and below are difficult to realize stably and in batches by adopting a silk-screen process on a thick copper single-sided board.

To provide an insert module for an electronic component, including: a pitch adjuster configured to allow an electronic component requiring a test to be seated thereon, and including one side electrically connected to connection pins of the electronic component and another side provided with electrical contact means at a second pitch wider than a first pitch of the connection pins; and a holder configured to be able to hold the seated electronic component.SOLUTION: The insert module for an electronic component and a test tray including the same are capable of accurate contact corresponding to a fine pitch of the electronic component, and can maintain precise contact during a test, thereby capable of improving the accuracy of the test.SELECTED DRAWING: Figure 2

A probe card for use in circuit probe testing and methods of fabrication thereof. The probe card includes a circuit board, an interposer structure that is mounted to the circuit board, and a probe structure mounted to the interposer structure and including a probe substrate, a redistribution layer over the probe substrate, and a plurality of probe pins over the redistribution layer. The interposer structure may include a plurality of elastically-deformable interposer pins electrically connecting the circuit board to the probe substrate. The center-to-center spacing (i.e., pin pitch) between the interposer pins may be greater than the center-to-center spacing (i.e., a second pin pitch) between the probe pins. A probe card in accordance with various embodiments may enable circuit probe testing of a device-under-test with a pitch between adjacent probe pins that is less than 50 μm.

A wire bonding method for forming a vertical wire interconnect structure includes the steps of: forming a wire bond at a bonding pad on a substrate using a wire bonding tool; removing the wire bonding tool from the bonding pad to extend a segment of bonding wire between the wire bonding tool and the wire bond; pressing a point on the section of the bonding wire between the capillary tube and the spherical wire bonding against a part of the wire bonding by using a wire bonding tool so as to form a weakened part of the bonding wire; and straightening the section of bonding wire by moving the wire bonding tool, and enabling the bonding wire to be broken at the weakening part to form the vertical wire interconnection structure.

A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and / or claimed.

An integrated circuit package provides a high bandwidth interconnect between wafers using a very high density interconnect using a silicon bridge or a multi-layer flex between wafers. In some embodiments, more than one wafer may be mounted and connected with a rigid silicon bridge onto a common substrate. This common substrate can be matched, with respect to their coefficients of thermal expansion (CTE), to the silicon wafer. The CTE matched substrate can reduce the thermal mechanical stress on the wafers and the rigid silicon bridge interconnect. In some embodiments, a thinned silicon bridge is utilized to interconnect wafers which are mounted on separate glass substrates. The thinned bridge would allow for mechanical compliance between the wafers. In some embodiments, the wafers can be mounted onto separate glass substrates and attached with a fine pitch multi-layer flex structure which provides compliance between the wafers.

The invention discloses a chemical tin plating solution suitable for fine-pitch high-density interconnection and a preparation method of the chemical tin plating solution, and belongs to the technical field of chemical tin plating. The chemical tin plating solution suitable for fine-pitch high-density interconnection comprises the following components: 12-20 g / L of stannous mono-sulphate, 35-45 mL / L of sulfuric acid, 90-110 g / L of a complexing agent, 30-45 g / L of a reducing agent, 1.2-1.8 g / L of a stabilizer, 1.5-3 g / L of a dispersing agent, 0.8-1.2 g / L of a surfactant, a pH regulator and water. The invention also provides a preparation method of the composition. Compared with the prior art, the dispersing agent is obtained through condensation and sulfonation of the ketone-containing monomer and the formaldehyde, and wettability is improved after sulfonation, so that the blind hole filling problem of fine-pitch electroplating can be solved, and the tin plating solution can form a uniform and stable tin protection layer in a tiny bonding pad and dense wiring environment.

An integrated circuit (IC) package includes a package substrate, a first die over the package substrate, a stack of a first material and a second material over the first die, where the first material is between the first die and the second material and the second material includes an organic passivation material, interconnect structures including vias on the first die and extending through the first and second materials and conductive bumps on the second material, and a second die over the first die and connected to the first die via the interconnect structures, where a taper angle between an inner portion of a side wall of one of the vias and a plane parallel to a bottom opening of the one of the vias is less than or equal to 90 degrees.

To provide a package substrate with a new structure, a package substrate that is easy to adapt to fine pitches, and a manufacturing method thereof.SOLUTION: A package substrate 100 includes a first outer circuit pattern 120 arranged on the upper surface of an insulating layer 110, a second outer circuit pattern 125 arranged on the lower surface of the insulating layer, a first connecting portion 170 arranged on the upper surface of the 1-1 circuit pattern of the first outer circuit pattern, a first connection portion 180 arranged on the first connecting portion, a first element 200 arranged on the first connecting portion via the first connection portion, a second connection portion 185 arranged on the lower surface of the 2-1 circuit pattern of the second outer circuit pattern, a second element 300 attached to the 2-1 circuit pattern via the second connection portion, and a second connecting portion 175 arranged on the lower surface of the 2-2 circuit pattern of the second outer circuit pattern, and the first connecting portion has a first width and a first spacing, and the second connecting portion has a second width greater than the first width and a second spacing greater than the first spacing.SELECTED DRAWING: Figure 2

Vertical die to die (D2D) interconnected chiplets on a glass core. The chiplets are two different integrated circuit dies, often considered “hot” dies, and called top dies herein. The glass core includes a cavity. An active I / O die is in the cavity to provide the D2D communication, its top surface flush with the upper surface of the glass core. Two different sized micro-bumps are used, the first micro-bumps have a smaller pitch (e.g., “fine pitch”) and are to attach the top dies to the top surface. The second micro-bumps are larger than the first (e.g., “coarse pitch”), and are to attach the top dies to the upper surface of the glass core. An organic build, and solder ball backside may be fabricated on the lower surface of the glass core.

A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

The present invention discloses a high-density and low-porosity graphite crucible special for crystal growth furnaces and a preparation method thereof. Graphene powder, graphite powder and ultra-fine pitch coke are used as aggregates. The aggregates and ultra-fine pitch powder are dispersed at low temperature and kneaded at high temperature to prepare a paste, which is crushed into pressed powder. The pressed powder is subjected to pre-forming, isostatic pressing, carbonization, impregnation, graphitization and machining to prepare a graphite crucible meeting the requirements of crystal growth furnaces. By introducing nano-scale and micro-scale microstructure regulators, on the one hand, the interfacial bonding property of raw materials is improved and the microstructure of the product is optimized; on the other hand, the structure regulator, as a reinforcing agent, strengthens the structural support force of the graphite crucible and also prevents the intercalation corrosion of the graphite crucible by silicon vapor under high-temperature conditions, effectively improving the structural stability and service life of the graphite crucible. In addition, the main raw materials of the present invention are industrial semi-finished products in the coal chemical industry or petrochemical industry, with wide sources and low prices, and are suitable for large-scale batch production.