491results about "Stacked capacitors" patented technology

This invention provides an X9R type MLCC ceramic powder based on chitosan oligosaccharide-assisted solid-phase synthesis and its preparation method, relating to the field of multilayer chip ceramic capacitor technology. The X9R type MLCC ceramic powder of this invention is prepared using a chitosan oligosaccharide-assisted solid-phase method, and the powder is Ba... 0.985‑y‑ z Bi 0.01 La y Dy z Ti 1‑a‑b‑c Mg a Ho b Ca c O3, where y=0-0.01, z=0-0.01, a=0-0.02, b=0-0.02, c=0.005-0.02; the c / a axis ratio of the powder is ≥1.009, exhibiting a highly tetragonal perovskite structure. The powder prepared by this invention has a dielectric constant ≥12000 (1 kHz), dielectric loss <0.03 (1 kHz), breakdown voltage ≥100 kV / cm, sintering temperature ≤1250℃, and temperature characteristics that meet the EIA X9R standard. This invention introduces chitosan oligosaccharide as a dispersant and complexing agent based on the traditional solid-phase method, combining the advantages of the simplicity of the solid-phase method and the good uniformity of the liquid-phase method. The synthesis process is simple, the batch stability is high, and it can be applied on a large scale.

To provide a multilayer electronic component that offers excellent heat dissipation performance while also possessing superior mechanical strength and equivalent series resistance (ESR) characteristics. [Solution] A stacked electronic component according to one embodiment of the present invention includes a body 110 including a dielectric layer 111 and internal electrodes 121 and 122 arranged alternately with the dielectric layer, external electrodes 130 and 140 arranged on the body and connected to the internal electrodes, and interface layers 151 and 152 arranged between the body and the external electrodes, wherein the interface layers include an oxide containing a crystalline conductive metal. A plurality of interface layers are arranged, and the plurality of interface layers are spaced apart from each other in a direction in which the dielectric layer and the internal electrodes are arranged alternately.

A multilayer electronic component according to an example embodiment of the present disclosure may include: a body including a dielectric layer and internal electrodes alternately disposed with the dielectric layer in a first direction, and including first and second surfaces opposing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction; a protrusion portion disposed on the first and second surfaces; and an external electrode disposed on the third and fourth surfaces, wherein a width of the body in the third direction is W and a width of the protrusion portion in the third direction is W1, W1 / W may be 0.5 or more and 0.85 or less.

A multilayer ceramic capacitor includes a multilayer body and three or more external electrodes. A first internal electrode layer includes a first counter electrode portion, a first extension portion, and a second extension portion. The first counter electrode portion includes a first central region, a first connection region connected to the first extension portion, and a second connection region connected to the second extension portion. Coverages of the first and second connection regions with respect to the dielectric layers are higher than a coverage of the first central region with respect to the dielectric layers, and coverages of the first and second extension portions with respect to the dielectric layers are higher than the coverage of the first central region with respect to the dielectric layers.

The disclosure provides a multilayer ceramic electronic component including: a ceramic main body including a capacitance forming part, an edge part, and a cover part, the capacitance forming part including a dielectric layer, a first internal electrode, and a second internal electrode, the first and second internal electrodes being disposed to be stacked in a third direction with the dielectric layer interposed therebetween, the edge part being disposed on both surfaces of the capacitance forming part in a second direction, the cover part being disposed on both surfaces of the capacitance forming part in the third direction; first and second external electrodes disposed on first and second surfaces of the ceramic main body opposite to each other in a first direction, respectively; and an auxiliary electrode spaced apart from the capacitance forming part and disposed to be in contact with one of the first and second external electrodes. The auxiliary electrode is spaced apart from the first and second surfaces of the ceramic main body in the first direction.

The application discloses a method for improving the lamination bubble of MLCC, comprising the following steps: mixing porcelain powder, organic solution, dispersing agent, adhesive and other auxiliary agents in a certain proportion to prepare porcelain slurry required for subsequent preparation; performing electrode printing after the casting operation of the porcelain slurry is completed; performing stacking after the film is peeled off, and forming a bubble discharge channel in the lamination process; performing uniform pressing on the film after the above operation is completed; and cutting each group of films to obtain the finished product; the method changes the morphology structure of the cast film by adjusting the ingredient process parameters and the formula, and forms the bubble discharge channel in the lamination process. Thus, the occurrence of the lamination bubble is inhibited, and in the packaging and uniform pressing process, the residual micro-bubbles can be effectively discharged from the bar block before the bar block is softened and pressed again, so that the layers of the bar block are fully pressed together, and the bar block delamination or cutting delamination caused by the local gas aggregation and residual is avoided.

A multilayer ceramic capacitor includes a multilayer body including dielectric layers, inner electrode layers on the dielectric layers, first through sixth surfaces, a first inner electrode layer on the dielectric layers and extended to the third and fourth surfaces, a second inner electrode layer on the dielectric layers and extended to the fifth and sixth surfaces, a first outer electrode on the third surface and connected to the first inner electrode layer, a second outer electrode on the fourth surface and connected to the first inner electrode layer, a third outer electrode on the fifth surface and connected to the second inner electrode layer, and a fourth outer electrode on the sixth surface and connected to the second inner electrode layer. The first outer electrode includes a first turn-up portion and the second outer electrode includes a second turn-up portion, each covering portions of the fifth and sixth surfaces.

Providing a slurry composition excellent in dispersion stability and drying rate. 【Solution means】The present invention is a slurry composition containing a dielectric material, a polymer, and a solvent, wherein the solvent is represented by the following formula (A): R 1 =O (A) [In formula (A), R 1 is a divalent alicyclic hydrocarbon group.] a ketone solvent A represented by, and the following formula (B): R 2 -O-R 3 (B) [In formula (B), R 2 is a monovalent alicyclic hydrocarbon group, and R 3 is a monovalent hydrocarbon group.] It is a slurry composition containing at least one of an ether solvent B represented by, and the total ratio of the ketone solvent A and the ether solvent B in the whole solvent is 50% by mass or more.

Method for producing a dielectric for a capacitor, method for producing a capacitor and capacitor The present application relates to a method for producing a dielectric for a capacitor, a method for producing a capacitor, and a capacitor. The method includes the production of a polymer chain from a monomer by polymerization. In this method, some repeat units in the polymer chain are functionalized with a reactive group. The reactive groups are branched from each polymer chain. Furthermore, the reactive groups are suitable for reacting with a linker molecule. The reactive groups are thus suitable for forming a covalent bond with the linker molecule. As a further method step, linker molecules are added to the polymer chain, each linker molecule having at least two chemical connection points, each of which is suitable for forming a covalent bond with a reactive group. Finally, cross-linking of the polymer chain is achieved by reaction of the linker molecules having two reactive groups.

A device according to some embodiments includes a first IPD die including a first SiC substrate. The first IPD die has a first surface and a second surface on the first SiC substrate opposite the first surface and includes a first contact and at least one first metal portion on the respective surfaces of the first SiC substrate. The device further includes a second IPD die including a second SiC substrate. The second IPD die has a third surface and a fourth surface on the second SiC substrate opposite the third surface and includes a second contact and at least one second metal portion on the respective surfaces of the second SiC substrate. The device further includes an electrical interconnection structure between one of the first and second surfaces of the first IPD die and one of the third and fourth surfaces of the second IPD die.

A multilayer ceramic electronic component includes internal electrode layers facing each other in a predetermined direction, dielectric layers laminated between the internal electrode layers; and a pair of external electrodes electrically connected to the internal electrode layers. At least one of the dielectric layers includes a first crystal grain as a main component ceramic having a perovskite structure represented by a general formula ABO3, and a second crystal grain whose main component is a barium titanate complex oxide in which an elemental ratio of barium to titanium is 0.70 or less. The second crystal grain is in contact with at least one of a pair of the internal electrode layers sandwiching the at least one of the dielectric layers.

The utility model discloses a new energy automobile battery swap station's PCB board 4 pin film capacitor, including plastic shell and the capacitor body of encapsulation in plastic shell, capacitor body includes the capacitor core that is composed of multiple single core and the laminated busbar that is connected with capacitor core through soldering tin, and the laminated busbar is connected with two outgoing terminals, and each outgoing terminal has two parallel interval opposite pins and the connecting portion of connecting two pins, and the connecting portion is integrally formed with two pins and is combined into U shape, and the pin stretches out plastic shell outside, and the connecting portion of each outgoing terminal is welded and connects the laminated busbar. Through setting laminated busbar, U type outgoing terminal, multiple core combination arrangement capacitor core in the inside of plastic shell, the soldering connection process that laminated busbar is used with electric core, makes capacitor presents high stable ESL, ESR parameter on high frequency resonance road, and the current capacity of capacitor improves self heating little, and circuit output high quality steady voltage waveform.

Provided is a laminated ceramic electronic component with high moisture resistance reliability. The laminated ceramic capacitor includes a laminate (10) including a plurality of ceramic layers (20) and a plurality of internal conductor layers (30), and a pair of external electrodes (40) disposed at both ends in a length direction (L) of the laminate, the internal conductor layers including a first internal conductor layer (31) and a second internal conductor layer (32), the external electrodes including a first external electrode (40A) including a first base electrode layer (50A) connected to the first internal conductor layer, and a second external electrode (40B) including a second base electrode layer (50B) connected to the second internal conductor layer, the first base electrode layer and the second base electrode layer having a metal portion (70) and a plurality of non-metal portions (80) present within the metal portion, in a cross section perpendicular to a width direction (W), an average area of the non-metal portions in a first total body constituted by the non-metal portions with a circularity of 0.4 or less is 12 μm 2 The following.

A multilayer capacitor and a method of manufacturing the multilayer capacitor including a capacitor body including a dielectric layer and an internal electrode layer, and an external electrode disposed on an outer surface of the capacitor body, wherein the dielectric layer includes a composite dielectric material including a polyvinylidene fluoride (PVDF)-based compound and a carbon-based material, and the external electrode includes an electrode layer including an intermetallic compound (IMC) including copper (Cu) and tin (Sn), and a thermosetting epoxy resin.

A multilayer electronic component includes a multilayer body and external electrodes each located on a corresponding one of a third surface or a fourth surface of the multilayer body. The external electrodes each include a Ni plated layer and an Au plated layer on the Ni plated layer. Gaps exist between the Ni plated layer and the Au plated layer. An existence ratio of the gaps is about 0.05% or less.

A three-terminal multilayer ceramic capacitor includes end-surface external electrodes on end surfaces, and a side-surface external electrode on at least one side surface. An internal electrode includes an end-surface exposed internal electrode exposed on an end surface and connected to the end-surface external electrode, and a side-surface exposed internal electrode on a side surface and connected to the side-surface external electrode. A lengthwise dimension of the side-surface external electrode satisfies about 0.10 mm<Li<about 0.25 mm, and a total dimension Lall and a total dimension Wall satisfy a relationship of about 0.4 Wall≤Lall≤about 1.0 Wall.

This semiconductor capacitor includes a substrate, a first capacitor, and a second capacitor. The substrate has a first main surface, and a first groove and a second groove are formed at different positions on the first main surface. The first capacitor includes a first laminated structure in which two or more first dielectric films and two or more first conductive films are alternately laminated at least on an inner surface of the first groove. The second capacitor includes a second laminated structure in which two or more second dielectric films and two or more second conductive films are alternately laminated on at least the inner surface of the second groove. The first capacitor and the second capacitor are connected in series.

A trench capacitor includes a plurality of unit trench capacitors arranged in a 2D repetitive pattern in a substrate. The unit trench capacitors are separated by elongated trenches or elongated walls between the unit trench capacitors. The trench capacitor includes a plurality of stress compensation elements. Each unit trench capacitor has one or more closed trenches, with each trench further having a bottom electrode, a top electrode, and a dielectric between the bottom electrode and the top electrode. The unit trench capacitors are connected in parallel and the stress compensation elements are arranged between the unit trench capacitors such that they interrupt the elongated walls or trenches.

A stacked capacitor assembly and a stacked capacitor packaging structure. The stacked capacitor packaging structure includes a stacked capacitor assembly, an electrode assembly and an insulating package body. The stacked capacitor assembly includes a plurality of conductive substrates. The insulating package body can cover the stacked capacitor assembly and carry the electrode assembly. The conductive substrates can conform to the following formula: H=nt+(n−1) d, in which H is a total thickness of the conductive substrates, n is the number of the conductive substrates, t is a thickness of each conductive substrate, and d is a distance between two adjacent conductive substrates. The number of the conductive substrates is between 2 and 30, the thickness of each conductive substrate is between 80 μm and 150 μm, the distance between the two adjacent conductive substrates is between 0.05 μm and 30 μm, and the ratio d / H is between 0.35 and 350.

To provide a method for solving the problem of a low capacitance value at high voltage in a tunable multilayer capacitor.SOLUTION: A multilayer capacitor comprises a first active electrode 14 in electrical contact with a first active termination 16, and a second active electrode 20 in electrical contact with a second active termination 18. The capacitor comprises a first DC bias electrode 22 in electrical contact with a first DC bias termination 30, and a second DC bias electrode 26 in electrical contact with a second DC bias termination 32. Multiple dielectric layers 12 are disposed between the first and second active electrodes and between the first and second bias electrodes. At least a portion of the dielectric layers contains a tunable dielectric material that exhibits a variable dielectric constant upon application of an applied DC voltage across the first and second DC bias electrodes. The thickness of at least one of the multiple dielectric layers is greater than about 15 micrometers.SELECTED DRAWING: Figure 2A

The application relates to the technical field of polypropylene films, and discloses a preparation method and application of a double-sided metallized polypropylene film, which comprises the following steps: polypropylene film is subjected to corona stretching grafting treatment to obtain a surface-modified polypropylene film; the surface-modified polypropylene film is sequentially immersed in a sensitization liquid and a chemical plating liquid, hydrazine hydrate is added to the chemical plating liquid for reduction, a chemical plating film is obtained; a single-cathode and double-anode electroplating tank is used, the chemical plating film is used as a cathode, a corresponding metal plate is used as an anode, the chemical plating film is immersed in an electroplating liquid for electroplating, and a double-sided metallized polypropylene film is obtained. The process of the application strengthens the interface combination through the synergistic effect of corona stretching grafting modification, realizes uniform and dense plating layers on both sides by combining chemical plating with double-anode electroplating, and improves the adhesion, conductivity and uniformity of the double-sided thickness, so the application can be widely applied to film capacitors.

This utility model discloses a multilayer ceramic capacitor and its assembly. The multilayer ceramic capacitor includes a ceramic body and multiple external electrodes. The ceramic body includes multiple dielectric layers and internal electrodes, and is used to form at least two sub-capacitors with different capacitance values. Each sub-capacitor contains an independent set of internal electrodes. Multiple external electrodes are disposed on the end face and / or side face of the ceramic body, and are electrically connected to corresponding internal electrodes. The external electrodes and electronic components are connected and coupled in different ways to allow the multilayer ceramic capacitor to selectively form multiple different capacitance values. The multilayer ceramic capacitor of this application can meet the requirements of various capacitance values ​​required by circuits, and can greatly reduce the number of multilayer ceramic capacitors used. This not only reduces manufacturing costs and production time, but also reduces the space occupied by electronic components, which is beneficial to the flexibility, compactness and miniaturization of electronic component design.

To provide films for manufacturing electronic components that can prevent occurrence of static electricity during the production process; to provide films for manufacturing electronic components that allow an increase in cooling efficiency during the production process; to provide films for manufacturing electronic components having uniform thickness; and films for manufacturing electronic components that allow easy peeling of ceramic sheets while electronic components are made and also allow the electronic components to be made without damage.SOLUTION: An example of the present invention provides a film 10 for manufacturing electronic components that includes a polymer layer and metal nanowires 112 dispersed in the polymer layer.SELECTED DRAWING: Figure 3

A multilayer electronic component according to an embodiment of the present disclosure includes a body including g a capacitance formation portion including a dielectric layer including (Ba, Ca)TiO3 and BaTiO3 as a main component and an internal electrode alternately disposed with the dielectric layer; and an external electrode disposed on the body, wherein, if a secondary phase including calcium (Ca) and titanium (Ti) and in which an atomic percentage of a rare earth element is 0.1 at % or more is referred to as a first secondary phase, the dielectric layer includes the first secondary phase, and based on a cross-sectional area of the capacitance formation portion, an area percentage of the first secondary phase included in the dielectric layer, excluding the internal electrode, is more than 0% and less than 4.58%.

We provide stacked electronic components with excellent capacity and reliability. [Solution] A stacked electronic component according to one embodiment of the present disclosure includes a body including a dielectric layer and internal electrodes arranged alternately with the dielectric layer in a first direction, and external electrodes disposed on the body and connected to the internal electrodes, wherein at least one of the dielectric layers includes a perovskite compound represented by the general formula ABO3 and a perovskite layer including first crystal grains that do not have a core-shell structure, and auxiliary layers disposed on both sides of the perovskite layer facing the first direction and containing a first doping element, the first doping element may include one or more of Dy, Ho, Y, Er, Gd, Tb, Mg, Mn, V, Al, and Si.

We provide highly reliable stacked electronic components. [Solution] The stacked electronic component 100 includes a capacitance forming section including a dielectric layer and internal electrodes alternately arranged in the dielectric layer in a first direction X, a main body 110 including a first and second surface facing each other in a first direction X, a third and fourth surface connected to the first and second surfaces and facing each other in a second direction Y, a fifth and sixth surface connected to the first, second, third and fourth surfaces and facing each other in a third direction Z, external electrodes 131 and 132 arranged on the third and fourth surfaces respectively, and side margin sections 114 and 115 arranged on the fifth and sixth surfaces respectively. When the number of moles of Mn and Mg per 100 moles of Ti contained in the side margin section is S1 and S2, respectively, and the number of moles of Mn and Mg per 100 moles of Ti contained in the dielectric layer of the capacitance forming section is A1 and A2, respectively, the following conditions are met: 0.2 moles ≤ S1 - A1 ≤ 0.8 moles and S2 - A2 < 0.25 moles.

A multilayer ceramic electronic device includes a dielectric layer including a main phase and a segregated material containing a first rare earth element, a second rare earth element and magnesium, a plurality of internal electrode layers sandwiching the dielectric layer, and external electrodes electrically connected to the plurality of internal electrode layers respectively.

A multilayer ceramic capacitor includes: a capacitor body including dielectric layers, and first and second internal electrodes alternately disposed in the first direction with the dielectric layers interposed therebetween; and external electrodes including base electrodes disposed on outer sides of the capacitor body and connected to the first and the second internal electrodes, and conductive resin layers disposed on outer sides of the base electrodes. The external electrodes include: connection portions; side portions extending from the connection portions; first band portions including first portions extending from the connection portions, and second portions extending from the first portions to the side portions; and second band portions extending from the connection portions and then extending to the side portions, and the conductive resin layers disposed in the second portions of the first band portions include protruding portions that protrude further than the first portions along the first direction of the capacitor body.