575results about How to "Reduce leakage current" patented technology

The invention discloses a manufacturing method of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric integration technology capable of eliminating a buffer layer. The manufacturing method comprises the following steps: depositing a back gate electrode and a back gate dielectric on a substrate in sequence; transferring the channel layer to the back gate medium; sequentially forming a buffer layer, a source electrode, a drain electrode, a top gate dielectric layer formed by a high-k dielectric material and a top gate electrode on the channel layer; and annealing treatment is carried out in a vacuum environment, and the buffer layer sublimates, so that Van der Waals interfaces are formed between the channel layer and the top gate dielectric layer and between the channel layer and the source electrode as well as between the channel layer and the drain electrode. According to the high-k gate dielectric integration technology based on the erasable buffer layer, the erasable buffer layer after vacuum annealing is utilized, damage to a two-dimensional material is avoided, a high-quality high-k gate dielectric is deposited, interface regulation and control between a channel layer and a top gate dielectric are achieved, and the equivalent oxide thickness is reduced; and good contact between the channel layer and source and drain metal is realized, the contact resistance of the transistor is reduced, and the electrical performance of the transistor is improved.

The invention provides a superlattice infrared detector chip manufacturing method, and belongs to the technical field of infrared detector manufacturing. The problem that the product performance or the product yield is low due to the fact that the precision fluctuation of the photoetching technology when the hard mask is removed is not considered in the current hard mask removing scheme is solved; comprising the following steps: forming a hard mask: growing the hard mask with a certain thickness on the surface of a wafer made of a superlattice material; photoetching an upper electrode table top; etching a hard mask: taking the photoresist as a mask, and etching the hard mask by adopting an ICP (Inductively Coupled Plasma) technology to obtain an upper electrode mesa mask pattern; degumming and cleaning an upper electrode table board; photoetching a lower electrode table board: adopting photoresist as a mask of a lower electrode table board area, and manufacturing the lower electrode table board area through a photoetching technology; carrying out ICP etching on the table board; performing wet etching on the table board; degumming and cleaning a lower electrode table board; forming a passivation layer film; opening holes in the passivation layer; manufacturing a gold electrode; the method is applied to preparation of the superlattice infrared detector chip.

The invention relates to a preparation method of a memory cell and a memory, and relates to the technical field of integrated circuit design and manufacturing, the memory cell comprises an active column, a capacitor, a first grid electrode and a second grid electrode, the active column has a first end surface and a second end surface deviating from each other along a first direction, and the first end surface is used for being connected with a bit line; the active column internally comprises a first doped region, a channel region and a second doped region which are sequentially arranged along a first direction, the channel region is provided with a first outer surface and a second outer surface which are deviated from each other along a second direction, and the channel region internally comprises a stress structure which penetrates through the active column along a third direction; the first direction and the second direction intersect and are perpendicular to the third direction; the capacitor covers the second end surface and circumferentially surrounds part of the side surface of the active column; the first grid electrode is located on the first outer surface of the channel region; the second grid electrode is located on the second outer surface of the channel region, and the performance and reliability of the memory cell can be improved at least under the condition that the size of the memory cell is reduced.

The invention discloses a display panel, a preparation method thereof and a display device. The display panel comprises an array substrate and a plurality of light-emitting elements located on one side of the array substrate. The light-emitting element comprises a light-emitting functional layer, a first electrode and a second electrode; the display panel further comprises a pixel definition layer. The pixel definition layer comprises pixel openings and pixel interval openings. The pixel opening is configured to expose the first electrode; pixel spacing openings are located between adjacent pixel openings, and the pixel spacing openings are configured to expose the partition grooves; at least one film layer in the light-emitting functional layer is disconnected at the position of the partition groove; the pixel spacing opening comprises a first edge and a second edge; the first edge and the second edge are arranged in the direction perpendicular to the extending direction of the pixel interval opening; the first edge and / or the second edge are / is provided with a sawtooth structure. By adopting the technical scheme, the phenomenon of secret lighting among the sub-pixels can be improved, and the reliability and the yield of the display panel are improved.

The invention discloses a tunneling gate HEMT device, a preparation method, a chip and electronic equipment. The device structurally comprises a substrate layer, a transition layer, a buffer layer, a channel layer and a barrier layer, wherein the transition layer, the buffer layer, the channel layer and the barrier layer are sequentially located on the substrate layer; the p-GaN layer is located on the barrier layer; the isolation structure is located on the side wall of the HEMT device, and the isolation structure penetrates through the barrier layer and the channel layer and is located on the buffer layer; the passivation layer is located on the side wall of the p-GaN layer and on the barrier layer; the tunneling layer is positioned at the bottom and the side part of the grid opening area of the passivation layer; the grid electrode penetrates through the passivation layer and is positioned on the tunneling layer; and the source electrode and the drain electrode are respectively located at different sides of the p-GaN layer, and the source electrode and the drain electrode respectively penetrate through the passivation layer and are located on the barrier layer. Compared with the prior art, a layer of thin medium is deposited in the groove of the grid electrode to serve as the tunneling layer, so that the breakdown voltage of the grid electrode of the HEMT device is effectively improved.

The invention discloses a homogeneous pn junction terminal gallium oxide Schottky barrier diode and a preparation method thereof. The problems that gallium oxide p-type doping is difficult, and heterojunction electric leakage is high and voltage resistance is low are solved. The semiconductor device comprises a cathode, an n-Ga2O3 substrate and an n-Ga2O3 epitaxial layer from bottom to top, ion implantation regions are arranged at the left end and the right end of the upper surface of the n-Ga2O3 epitaxial layer, and the upper surface of the n-Ga2O3 epitaxial layer is covered with an anode; the ion implantation region is subjected to annealing treatment to form a p-type Ga2O3 region, and the p-type Ga2O3 region and the n-Ga2O3 epitaxial layer form a homogeneous pn junction terminal, so that the gallium oxide Schottky barrier diode with high voltage resistance and low electric leakage is realized. The preparation method comprises the steps of cleaning an epitaxial wafer, photoetching to form a region to be implanted with ions, carrying out ion implantation, cleaning, carrying out rapid thermal annealing to form p-Ga2O3, and preparing a cathode and an anode. According to the invention, N / P ions are injected, annealing treatment is carried out, a gallium-oxygen-nitrogen-phosphorus compound with a p-type characteristic is generated in the n-Ga2O3 epitaxial layer, and the homogeneous pn junction terminal gallium oxide Schottky barrier diode is realized. The method can be used in high-voltage and high-power fields such as power grids and high-speed rails

The invention discloses a gallium oxide-based MOSFET device and a preparation method thereof, and relates to the field of semiconductor devices. The device has the characteristics of high voltage resistance and low electric leakage, and comprises a conductive region and an edge terminal region connected with the conductive region, the conductive region comprises a first drain metal layer, a first gallium oxide substrate, a first gallium oxide epitaxial layer, a gallium oxide current barrier layer and a highly-doped gallium oxide N + region which are sequentially stacked from bottom to top, and a groove which is positioned on the surface of the highly-doped gallium oxide N + region and of which the bottom is propped against the first gallium oxide epitaxial layer; the conductive region further comprises a first p-type semiconductor buried layer located at the bottom and on the side wall of the groove, a gate dielectric layer located on the surface of the first p-type semiconductor buried layer, the side wall of the groove and the surface of the highly-doped gallium oxide N + region, and a gate metal layer located on the surface of the gate dielectric layer. The first interlayer dielectric layer covers the surface and the side face of the gate metal layer and the side face of the gate dielectric layer, and the source metal layer is located on the surface of the first interlayer dielectric layer and the surface of the highly-doped gallium oxide N + region.

The invention relates to the field of nonvolatile memories, in particular to an SOT-MRAM circuit unit based on a 2T2M differential structure and a storage array circuit of the SOT-MRAM circuit unit. The SOT-MRAM unit comprises a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first phase inverter, a second phase inverter, a write line, a read line, an input line and an output line which have a specific connection relation. According to the SOT-MRAM circuit unit, through the special 2T2M differential structure design and in combination with the excellent performance of a spin-orbit moment magnetic tunnel junction, the storage and operation performance and efficiency of a 2T2MSOT-MRAM differential circuit unit array are integrally improved, the dependence on the performance of the MTJ is reduced, the SOT-MRAM circuit unit has the better energy efficiency ratio and the more stable read-write speed and precision, and the SOT-MRAM circuit unit has the advantages of being simple in structure, low in cost and high in reliability. And the reliability and the stability are excellent.

The invention relates to the technical field of tube shell cleaning processes, in particular to a novel tube shell cleaning method. The method has the advantages that hydrochloric acid and hydrogen peroxide are proportioned in the first solution, the tube shell is placed in the solution for oxidation reaction, smudginess, oxidation parts and ceramic smudginess parts on the metal surface fall off, then hydrochloric acid is used for certain dilution, reduction reaction is carried out on the tube shell, dry printing traces and oxidation parts on the surface of the tube shell are removed, and the tube shell is obtained. Cleaning is carried out in the midway under flowing deionized water, it is ensured that residual liquid on the surface of the tube shell is cleaned away, impurities adsorbed on the surface of the tube shell are removed through ultrasonic cleaning, oxidized dirt on the surface of the tube shell can be removed in an acid pickling mode, and the tube shell can strongly react with a prepared solution of acid and hydrogen peroxide; and small burrs at some unobservable positions and observable positions of the tube shell react with the tube shell, so that the burrs are shortened or eliminated, and the lengths of the burrs which cannot be eliminated are shortened while the diameter of the tip is increased.

According to the preparation method for the positive electrode material of the aluminum electrolytic capacitor, the base material aluminum foil is not fully coated with the aluminum powder slurry, but blank areas are reserved on the left side and the right side, the blank areas are coated with a layer of anti-sticking slurry containing oxide particles or ceramic particles with the melting point higher than that of aluminum, and the melting point of the particles is higher than that of the aluminum; diffusion among aluminum atoms can be effectively blocked, an anti-sticking layer is formed, and adhesion between adjacent aluminum foil layers is prevented; due to the use of the anti-sticking slurry, the adhesive force between the aluminum foil layers is reduced, so that the occurrence of tearing and wrinkling in the processes of coil dividing, sintering, formation and subsequent treatment is reduced, the reliability of the aluminum electrolytic capacitor is improved, and the service life of the aluminum electrolytic capacitor is prolonged; according to the anti-adhesion sintered foil manufactured through the method, the width of the blank area is preferably 5-20 mm, and the design guarantees the sufficient anti-adhesion effect and does not affect the effective use area of the aluminum foil.

The invention provides an erasing method of a flash memory unit. The flash memory cell includes a memory transistor and a gate transistor connected in series. The erasing method comprises the steps that erasing voltages are applied to electrodes of the flash memory unit and gate electrodes of transistors, the erasing voltages applied to the gate electrodes of the erased memory transistors are lower than second power supply voltages, and therefore the channel hot electron induced hot hole injection physical effect occurs. Therefore, hot holes in the channel are attracted into the storage medium layer to realize erasing. Compared with the existing band-to-band tunneling hot hole (BBHH) erasing method, the erasing method of the flash memory unit disclosed by the invention has wider hole distribution and higher injection efficiency, so that the erasing method disclosed by the invention has higher erasing speed, larger erasing window, smaller hot carrier damage, lower leakage current and higher durability and reliability.

The utility model provides a high-reliability SIC-MOSFET terminal structure, belonging to the technical field of semiconductor devices, the high-reliability SIC-MOSFET terminal structure comprises a source electrode and a drain electrode, the source electrode is the input end of an MOSFET and is used for current in a circuit to enter, and the drain electrode is the output end of the MOSFET and is used for exporting current; a groove and a grating are arranged between the source electrode and the drain electrode, the structure among the source electrode, the drain electrode, the groove and the grating is a FinFET structure, the source electrode and the drain electrode are fixedly connected through the middle groove and the grating, the groove is fixedly connected with the grating, the groove comprises a first groove and a second groove, and the first groove and the second groove are communicated with each other. The first groove is fixedly connected with the source electrode. The problem that an existing SIC-MOSFET0 is prone to being broken down under the conditions of high voltage and high current can be solved.

The invention provides an inverter and a leakage current suppression method in a relay self-checking process thereof, and the method comprises the steps: controlling an inverter circuit to output an inverter voltage synchronous with a power grid voltage when one of a main relay and a slave relay of a null line branch is closed, and enabling the null line branch to be switched on because the null line branch is not switched on; no current path exists between the input end of the inverter circuit and the ground, and almost no current passes through the two first capacitors, so that the leakage current is very small. And when the voltage values at the two ends of the relay of which the null line branch is disconnected are within the target range, the main relay and the slave relay of the null line branch are controlled to be closed, so that the impact current generated when the relays are closed can be reduced. Therefore, the leakage current of the inverter can be effectively reduced, misoperation of the leakage current protector is prevented, and the working stability of the inverter is improved.

The invention discloses a self-adaptive filtering device for electromagnetic noise amplitude detection and a working method of the self-adaptive filtering device, and a detection circuit is characterized in that a sampling resistor R and a capacitor C are connected in series and then are connected to an optocoupler circuit, and a diode protection optocoupler is reversely connected in parallel to the primary side of the optocoupler and is connected to a digital signal controller. The detection circuit is realized by an RC circuit and a voltage transformer, an electromagnetic noise signal in a power loop is coupled by the voltage transformer, conditioned and amplified by an operational amplifier and then sent to an AD sampling pin of the controller, and the controller compares the detected noise amplitude with a set threshold value and controls the on-off of Ry1-Ry6 according to a calculation result. The device can also detect the electromagnetic noise amplitude of the power loop in real time through an optocoupler circuit and a digital signal controller, and actively control the filter parameters according to the noise amplitude. Therefore, the device not only can effectively reduce electromagnetic noise, but also can save energy, reduce reactive power content and reduce leakage current, so that the risk of electric shock caused by poor grounding is avoided.

The invention discloses a low leakage current enabling control circuit and method suitable for a high-voltage LDO, the low leakage current enabling control circuit comprises a bias unit, a turn-off unit and an output unit, and the output end of the bias unit is connected with the input end of the turn-off unit to provide static bias current for the turn-off unit; the output end of the turn-off unit is connected with the input end of the output unit to provide a controllable high-voltage domain power supply for the output unit, and the first output end of the output unit is connected with the first input end of the low-voltage circuit module to provide a low-voltage domain power supply for the low-voltage circuit module. And the second output end of the output unit is connected with the second input end of the low-voltage circuit module and is used for controlling the enabling and turn-off of the low-voltage circuit module. According to the invention, the isolation degree of the chip in the disable state is improved, and the leakage current of the chip in the disable state is effectively reduced.

The invention provides a display device which comprises a plurality of cascaded gate drive circuits, and each gate drive circuit comprises two pull-down sub-circuits. Each pull-down sub-circuit includes an inverter and a pull-down maintenance unit, wherein the inverter includes a reset transistor and a plurality of transistors. The two pull-down sub-circuits are configured to alternately output low-level power supply signals to the second node in a period of a preset duration, and the preset duration is in a range from the duration of a driving period of 160 frames of pictures to the duration of a driving period of 240 frames of pictures. Through the combined action of the plurality of transistors in the inverter, the grid voltage of the transistor connected with the second node is reduced, and the working time of each pull-down sub-circuit is reduced through the alternate working mode of the double pull-down sub-circuits; therefore, the problems of electric leakage and stability in the gate drive circuit of the high-mobility oxide semiconductor thin film transistor are effectively solved.

The invention provides a preparation method of a special aluminum electrolytic capacitor for a low-temperature-resistant detonator trigger, and the method comprises the following steps: cutting a positive electrode foil and a negative electrode foil, and riveting the cut positive electrode foil and negative electrode foil with a positive guide pin and a negative guide pin; placing electrolytic paper between the riveted positive electrode foil and negative electrode foil, winding the electrolytic paper to form a core package, injecting electrolyte into the core package, and sealing the core package in an aluminum shell by using colloidal particles to obtain a semi-finished capacitor; and cleaning the semi-finished product capacitor, sleeving, and sequentially carrying out primary aging sorting, secondary aging sorting, appearance observation and inspection to obtain the capacitor. The preparation method of the aluminum electrolytic capacitor special for the low-temperature-resistant detonator trigger is simple in production process, common in material and low in price, and the prepared aluminum electrolytic capacitor is excellent in electrical performance, wide in working temperature range and small in size.

The invention discloses a p-Ga2O3 / n-Ga2O3pn junction diode and a preparation method thereof, and solves the problems that gallium oxide p-type doping is difficult, and a heterojunction diode is large in leakage current and low in withstand voltage. The gallium oxide homogeneous pn junction structure comprises cathode metal, a substrate and an n-type Ga2O3 epitaxial layer from bottom to top, a p-type NiO layer is arranged above the n-type Ga2O3 epitaxial layer, a p-type Ga2O3 material layer is arranged between the n-type Ga2O3 epitaxial layer and the p-type NiO layer, and a gallium oxide homogeneous pn junction is formed. The preparation method comprises the steps of epitaxial wafer cleaning, p-type Ga2O3 material layer preparation, cathode metal preparation, photoetching, p-type NiO film deposition, photoetching and anode metal preparation. N / P ion implantation is carried out on the upper portion of the gallium oxide epitaxial layer, Ga atoms in Ga2O3 are separated out and react again through high-temperature annealing to form the effective p-type characteristic, meanwhile, the effective p-type characteristic is combined with the p-type characteristic of p-type nickel oxide, p-type doping of gallium oxide is achieved through a simple process, the gallium oxide homogeneous pn junction is obtained, reliability is high, leakage current is small, and the gallium oxide homogeneous pn junction is suitable for large-scale production. The preparation method is used for preparing the p-Ga2O3 / n-Ga2O3pn junction diode with high voltage resistance.

The invention discloses an impregnation preparation method of a hybrid aluminum electrolytic capacitor, and relates to the technical field of capacitors. The method at least comprises the following steps: soaking corroded anode aluminum foil and cathode aluminum foil with citrate; placing electrolytic paper between the anode aluminum foil and the cathode aluminum foil and winding the electrolytic paper into a core package; at least one half of the volume of the core package is immersed in an impregnation liquid from one end for first impregnation treatment, then the core package is inverted, and at least one remaining half of the volume of the core package is immersed in the impregnation liquid from the other end for second impregnation treatment; carrying out drying treatment on the core package subjected to the second impregnation treatment; and carrying out assembling and aging treatment on the dried core cladding, an aluminum shell and a leather plug to obtain the hybrid aluminum electrolytic capacitor. Through the impregnation preparation method of the hybrid aluminum electrolytic capacitor provided by the invention, the impregnation time is greatly shortened, the impregnation efficiency and consistency are improved, and the performance of the capacitor is improved.

The invention provides a semiconductor device and a processing method thereof, and the semiconductor device comprises a semiconductor substrate; the gate metal structure is arranged on the semiconductor substrate; the gate dielectric layer is arranged between the gate metal structure and the semiconductor substrate; the covering layer is arranged between the gate dielectric layer and the gate metal structure, the covering layer comprises a first covering layer and a second covering layer, the first covering layer is located in a central area opposite to the gate metal structure, the second covering layer is located on at least one side of the first covering layer, and the material of the second covering layer is different from that of the first covering layer; and the work function of the second covering layer is different from that of the first covering layer. Therefore, work functions on two sides of the transistor can be changed, especially the work function of one side, close to the drain, of the gate metal structure, thereby improving the electric field intensity of an overlapping region of the gate and the drain, weakening the leakage current of the transistor, and improving the performance of a semiconductor device.

The invention relates to the technical field of dielectric energy storage device materials, in particular to high-entropy designed bismuth ferrite-based energy storage ceramic as well as a preparation method and application thereof, the chemical composition formula of the material is (0.7-x) Bi < 0.9 > (Sm < 0.5 > Gd < 0.5 >) < 0.1 > FeO < 3-0.3 > (Sr < 0.5 > Ba < 0.5 >) TiO < 3-x > NaNbO < 3-y > MnO < 2 >, the value range of x is 0-0.15, and the value range of y is 0-0.005. The relaxation ferroelectric material is designed by adopting a high-entropy strategy, and various elements occupy the same site of the material to generate lattice distortion, so that the relaxation characteristic of bismuth ferrite-based ceramic is promoted, and a ferroelectric hysteresis loop is optimized. The NaNbO3 anti-ferroelectric material is introduced, the long-range ferroelectric order is destroyed, the local random field is enhanced, and a low Pr value can be obtained. And in addition, the concentration of oxygen vacancies can be reduced by properly adding 0.5% mol of MnO2, so that the leakage current of the material is reduced, the energy storage efficiency is improved, and the material design not only enriches the application field of the high-entropy ceramic, but also provides a new thought for improving the performance of the energy storage ceramic.

The invention discloses a back contact battery and a preparation method thereof, and belongs to the technical field of photovoltaics. The back contact cell comprises a silicon substrate, a first doping layer and a second doping layer are arranged on the backlight surface of the silicon substrate at intervals, and the conduction types of the first doping layer and the second doping layer are opposite; the silicon substrate comprises a first region, a second region and a channel region, the first region corresponds to the first doping layer, and the second region corresponds to the second doping layer; the channel region is located between the first region and the second region; a concave structure is arranged at the edge junction, close to the first region, of the channel region, and / or a concave structure is arranged at the edge junction, close to the second region, of the channel region, the concave structure extends into the silicon substrate from the surface of the channel region to form a groove, the depth of the groove is d, and d is larger than or equal to 0.1 micron. And obtaining a concave structure at at least one boundary of the channel region by regulating and controlling the laser.

The invention discloses a trench p-type gallium oxide junction barrier Schottky diode and a preparation method thereof, and mainly solves the problems that an existing gallium oxide Schottky diode is high in on resistance and reverse leakage current and poor in voltage endurance capability and surge resistance capability. The device comprises a cathode ohmic metal layer (1), an n-type heavily-doped gallium oxide substrate (2), an n-type lightly-doped gallium oxide drift layer (3) and an anode Schottky metal layer (4) from bottom to top, and the upper surface of the n-type lightly-doped gallium oxide drift layer is downwards provided with a plurality of grooves (5) so as to change the surface electric field of the device; a p-type gallium oxide region (6) is injected below each groove, and the p-type gallium oxide region (6) and the n-type lightly doped gallium oxide drift layer form a gallium oxide homogeneous pn junction; and a high-k dielectric layer (7) is deposited in each groove. According to the invention, the leakage current is reduced, the reverse breakdown voltage of the device is improved, the on resistance is reduced, the anti-surge capability is improved, and the device can be used for power electronic equipment.

The invention discloses a PN junction gate gallium oxide-based MODFET device and a preparation method thereof, the PN junction gate gallium oxide-based MODFET device sequentially comprises a substrate, a channel layer, a spacing layer, a delta doping layer and a barrier layer, and further comprises a first ohmic contact region arranged on one side of the end surfaces of the spacing layer, the delta doping layer and the barrier layer; the second ohmic contact region is arranged on the other side of the end surfaces of the spacing layer, the delta doping layer and the barrier layer; the first ohmic contact region and the second ohmic contact region are higher than the upper surface of the barrier layer; the PN junction structure is arranged on a part of the surface of the barrier layer; the dielectric layer structure is arranged above the barrier layer, the PN junction structure, the first ohmic contact region and the second ohmic contact region in a crossing manner; a source electrode disposed on the first ohmic contact region; the drain electrode is arranged on the second ohmic contact region; the gate electrode is arranged on the PN junction structure and the dielectric layer structure, and the upper end of the gate electrode extends towards the two ends of the dielectric layer structure located above the PN junction structure to form a field plate structure. The reliability of the device can be improved.

The invention discloses a terminal structure of a power device, a preparation method and the power device. The terminal structure comprises a substrate; the epitaxial layer is located on one side of the substrate, the epitaxial layer is of the first doping type, and the epitaxial layer is provided with a first surface deviating from the substrate; the epitaxial regions are located on the side, away from the substrate, of the epitaxial layer, the epitaxial regions are distributed at intervals in the first direction, the region between any two adjacent epitaxial regions is an interval region, each epitaxial region comprises a first epitaxial region and a second epitaxial region which are arranged in a laminated mode, the first epitaxial region is of a second doping type, and the second epitaxial region is of a second doping type; the second epitaxial region has a first doping type, and the first direction is parallel to the first surface; the injection regions are located in the epitaxial layer and make contact with the interval regions, the surfaces, away from the substrate, of the injection regions are located in the first surface, and the injection regions are of the second doping type. The problem of low breakdown voltage of a power device with a field limiting ring structure in the prior art is solved.

The invention belongs to the technical field of electrode materials, and particularly relates to an electrode foil, a preparation method thereof and an aluminum electrolytic capacitor, and the preparation method of the electrode foil comprises the steps: carrying out the formation of a corrosion foil, and forming an aluminum oxide film on the surface of the corrosion foil; forming a nano-porous silicon dioxide film on the surface of the aluminum oxide film to obtain an electrode foil with an aluminum oxide-silicon dioxide double-layer composite oxide film; and sequentially carrying out phosphating treatment and annealing treatment on the electrode foil. According to the preparation method, after the corrosion foil is subjected to formation treatment to form the Al2O3 film, the nano-porous SiO2 film is formed on the surface of the Al2O3 film, the SiO2 film is subjected to phosphating treatment to contain phosphorus elements, the phosphorus elements are uniformly diffused into the SiO2 film, a double-layer composite oxidation film with the Al2O3 inner layer and the SiO2 outer layer is obtained, and the specific volume, the hydration resistance and the corrosion resistance of the low-voltage electrode foil are improved.

The invention belongs to the technical field of high-voltage electric appliance material preparation, and particularly relates to a zinc oxide resistor disc and a preparation method and application thereof. The preparation method comprises the following steps: (1) pre-sintering zinc oxide powder; (2) mixing the zinc oxide powder obtained in the step (1), an auxiliary agent and a dispersion liquid, and carrying out ball milling to obtain slurry; the particle size D50 of the slurry is 0.8-1.2 [mu] m, and the dispersity is greater than or equal to 95%; (3) performing spray drying and granulation on the slurry to obtain granulation powder; (4) carrying out molding and first sintering on the granulated powder to obtain a resistor disc semi-finished product; the first sintering adopts sectional sintering; and (5) forming an electrode layer on at least one surface of the resistor disc semi-finished product by adopting a vacuum sputtering and / or electrophoretic deposition process, and performing secondary sintering and annealing. The contact resistance of the zinc oxide resistor disc is less than or equal to 5m omega; and after 1000 hours of aging in a 85 DEG C + 85% RH environment, the leakage current increase is less than or equal to 2 [mu] A, and the performance degradation rate is less than or equal to 5%.

The invention belongs to the technical field of LED display chips, and discloses a Micro LED display chip and a preparation method thereof.According to the Micro LED display chip and the preparation method thereof, an epitaxial wafer MQW layer is processed through ultrafast pulse laser, so that an EBL layer and a P-GaN layer which can be free of ICP etching are prepared through subsequent deposition processing, the preparation method for constructing a vertically-distributed LED display chip is greatly simplified, and the manufacturing cost is reduced. And meanwhile, through the design of the cathode shallow slot network and the deep through holes, relatively high current density can be realized, and optical crosstalk can be effectively prevented.

The invention discloses an insulated gate MIS HEMT device, a preparation method, a chip and electronic equipment. The device structurally comprises a substrate layer, a nucleating layer, a transition layer, a buffer layer, a channel layer, an insertion layer, a barrier layer and a C-doped C: GaN insulating layer, wherein the nucleating layer, the transition layer, the buffer layer, the channel layer, the insertion layer, the barrier layer and the C-doped C: GaN insulating layer are sequentially located on the substrate layer. A metal layer on the insulating layer; the isolation structure is located on the side wall of the HEMT device, penetrates through the barrier layer, the insertion layer and the channel layer and is located on the buffer layer; the passivation layer is located on the upper surfaces of the metal layer and the barrier layer and the side walls of the insulating layer and the metal layer; the grid electrode is located in the grid electrode opening area and penetrates through the passivation layer to the upper surface of the metal layer; the source electrode and the drain electrode are located on different sides of the grid electrode respectively, and the source electrode and the drain electrode penetrate through the passivation layer, the barrier layer, the insertion layer and part of the channel layer. Through the arrangement of the C: GaN insulating layer and the high-resistance buffer layer, the device has a relatively positive threshold voltage, the gate electric leakage of the device is reduced, and the voltage withstanding characteristic of the gate of the device is improved.

The invention relates to a battery management system, in particular to a low-power-consumption battery management system which comprises a plurality of battery sampling chips AFE, a plurality of slave control units CSC and a master control unit BMU. The battery sampling chip AFE is used for acquiring voltage, current and temperature data of the single battery, sending the data to the corresponding slave control unit CSC, and entering a low-power-consumption state when an effective command is not received for a long time; the slave control unit CSC is used for collecting the voltage, current and temperature data, sent by the battery sampling chip AFE, of the single battery, sending the data to the master control unit BMU, and sending a wake-up signal, a register read-write command and an ADC measurement command to the corresponding battery sampling chip AFE when the data of the single battery needs to be measured; the master control unit BMU is used for processing the data sent by each slave control unit CSC and executing an advanced control algorithm; the technical scheme provided by the invention can effectively overcome the defect of relatively high energy consumption of the battery management system.