86results about How to "Reduce leakage current" patented technology

The invention belongs to the technical field of high-voltage electric appliance material preparation, and particularly relates to a zinc oxide resistor disc and a preparation method and application thereof. The preparation method comprises the following steps: (1) pre-sintering zinc oxide powder; (2) mixing the zinc oxide powder obtained in the step (1), an auxiliary agent and a dispersion liquid, and carrying out ball milling to obtain slurry; the particle size D50 of the slurry is 0.8-1.2 [mu] m, and the dispersity is greater than or equal to 95%; (3) performing spray drying and granulation on the slurry to obtain granulation powder; (4) carrying out molding and first sintering on the granulated powder to obtain a resistor disc semi-finished product; the first sintering adopts sectional sintering; and (5) forming an electrode layer on at least one surface of the resistor disc semi-finished product by adopting a vacuum sputtering and / or electrophoretic deposition process, and performing secondary sintering and annealing. The contact resistance of the zinc oxide resistor disc is less than or equal to 5m omega; and after 1000 hours of aging in a 85 DEG C + 85% RH environment, the leakage current increase is less than or equal to 2 [mu] A, and the performance degradation rate is less than or equal to 5%.

The invention relates to a high-entropy ceramic capacitor, a ceramic dielectric material for the high-entropy ceramic capacitor and a preparation method, the raw material composition of the ceramic dielectric material comprises NaNbO3, (Na0. 2Bi0. 2Ba0. 2Mg0. 2Zn0. 2) TiO3, H3BO3, CaZrO3 and the like, by controlling the raw material ratio and preparation process parameters of sodium niobate and adopting a multi-step grinding synthesis method, NaNbO3-based high-entropy ceramic is designed, so that the insulation resistance of the high-entropy ceramic capacitor is effectively improved; on the other hand, chemical modification treatment is carried out by introducing (Na0. 2Bi0. 2Ba0. 2Mg0. 2Zn0. 2) TiO3, H3BO3, CaZrO3 and the like, so that the structural stability of an antiferroelectric phase is enhanced, the compactness of the material is improved, and finally, the energy storage performance of the material is optimized and improved.

The application provides an anode foil and a preparation method thereof. The preparation method comprises the following steps: providing an unformed foil, wherein the unformed foil comprises an aluminum foil base material and an aluminum powder sintering layer arranged on the surface of the aluminum foil base material; and sequentially performing the following processes on the unformed foil: water boiling, first-stage chemical conversion, second-stage chemical conversion, third-stage chemical conversion, power feeding treatment, fourth-stage chemical conversion, fifth-stage chemical conversion, first-stage heat treatment, first chemical conversion repair, first phosphoric acid treatment, second chemical conversion repair, second-stage heat treatment, third chemical conversion repair and second phosphoric acid treatment. The solutes of the electrolyte of the first-stage chemical conversion, the second-stage chemical conversion and the third-stage chemical conversion comprise citric acid, triammonium citrate, adipic acid, ammonium adipate, salicylic acid, hypophosphite, boric acid and ammonium salt, and the solvent is water. The solutes of the electrolyte of the fourth-stage chemical conversion and the fifth-stage chemical conversion comprise citric acid, triammonium citrate, sebacic acid, ammonium sebacate, salicylic acid, sodium hypophosphite, boric acid and ammonium salt, and the solvent is water. An anode foil prepared by the preparation method has a high specific capacity and a small hydration leakage current.

The invention discloses corrosion aluminum powder and a preparation method and application thereof, and the preparation method comprises the following steps: S1, carrying out plasma passivation treatment on aluminum powder to obtain surface modified aluminum powder with an amorphous aluminum oxide layer; and S2, carrying out surface micro-corrosion on the surface modified aluminum powder, and then drying and grading to obtain the corroded aluminum powder. The method comprises the following steps: forming an amorphous aluminum oxide layer on the surface of aluminum powder; and then micro-corrosion is carried out on the amorphous aluminum oxide layer, a rich pore structure is formed on the amorphous aluminum oxide layer, and after corrosion is completed, the amorphous aluminum oxide layer can be automatically formed on the corrosion surface again. The surface of the obtained corrosion aluminum powder is completely wrapped by the amorphous aluminum oxide layer, so that the leakage current can be greatly reduced, and the electrochemical stability of the anode foil is greatly improved; the porous carbon has certain roughness and rich pore structures, and the specific surface area and the specific volume are greatly increased; the micro-corrosion has no negative influence on the mechanical strength of the aluminum powder, and ensures that no micro-crack appears on the surface of the anode foil.

The invention discloses a volatile threshold switching device based on an atomic-scale geometric confinement layer and a preparation method thereof. The device comprises a substrate layer, a bottom electrode layer, a functional active layer, a geometric confinement layer and a top electrode layer which are stacked in sequence, the functional active layer is used for providing active metal ions to form conductive filaments; the functional active layer is made of a two-dimensional layered ferroelectric material; the geometric confinement layer is made of hexagonal boron nitride sheets, and the thickness range of the hexagonal boron nitride sheets is 1-5 hexagonal boron nitride atomic layers. According to the invention, the h-BN material with atomic-scale lattice defects is introduced as the geometric confinement layer, and the diameter of the conductive filament formed by copper ions in the functional active layer is physically limited by using the atomic-scale ion sieve effect of the h-BN material, so that the problem of failure caused by overgrowth of the filament in a traditional device is solved.

The application discloses a kind of copolymer organic semiconductor devices based on isolation and interconnection and preparation method, including substrate, photoetching blocking layer, insulating isolation layer, N organic field effect transistor and N-1 interconnection line;Photoetching blocking layer includes isolation layer and inorganic dielectric layer;Isolation layer is opened with N longitudinal through isolation groove along length direction;Inorganic dielectric layer includes lower dielectric layer and upper dielectric layer;Lower dielectric layer is located in N isolation, and upper dielectric layer is laid on the top of isolation layer and lower dielectric layer;Each organic field effect transistor includes semiconductor layer, source, drain and gate;Semiconductor layer is laid in the isolation groove at the bottom of corresponding lower dielectric layer section, and its material is organic copolymer.The application effectively utilizes isolation groove and photoetching blocking layer, and the semiconductor layer of different semiconductor materials is wrapped and isolated, so as to realize the integration of different organic field effect transistors on the same substrate, and the organic field effect transistor can realize effective interconnection.

The invention discloses a preparation method of an HfO2-based ferroelectric film with gradient oxygen vacancy distribution as well as the film and application of the HfO2-based ferroelectric film. The method comprises the steps that a lower electrode is prepared on a substrate, an amorphous HfO2-based prefabricated film is deposited on the lower electrode through atomic layer deposition, an upper electrode is prepared on the prefabricated film to form a sandwich stacking structure, and crystallization annealing is carried out to induce the prefabricated film to be crystallized into a ferroelectric orthorhombic phase; wherein the atomic layer deposition comprises at least one oxidant modulation period, a first deposition stage and a second deposition stage with different oxidation capacities are alternately carried out, and the oxygen content and oxygen vacancy defect distribution are regulated and controlled in the film thickness direction through the combination of sub-cycles, so that the oxygen vacancy concentration on one side close to the lower electrode and the upper electrode is lower than that in the middle area of the film. The obtained film can be applied to devices such as ferroelectric capacitors and ferroelectric field effect transistors, and is used for improving polarization output, reducing electric leakage and improving consistency and reliability of the devices.

This application relates to the field of sensor encapsulation, specifically disclosing an encapsulation composition with both high hydrophobicity and easy permeability, its preparation method, and its application. The raw materials used include epoxy resin, a curing agent, and a hydrophobic additive in a weight ratio of 1:1:(3-4). The epoxy resin includes bisphenol A type epoxy resin or bisphenol F type epoxy resin. The hydrophobic additive is prepared from quartz sand and a surface-modified paraffin oil emulsion in a weight ratio of 100:(0.99-4.75), with the quartz sand having a mesh size of 10-1500 mesh. The preparation method involves continuously dispersing the quartz sand while simultaneously spray-mixing the surface-modified paraffin oil emulsion with the quartz sand until the surface-modified paraffin oil emulsion is completely consumed, followed by drying to obtain the hydrophobic additive. The composition of this application can be used for encapsulating sensors, exhibiting both good hydrophobicity and permeability, ensuring good insulation reliability and initial discharge voltage for the sensor.

The application relates to a thin film transistor structure for reducing off-state power consumption and a preparation method thereof, and relates to the technical field of thin film transistors.The structure comprises a source electrode and a drain electrode arranged on a substrate; an active layer is arranged in a spacing region between the source electrode and the drain electrode; and a drain electrode isolation layer is arranged on the side of the drain electrode in contact with the active layer.The application prepares an insulation layer in the active layer close to one end of the drain electrode, so that the purpose of reducing the drain current of the thin film transistor in the off state is achieved, and the problem of unstable liquid crystal bias in the holding stage of the thin film transistor is solved.

The application discloses a TBC battery and a preparation method thereof. The TBC battery comprises a substrate and a P-zone assembly arranged on the back of the substrate. The P-zone assembly comprises a first electrode, a first tunneling silicon oxide layer, a boron-doped polysilicon layer and a first passivation layer which are sequentially stacked on the back of the substrate. The first electrode penetrates through the first passivation layer and the boron-doped polysilicon layer. The P-zone assembly further comprises a tunneling silicon nitride layer arranged between the first tunneling silicon oxide layer and the boron-doped polysilicon layer. The tunneling silicon nitride layer is used to block the boron element in the boron-doped polysilicon layer from being precipitated to the first tunneling silicon oxide layer. The application inhibits the precipitation of the boron element in the boron-doped polysilicon layer through the silicon nitride layer, enhances the passivation effect, and further improves the final conversion efficiency and reliability of the battery.

Embodiments of the present application relate to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate, a trench is formed in the substrate; a conductive layer is located in the trench, the conductive layer comprises a first conductive layer and a second conductive layer, the second conductive layer is located on the first conductive layer, and a projection area of a bottom of the second conductive layer in the trench is greater than a projection area of a top of the first conductive layer in the trench; a dielectric layer is located between the conductive layer and an inner wall of the trench, and a top of the dielectric layer is lower than a top of the first conductive layer; an isolation layer is located on the conductive layer; and a gap is enclosed by the isolation layer, the conductive layer, the dielectric layer and a side wall of the trench. A work function of the first conductive layer is greater than a work function of the second conductive layer. The opening speed of the transistor is improved, the gate-induced drain leakage current of the semiconductor structure is reduced, the reliability of the semiconductor structure is improved, and the power consumption of the semiconductor structure is reduced.

The application provides a detector pixel structure and an electronic detector. The detector pixel structure comprises a semiconductor substrate, a first and a second conductive type heavily doped layer, an insulating layer, an upper electrode, a lower electrode, an electron channel hole electrode, a metal protection ring and a doped ring; the doped ring is located in the semiconductor substrate and outside the first conductive type heavily doped layer and is exposed on the first surface of the semiconductor substrate; the insulating layer extends from the surface of a non-detection area to the surface of the semiconductor substrate, and the upper electrode extends from the surface of the non-detection area to the surface of the insulating layer; the electron channel hole electrode is located on the sidewall of the semiconductor substrate and is electrically connected to the lower electrode at one end and extends to the side surface of the insulating layer at the other end; and the metal protection ring is located on the surface of the semiconductor substrate and outside the upper electrode. The application can effectively avoid the image distortion caused by the deviation of the electron beam propagation direction, reduce the leakage current of the detector, improve the breakdown voltage and thus improve the detection performance.

The invention provides an intelligent linear cyclic lithium battery charging control method, which comprises the following steps of: constructing a charging channel selection network, sequentially gating a charging channel of a single lithium battery by adopting a fixed time slice polling mechanism, and executing three-section type charging control of pre-charging, constant-current charging and constant-voltage charging in each time slice, and meanwhile, by combining a voltage sampling scheme of a shared divider resistor and a multi-protection function, accurate and balanced charging of a plurality of lithium batteries is realized. The method has the advantages that the method can be suitable for a 9V power supply scene of three lithium battery packs connected in series, a DC-DC step-up / step-down circuit does not need to be configured, ripple waves, EMI interference and power loss caused by a switching power supply are eliminated at the same time, the system architecture is simplified, the cost is reduced, the charging safety of the battery packs is improved, and the cycle life of the battery packs is prolonged.

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, the method comprising: providing a semiconductor substrate, the semiconductor substrate being provided with a plurality of first bit lines extending along a first direction; forming a first transistor array on the semiconductor substrate, the first transistor array comprising a plurality of first semiconductor columns; forming first word lines, each first semiconductor column being connected with a corresponding first word line and a first bit line; forming a second transistor array on the first transistor array, the second transistor array comprising a plurality of second semiconductor columns, the first semiconductor columns and the second semiconductor columns corresponding to each other; and forming second word lines and second bit lines, each second semiconductor column being connected with a corresponding second word line and a second bit line, so as to form a 2T0C semiconductor structure, and the capacitor process in the manufacturing process of the semiconductor structure can be simplified.

Provided is a semiconductor structure manufacturing method, comprising: providing a first wafer, the upper surface of the first wafer having a void structure extending to the interior of the first wafer; providing a second wafer, the lower surface of the second wafer having an insulating layer; bonding the second wafer and the first wafer with the insulating layer and the upper surface of the first wafer as the bonding surface, the insulating layer sealing the void structure; manufacturing a device on the upper surface of the second wafer; and forming a through-silicon via structure, at least part of the side surface of the through-silicon via structure being surrounded by the void structure. The application can seal the void structure with the existing insulating layer, thereby maintaining the design pattern of the void structure, ensuring the stress release effect of the subsequently formed through-silicon via structure, increasing the area of the region around the through-silicon via structure that is not affected by internal stress, increasing the number of transistors arranged, and improving the performance of the semiconductor structure. In addition, the device is formed on the insulating layer, which can greatly reduce the parasitic capacitance, improve the clock, reduce the current leakage current of the device, and improve the performance of the semiconductor structure.

The present application relates to a GaN HEMT power semiconductor epitaxial wafer, comprising: a silicon (Si) substrate; a nucleation region formed on the substrate; a stress relief region formed on the nucleation region; a buffer region formed on the stress relief region; a channel region formed on the buffer region; and a barrier region formed on the channel region. Wherein, below the channel region, specifically, at any position between the buffer region and the channel region, inside the buffer region, or between the stress relief region and the buffer region, a rear barrier region is provided. The rear barrier region has a superlattice structure or a multilayer structure in which layers of 2H-Al(Ga)N material and layers of 4H-SiC(N) material are alternately stacked.

This invention relates to the field of dielectric materials and energy storage materials, specifically to a self-assembled nanoscale multi-interface all-polymer nanostructure dielectric thin film and its preparation method. The composition of the thin film material meets the following requirements: the mass ratio of thermoplastic resin to bismaleimide resin is 95:5-65:35; the amount of catalyst added is 0.05wt%-2wt% of the weight of the bismaleimide resin. The thin film provided by this invention can meet the application requirements at 150℃ and above 600MV / m. The thermoplastic resin component in the film imparts good flexibility, suitable for the winding and stacking processes of thin film capacitors; while the bismaleimide (BMI) nanoscale multi-interface structure effectively blocks charge injection and excitation, significantly reducing leakage current under high temperature and strong electric field conditions, thereby improving its dielectric energy storage performance under high temperature and strong electric field conditions.

The application discloses a quantum dot light-emitting device and a display device. The quantum dot light-emitting device comprises a cathode, an anode and a light-emitting layer arranged between the cathode and the anode. The light-emitting layer comprises a plurality of quantum dot layers arranged in a stack. The plurality of quantum dot layers comprise a first quantum dot layer and a second quantum dot layer arranged adjacently. The diameter of the quantum dots in the first quantum dot layer is different from the diameter of the quantum dots in the second quantum dot layer. The above scheme can reduce the probability of leakage of the quantum dot light-emitting device and improve the light-emitting efficiency.

Methods and systems for forming structures including a layer of low dielectric constant material on a surface of a substrate and structures and devices formed using the methods or systems are disclosed. An exemplary method includes providing a substrate within a reaction chamber of a reactor system, providing one or more precursors to the reaction chamber, providing one or more reactants, including a mixture of a nitrogen and oxygen containing reactant and a hydrogen containing reactant, and providing pulsed plasma power to polymerize the one or more precursors within the reaction chamber.

This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and barrier layer include a gate region and source and drain regions located on both sides of the gate region. A P-type semiconductor layer is located on the gate region. A first hydrogen-rich layer is located on the side of the P-type semiconductor layer near the drain region. The hydrogen concentration of the first hydrogen-rich layer is greater than that of the P-type semiconductor layer. Compared with the P-type semiconductor layer, the resistivity of the first hydrogen-rich layer is higher, which can reduce the leakage current on the side of the gate near the drain when the gate is off and reduce the electric field strength on the drain side when the gate is on, thereby improving the reliability of the device.

The present disclosure obtains an optical semiconductor device capable of preventing a decrease in a frequency band. A first pad (8) connected to a first electrode (6) of an optical modulator (2) and a second pad (9) connected to a second electrode (7) of the optical modulator (2) are disposed on a first terrace (11) via an insulating film (22). In the first terrace (11), a first conductive type layer (13, 14) is removed between the first pad (8) and the second pad (9).

The invention provides a resin composition and application thereof, a layer-adding film and a preparation method and application thereof, and belongs to the technical field of composite materials. The resin composition is prepared from the following components in parts by mass: 10 to 30 parts of modified benzoxazine prepolymer; 10 to 40 parts of modified polyphenyl ether resin; 1-5 parts of an initiator; and 100 to 300 parts of an inorganic filler. The modified benzoxazine prepolymer is synthesized from raw materials including allyl benzoxazine and a diamine compound containing a benzocyclobutene structure. According to the present invention, the diamine compound containing the benzocyclobutene structure is adopted to modify the allyl benzoxazine, and the mass parts of the modified benzoxazine prepolymer, the modified polyphenyl ether resin, the initiator and the inorganic filler in the resin composition are controlled, such that the dielectric property and the heat resistance of the resin composition can be significantly improved; and the film-forming property is excellent, and the requirement of a layer-adding film is met.

The invention discloses an unmanned aerial vehicle self-locking switch system and a control method thereof, and relates to the technical field of unmanned aerial vehicles. The system comprises a switch button, an auxiliary power module, a main power module, a self-locking unit, a control unit and an electric quantity display unit, stable startup and shutdown are achieved through dual-time-sequence button control that first pressing lasts for a first preset time and second pressing lasts for a second preset time in cooperation with a time-sharing cooperation mechanism of auxiliary power and main power, the self-locking unit locks the switch state, and the electric quantity display unit displays the electric quantity. And accidental on-off caused by signal jitter is avoided. The system is extremely low in leakage current in a shutdown state, effectively prevents battery over-discharge, has electric quantity display and state feedback functions, and remarkably improves the reliability, safety and user experience of the switch.

The application relates to a kind of graphite-like capacitor carbon and its preparation method and application, relate to carbon material technical field, solve the problem that the needle coke-based capacitor carbon in the activation pore-forming process of prior art is difficult to consider high specific surface area, layered ordered graphite structure keeps, pore size structure uniform control and continuous electric conduction network, leading to the specific capacitance, rate performance and cycle stability of material are limited.The application is by mixing needle coke powder and chemical activator, first activation is carried out by heating, and the activated product is obtained, and the intermediate product A is obtained by post-processing;Intermediate product A is mixed with catalytic activator, second activation is carried out by heating, and catalytic graphitization product is obtained, and the intermediate product B is obtained by post-processing;The intermediate product B is calcined to obtain graphite-like capacitor carbon by refining treatment.The graphite-like capacitor carbon provided by the application can be applied to the preparation of supercapacitors, and the synergistic balance between high specific surface area, high packing density, excellent conductivity and structural stability is realized.

The invention discloses a non-polar high-voltage foamed aluminum-based hybrid super capacitor and a preparation method thereof, and belongs to the technical field of super capacitors. The super capacitor adopts a symmetrical non-polar structure, a composite electrode comprises a pure aluminum current collecting layer, a foamed aluminum matrix layer and a uniform anodized aluminum oxide insulating layer which is prepared by coating the surface of a matrix aluminum rib with a directional scouring process, active carbon coating without hole blockage is realized through gas-phase camphor occupation, and the rated working voltage of a monomer is 6-10V; and after being connected in series and in parallel and superposed, a plurality of monomers are packaged by insulating heat-conducting silica gel and a heat-dissipating aluminum shell to form a high-voltage module The industrial problems of foamed aluminum pore-forming carbonization, uneven oxidation film and activated carbon hole blocking are thoroughly solved, the product power density is 15-25 kW / kg, the cycle life is larger than or equal to 1 million times, breakdown is avoided through nonpolar reverse connection, and the method can be widely applied to middle-high voltage power electronic scenes such as inverters, frequency converters, solid-state transformers and power reactive compensation.

This utility model relates to a switching circuit assembly, which includes a mechanical switch, a voltage adjustment module, and an overvoltage detection module. A first terminal of the mechanical switch is connected to a power supply input, and a second terminal of the mechanical switch is electrically connected to both the input terminals of the voltage adjustment module and the overvoltage detection module. The voltage adjustment module is configured to adjust the voltage on the power supply input when the mechanical switch is closed, ensuring that the voltage on the power supply input is within a predetermined voltage range. The overvoltage detection module is configured to detect an overvoltage event on the power supply input when the mechanical switch is closed and to deactivate the voltage adjustment module based on the detected overvoltage event. Furthermore, this utility model relates to a sensor module, a sensor system, and a vehicle.

The application discloses a GPP rectifier diode chip with a gradient-doped composite glass passivation layer, and belongs to the technical field of semiconductor devices. The GPP rectifier diode chip with the gradient-doped composite glass passivation layer comprises a base substrate, a gradient diffusion zone and a composite glass passivation layer. The application solves the problems of poor interface charge stability, large leakage current and insufficient long-term reliability of a conventional single-layer or multi-layer glass passivation layer of an existing GPP rectifier diode chip. The first gradient distribution of the resistivity of the base substrate along the thickness direction, the second gradient distribution of the impurity concentration of the gradient diffusion zone surface along the transverse direction and the composite glass passivation layer with periodic fluctuation of carbon content inhibit the concentration effect of the junction edge electric field, improve the interface matching property and compactness of the passivation layer and the semiconductor surface, thereby reducing the leakage current, and improving the voltage resistance and long-term working stability of the device.

The invention discloses a process method and process equipment of a semiconductor device. The process method comprises the following steps: acquiring a substrate with an original thin film; introducing a first gas into the process cavity; high-temperature plasma treatment is conducted on the first gas, so that the first gas is ionized and excited to release ultraviolet photons, the ultraviolet photons penetrate through the surface of the original thin film, impurity atoms in the original thin film are removed, and the energy of the ultraviolet photons generated by the first gas is larger than the chemical bond energy of the impurity atoms. By executing the steps, the defect density in the tunneling layer thin film can be reduced, so that the overall quality of the thin film is improved, the occurrence of leakage current of the memory can be effectively reduced, the service life of the memory is prolonged, the breakdown voltage of the memory can be improved, and the reliability of the memory is improved.

A panel device includes a substrate, a common electrode, and an electrostatic protection component. The substrate includes an active area and a peripheral area, the peripheral area is outside of the active area, and a plurality of signal lines is disposed on the substrate. The common electrode is disposed on the substrate, and at least part of the common electrode is disposed in the peripheral area. The electrostatic protection component is disposed in the peripheral area of the substrate and electrically connected to one of the plurality of signal lines and the common electrode, and the electrostatic protection component includes a first double-gate transistor. The first double-gate transistor includes a first gate, a second gate, a first electrode and a second electrode. The first gate is electrically connected to the first electrode, and the second gate is electrically connected to the second electrode.

The invention provides a semiconductor device and a preparation method thereof, and belongs to the technical field of semiconductors. The active region is positioned in the substrate and extends along a first direction; the gate structure is located on the surface of the substrate and crosses the active region along a second direction, and the second direction is orthogonal to the first direction; the trench isolation structure is located in the substrate and surrounds the active region, grooves are formed in the edges of the two sides, making contact with the active region, of the trench isolation structure, and the grooves are located below the gate structure; the groove is filled with the wide bandgap semiconductor material layer, the wide bandgap semiconductor material layer is in contact with the edge of the active region, the top of the wide bandgap semiconductor material layer is in contact with the bottom of the gate structure, and the bandgap width of the wide bandgap semiconductor material layer is larger than that of the substrate. The performance of the semiconductor device can be improved.