151results about How to "Reduce leakage current" patented technology

The invention discloses a manufacturing method of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric integration technology capable of eliminating a buffer layer. The manufacturing method comprises the following steps: depositing a back gate electrode and a back gate dielectric on a substrate in sequence; transferring the channel layer to the back gate medium; sequentially forming a buffer layer, a source electrode, a drain electrode, a top gate dielectric layer formed by a high-k dielectric material and a top gate electrode on the channel layer; and annealing treatment is carried out in a vacuum environment, and the buffer layer sublimates, so that Van der Waals interfaces are formed between the channel layer and the top gate dielectric layer and between the channel layer and the source electrode as well as between the channel layer and the drain electrode. According to the high-k gate dielectric integration technology based on the erasable buffer layer, the erasable buffer layer after vacuum annealing is utilized, damage to a two-dimensional material is avoided, a high-quality high-k gate dielectric is deposited, interface regulation and control between a channel layer and a top gate dielectric are achieved, and the equivalent oxide thickness is reduced; and good contact between the channel layer and source and drain metal is realized, the contact resistance of the transistor is reduced, and the electrical performance of the transistor is improved.

The invention provides a superlattice infrared detector chip manufacturing method, and belongs to the technical field of infrared detector manufacturing. The problem that the product performance or the product yield is low due to the fact that the precision fluctuation of the photoetching technology when the hard mask is removed is not considered in the current hard mask removing scheme is solved; comprising the following steps: forming a hard mask: growing the hard mask with a certain thickness on the surface of a wafer made of a superlattice material; photoetching an upper electrode table top; etching a hard mask: taking the photoresist as a mask, and etching the hard mask by adopting an ICP (Inductively Coupled Plasma) technology to obtain an upper electrode mesa mask pattern; degumming and cleaning an upper electrode table board; photoetching a lower electrode table board: adopting photoresist as a mask of a lower electrode table board area, and manufacturing the lower electrode table board area through a photoetching technology; carrying out ICP etching on the table board; performing wet etching on the table board; degumming and cleaning a lower electrode table board; forming a passivation layer film; opening holes in the passivation layer; manufacturing a gold electrode; the method is applied to preparation of the superlattice infrared detector chip.

The invention discloses a homogeneous pn junction terminal gallium oxide Schottky barrier diode and a preparation method thereof. The problems that gallium oxide p-type doping is difficult, and heterojunction electric leakage is high and voltage resistance is low are solved. The semiconductor device comprises a cathode, an n-Ga2O3 substrate and an n-Ga2O3 epitaxial layer from bottom to top, ion implantation regions are arranged at the left end and the right end of the upper surface of the n-Ga2O3 epitaxial layer, and the upper surface of the n-Ga2O3 epitaxial layer is covered with an anode; the ion implantation region is subjected to annealing treatment to form a p-type Ga2O3 region, and the p-type Ga2O3 region and the n-Ga2O3 epitaxial layer form a homogeneous pn junction terminal, so that the gallium oxide Schottky barrier diode with high voltage resistance and low electric leakage is realized. The preparation method comprises the steps of cleaning an epitaxial wafer, photoetching to form a region to be implanted with ions, carrying out ion implantation, cleaning, carrying out rapid thermal annealing to form p-Ga2O3, and preparing a cathode and an anode. According to the invention, N / P ions are injected, annealing treatment is carried out, a gallium-oxygen-nitrogen-phosphorus compound with a p-type characteristic is generated in the n-Ga2O3 epitaxial layer, and the homogeneous pn junction terminal gallium oxide Schottky barrier diode is realized. The method can be used in high-voltage and high-power fields such as power grids and high-speed rails

The invention discloses a gallium oxide-based MOSFET device and a preparation method thereof, and relates to the field of semiconductor devices. The device has the characteristics of high voltage resistance and low electric leakage, and comprises a conductive region and an edge terminal region connected with the conductive region, the conductive region comprises a first drain metal layer, a first gallium oxide substrate, a first gallium oxide epitaxial layer, a gallium oxide current barrier layer and a highly-doped gallium oxide N + region which are sequentially stacked from bottom to top, and a groove which is positioned on the surface of the highly-doped gallium oxide N + region and of which the bottom is propped against the first gallium oxide epitaxial layer; the conductive region further comprises a first p-type semiconductor buried layer located at the bottom and on the side wall of the groove, a gate dielectric layer located on the surface of the first p-type semiconductor buried layer, the side wall of the groove and the surface of the highly-doped gallium oxide N + region, and a gate metal layer located on the surface of the gate dielectric layer. The first interlayer dielectric layer covers the surface and the side face of the gate metal layer and the side face of the gate dielectric layer, and the source metal layer is located on the surface of the first interlayer dielectric layer and the surface of the highly-doped gallium oxide N + region.

The invention relates to the field of nonvolatile memories, in particular to an SOT-MRAM circuit unit based on a 2T2M differential structure and a storage array circuit of the SOT-MRAM circuit unit. The SOT-MRAM unit comprises a first magnetic tunnel junction, a second magnetic tunnel junction, a first field effect transistor, a second field effect transistor, a first phase inverter, a second phase inverter, a write line, a read line, an input line and an output line which have a specific connection relation. According to the SOT-MRAM circuit unit, through the special 2T2M differential structure design and in combination with the excellent performance of a spin-orbit moment magnetic tunnel junction, the storage and operation performance and efficiency of a 2T2MSOT-MRAM differential circuit unit array are integrally improved, the dependence on the performance of the MTJ is reduced, the SOT-MRAM circuit unit has the better energy efficiency ratio and the more stable read-write speed and precision, and the SOT-MRAM circuit unit has the advantages of being simple in structure, low in cost and high in reliability. And the reliability and the stability are excellent.

The invention provides a display device which comprises a plurality of cascaded gate drive circuits, and each gate drive circuit comprises two pull-down sub-circuits. Each pull-down sub-circuit includes an inverter and a pull-down maintenance unit, wherein the inverter includes a reset transistor and a plurality of transistors. The two pull-down sub-circuits are configured to alternately output low-level power supply signals to the second node in a period of a preset duration, and the preset duration is in a range from the duration of a driving period of 160 frames of pictures to the duration of a driving period of 240 frames of pictures. Through the combined action of the plurality of transistors in the inverter, the grid voltage of the transistor connected with the second node is reduced, and the working time of each pull-down sub-circuit is reduced through the alternate working mode of the double pull-down sub-circuits; therefore, the problems of electric leakage and stability in the gate drive circuit of the high-mobility oxide semiconductor thin film transistor are effectively solved.

The invention provides a preparation method of a special aluminum electrolytic capacitor for a low-temperature-resistant detonator trigger, and the method comprises the following steps: cutting a positive electrode foil and a negative electrode foil, and riveting the cut positive electrode foil and negative electrode foil with a positive guide pin and a negative guide pin; placing electrolytic paper between the riveted positive electrode foil and negative electrode foil, winding the electrolytic paper to form a core package, injecting electrolyte into the core package, and sealing the core package in an aluminum shell by using colloidal particles to obtain a semi-finished capacitor; and cleaning the semi-finished product capacitor, sleeving, and sequentially carrying out primary aging sorting, secondary aging sorting, appearance observation and inspection to obtain the capacitor. The preparation method of the aluminum electrolytic capacitor special for the low-temperature-resistant detonator trigger is simple in production process, common in material and low in price, and the prepared aluminum electrolytic capacitor is excellent in electrical performance, wide in working temperature range and small in size.

The invention discloses a p-Ga2O3 / n-Ga2O3pn junction diode and a preparation method thereof, and solves the problems that gallium oxide p-type doping is difficult, and a heterojunction diode is large in leakage current and low in withstand voltage. The gallium oxide homogeneous pn junction structure comprises cathode metal, a substrate and an n-type Ga2O3 epitaxial layer from bottom to top, a p-type NiO layer is arranged above the n-type Ga2O3 epitaxial layer, a p-type Ga2O3 material layer is arranged between the n-type Ga2O3 epitaxial layer and the p-type NiO layer, and a gallium oxide homogeneous pn junction is formed. The preparation method comprises the steps of epitaxial wafer cleaning, p-type Ga2O3 material layer preparation, cathode metal preparation, photoetching, p-type NiO film deposition, photoetching and anode metal preparation. N / P ion implantation is carried out on the upper portion of the gallium oxide epitaxial layer, Ga atoms in Ga2O3 are separated out and react again through high-temperature annealing to form the effective p-type characteristic, meanwhile, the effective p-type characteristic is combined with the p-type characteristic of p-type nickel oxide, p-type doping of gallium oxide is achieved through a simple process, the gallium oxide homogeneous pn junction is obtained, reliability is high, leakage current is small, and the gallium oxide homogeneous pn junction is suitable for large-scale production. The preparation method is used for preparing the p-Ga2O3 / n-Ga2O3pn junction diode with high voltage resistance.

The invention relates to the technical field of dielectric energy storage device materials, in particular to high-entropy designed bismuth ferrite-based energy storage ceramic as well as a preparation method and application thereof, the chemical composition formula of the material is (0.7-x) Bi < 0.9 > (Sm < 0.5 > Gd < 0.5 >) < 0.1 > FeO < 3-0.3 > (Sr < 0.5 > Ba < 0.5 >) TiO < 3-x > NaNbO < 3-y > MnO < 2 >, the value range of x is 0-0.15, and the value range of y is 0-0.005. The relaxation ferroelectric material is designed by adopting a high-entropy strategy, and various elements occupy the same site of the material to generate lattice distortion, so that the relaxation characteristic of bismuth ferrite-based ceramic is promoted, and a ferroelectric hysteresis loop is optimized. The NaNbO3 anti-ferroelectric material is introduced, the long-range ferroelectric order is destroyed, the local random field is enhanced, and a low Pr value can be obtained. And in addition, the concentration of oxygen vacancies can be reduced by properly adding 0.5% mol of MnO2, so that the leakage current of the material is reduced, the energy storage efficiency is improved, and the material design not only enriches the application field of the high-entropy ceramic, but also provides a new thought for improving the performance of the energy storage ceramic.

The invention discloses a trench p-type gallium oxide junction barrier Schottky diode and a preparation method thereof, and mainly solves the problems that an existing gallium oxide Schottky diode is high in on resistance and reverse leakage current and poor in voltage endurance capability and surge resistance capability. The device comprises a cathode ohmic metal layer (1), an n-type heavily-doped gallium oxide substrate (2), an n-type lightly-doped gallium oxide drift layer (3) and an anode Schottky metal layer (4) from bottom to top, and the upper surface of the n-type lightly-doped gallium oxide drift layer is downwards provided with a plurality of grooves (5) so as to change the surface electric field of the device; a p-type gallium oxide region (6) is injected below each groove, and the p-type gallium oxide region (6) and the n-type lightly doped gallium oxide drift layer form a gallium oxide homogeneous pn junction; and a high-k dielectric layer (7) is deposited in each groove. According to the invention, the leakage current is reduced, the reverse breakdown voltage of the device is improved, the on resistance is reduced, the anti-surge capability is improved, and the device can be used for power electronic equipment.

The invention belongs to the technical field of electrode materials, and particularly relates to an electrode foil, a preparation method thereof and an aluminum electrolytic capacitor, and the preparation method of the electrode foil comprises the steps: carrying out the formation of a corrosion foil, and forming an aluminum oxide film on the surface of the corrosion foil; forming a nano-porous silicon dioxide film on the surface of the aluminum oxide film to obtain an electrode foil with an aluminum oxide-silicon dioxide double-layer composite oxide film; and sequentially carrying out phosphating treatment and annealing treatment on the electrode foil. According to the preparation method, after the corrosion foil is subjected to formation treatment to form the Al2O3 film, the nano-porous SiO2 film is formed on the surface of the Al2O3 film, the SiO2 film is subjected to phosphating treatment to contain phosphorus elements, the phosphorus elements are uniformly diffused into the SiO2 film, a double-layer composite oxidation film with the Al2O3 inner layer and the SiO2 outer layer is obtained, and the specific volume, the hydration resistance and the corrosion resistance of the low-voltage electrode foil are improved.

The invention belongs to the technical field of high-voltage electric appliance material preparation, and particularly relates to a zinc oxide resistor disc and a preparation method and application thereof. The preparation method comprises the following steps: (1) pre-sintering zinc oxide powder; (2) mixing the zinc oxide powder obtained in the step (1), an auxiliary agent and a dispersion liquid, and carrying out ball milling to obtain slurry; the particle size D50 of the slurry is 0.8-1.2 [mu] m, and the dispersity is greater than or equal to 95%; (3) performing spray drying and granulation on the slurry to obtain granulation powder; (4) carrying out molding and first sintering on the granulated powder to obtain a resistor disc semi-finished product; the first sintering adopts sectional sintering; and (5) forming an electrode layer on at least one surface of the resistor disc semi-finished product by adopting a vacuum sputtering and / or electrophoretic deposition process, and performing secondary sintering and annealing. The contact resistance of the zinc oxide resistor disc is less than or equal to 5m omega; and after 1000 hours of aging in a 85 DEG C + 85% RH environment, the leakage current increase is less than or equal to 2 [mu] A, and the performance degradation rate is less than or equal to 5%.

The invention relates to an ultrathin hafnium oxide ferroelectric film capacitor based on electrode optimization and a preparation method thereof, and the method can effectively inhibit the production of an interface dead layer and excessive oxygen vacancies at the bottom of an HYO ferroelectric film through constructing a capacitor with a six-layer structure of a substrate, a bottom electrode layer, an oxide intercalation layer, a metal layer, an HYO ferroelectric film layer and a top electrode layer. The HYO ferroelectric film layer is grown through an atomic layer deposition method, and a large-area high-quality ferroelectric film with good uniformity can be grown; the capacitor with a six-layer structure is rapidly annealed in an inert atmosphere, so that the formation of a ferroelectric orthogonal phase in the HYO ferroelectric film can be promoted, the ferroelectricity is improved, the coercive field and the leakage current are reduced, and the fatigue characteristic is enhanced; meanwhile, the whole preparation process is simple and controllable, and the prepared ferroelectric film is good in quality and has commercial production and application potential.

The invention relates to a light emitting diode device based on quantum dots and a preparation method thereof, and belongs to the technical field of semiconductor devices. The light-emitting diode device based on the quantum dots comprises a light-emitting layer, the materials of the light-emitting layer comprise colloidal quantum dots and an organic light-emitting material; the mass ratio of the colloidal quantum dots to the organic light-emitting material is 100: (0.1-20); and the distribution gap of the colloidal quantum dots is larger than the unit cell size of the organic light-emitting material. By selecting proper colloidal quantum dots and organic light-emitting materials for compounding, dot gap defects are reduced, non-radiative recombination is inhibited, the structure of a functional layer of a device is optimized, and the carrier injection efficiency is improved, so that the photoelectric property of a colloidal quantum dot light-emitting layer is improved.

The invention provides a super junction diode and a manufacturing method thereof, and relates to the technical field of semiconductors. The super junction diode comprises an N-type epitaxial wafer; the terminal region and the active region are located on the surface of the N-type epitaxial wafer; wherein the active region comprises at least two first P columns, and each first P column comprises a P-type side wall, and a low-doped N-type ion region, a first insulating dielectric layer and a second insulating dielectric layer which are positioned in the P-type side wall; the first insulating dielectric layer and the second insulating dielectric layer are made of different materials; the first insulating dielectric layer is made of a material with a low dielectric constant or high dielectric strength; a passivation protection layer located on the surface of the terminal area; the first metal layer is located on the surface of the active region; and the second metal layer is located on the back of the epitaxial wafer. The super junction diode and the manufacturing method thereof provided by the invention have the advantages that the thermal failure probability of the device is reduced, and the breakdown voltage, reliability and robustness of the device are improved.

The invention relates to a high-entropy ceramic capacitor, a ceramic dielectric material for the high-entropy ceramic capacitor and a preparation method, the raw material composition of the ceramic dielectric material comprises NaNbO3, (Na0. 2Bi0. 2Ba0. 2Mg0. 2Zn0. 2) TiO3, H3BO3, CaZrO3 and the like, by controlling the raw material ratio and preparation process parameters of sodium niobate and adopting a multi-step grinding synthesis method, NaNbO3-based high-entropy ceramic is designed, so that the insulation resistance of the high-entropy ceramic capacitor is effectively improved; on the other hand, chemical modification treatment is carried out by introducing (Na0. 2Bi0. 2Ba0. 2Mg0. 2Zn0. 2) TiO3, H3BO3, CaZrO3 and the like, so that the structural stability of an antiferroelectric phase is enhanced, the compactness of the material is improved, and finally, the energy storage performance of the material is optimized and improved.

The utility model belongs to the field of semiconductor power device manufacturing, and particularly relates to a GaN HEMT device with a back barrier structure with gradually changed components, which comprises a SiC substrate layer, a GaN buffer layer connected above the SiC substrate layer, a first AlGaN back barrier layer connected above the GaN buffer layer, and a GaN channel layer connected above the first AlGaN back barrier layer. According to the GaN-based HEMT device, the back barrier layer with gradually-changed components is introduced, so that the electron constraint in a channel is effectively enhanced, the short-channel effect of the device is inhibited, the direct-current characteristic of the device is improved, and the power characteristic of the GaN-based HEMT device is further improved. For the interface scattering problem caused by the back barrier structure, the gradient component back barrier structure can reduce interface scattering and parasitic parameters compared with a fixed component back barrier structure, the influence on a GaN main channel is reduced, and the small signal and large signal characteristics of the device are improved.

The application provides an anode foil and a preparation method thereof. The preparation method comprises the following steps: providing an unformed foil, wherein the unformed foil comprises an aluminum foil base material and an aluminum powder sintering layer arranged on the surface of the aluminum foil base material; and sequentially performing the following processes on the unformed foil: water boiling, first-stage chemical conversion, second-stage chemical conversion, third-stage chemical conversion, power feeding treatment, fourth-stage chemical conversion, fifth-stage chemical conversion, first-stage heat treatment, first chemical conversion repair, first phosphoric acid treatment, second chemical conversion repair, second-stage heat treatment, third chemical conversion repair and second phosphoric acid treatment. The solutes of the electrolyte of the first-stage chemical conversion, the second-stage chemical conversion and the third-stage chemical conversion comprise citric acid, triammonium citrate, adipic acid, ammonium adipate, salicylic acid, hypophosphite, boric acid and ammonium salt, and the solvent is water. The solutes of the electrolyte of the fourth-stage chemical conversion and the fifth-stage chemical conversion comprise citric acid, triammonium citrate, sebacic acid, ammonium sebacate, salicylic acid, sodium hypophosphite, boric acid and ammonium salt, and the solvent is water. An anode foil prepared by the preparation method has a high specific capacity and a small hydration leakage current.

A display device and a manufacturing method thereof are provided. The display device includes a substrate and a pixel arranged on the substrate. The pixel includes a first transistor, a second transistor electrically connected to the first transistor, a third transistor electrically connected to the first transistor, and a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor. The first transistor includes a first semiconductor component and a first gate electrode. The first semiconductor component includes an oxide semiconductor material. The first gate electrode is arranged between the first semiconductor component and the substrate. The second transistor includes a second semiconductor component and a second gate electrode. The second semiconductor component includes the oxide semiconductor material. The second semiconductor component is arranged between the second gate electrode and the substrate. The third transistor includes a third semiconductor component including silicon.

The invention discloses corrosion aluminum powder and a preparation method and application thereof, and the preparation method comprises the following steps: S1, carrying out plasma passivation treatment on aluminum powder to obtain surface modified aluminum powder with an amorphous aluminum oxide layer; and S2, carrying out surface micro-corrosion on the surface modified aluminum powder, and then drying and grading to obtain the corroded aluminum powder. The method comprises the following steps: forming an amorphous aluminum oxide layer on the surface of aluminum powder; and then micro-corrosion is carried out on the amorphous aluminum oxide layer, a rich pore structure is formed on the amorphous aluminum oxide layer, and after corrosion is completed, the amorphous aluminum oxide layer can be automatically formed on the corrosion surface again. The surface of the obtained corrosion aluminum powder is completely wrapped by the amorphous aluminum oxide layer, so that the leakage current can be greatly reduced, and the electrochemical stability of the anode foil is greatly improved; the porous carbon has certain roughness and rich pore structures, and the specific surface area and the specific volume are greatly increased; the micro-corrosion has no negative influence on the mechanical strength of the aluminum powder, and ensures that no micro-crack appears on the surface of the anode foil.

The invention discloses a volatile threshold switching device based on an atomic-scale geometric confinement layer and a preparation method thereof. The device comprises a substrate layer, a bottom electrode layer, a functional active layer, a geometric confinement layer and a top electrode layer which are stacked in sequence, the functional active layer is used for providing active metal ions to form conductive filaments; the functional active layer is made of a two-dimensional layered ferroelectric material; the geometric confinement layer is made of hexagonal boron nitride sheets, and the thickness range of the hexagonal boron nitride sheets is 1-5 hexagonal boron nitride atomic layers. According to the invention, the h-BN material with atomic-scale lattice defects is introduced as the geometric confinement layer, and the diameter of the conductive filament formed by copper ions in the functional active layer is physically limited by using the atomic-scale ion sieve effect of the h-BN material, so that the problem of failure caused by overgrowth of the filament in a traditional device is solved.

The application discloses a kind of copolymer organic semiconductor devices based on isolation and interconnection and preparation method, including substrate, photoetching blocking layer, insulating isolation layer, N organic field effect transistor and N-1 interconnection line;Photoetching blocking layer includes isolation layer and inorganic dielectric layer;Isolation layer is opened with N longitudinal through isolation groove along length direction;Inorganic dielectric layer includes lower dielectric layer and upper dielectric layer;Lower dielectric layer is located in N isolation, and upper dielectric layer is laid on the top of isolation layer and lower dielectric layer;Each organic field effect transistor includes semiconductor layer, source, drain and gate;Semiconductor layer is laid in the isolation groove at the bottom of corresponding lower dielectric layer section, and its material is organic copolymer.The application effectively utilizes isolation groove and photoetching blocking layer, and the semiconductor layer of different semiconductor materials is wrapped and isolated, so as to realize the integration of different organic field effect transistors on the same substrate, and the organic field effect transistor can realize effective interconnection.

The invention discloses a preparation method of an HfO2-based ferroelectric film with gradient oxygen vacancy distribution as well as the film and application of the HfO2-based ferroelectric film. The method comprises the steps that a lower electrode is prepared on a substrate, an amorphous HfO2-based prefabricated film is deposited on the lower electrode through atomic layer deposition, an upper electrode is prepared on the prefabricated film to form a sandwich stacking structure, and crystallization annealing is carried out to induce the prefabricated film to be crystallized into a ferroelectric orthorhombic phase; wherein the atomic layer deposition comprises at least one oxidant modulation period, a first deposition stage and a second deposition stage with different oxidation capacities are alternately carried out, and the oxygen content and oxygen vacancy defect distribution are regulated and controlled in the film thickness direction through the combination of sub-cycles, so that the oxygen vacancy concentration on one side close to the lower electrode and the upper electrode is lower than that in the middle area of the film. The obtained film can be applied to devices such as ferroelectric capacitors and ferroelectric field effect transistors, and is used for improving polarization output, reducing electric leakage and improving consistency and reliability of the devices.

The invention discloses a multi-layer composite aluminum foil capacitor with high charge capacity density, which is applied to the technical field of capacitors, and can store more charges in a limited area by optimizing an electrode material, improving an insulating medium and innovating a structural design, thereby effectively improving the charge capacity density of the capacitor. Compared with a traditional aluminum foil capacitor formed through corrosion, the charge capacity density of the capacitor is greatly improved, the requirements for miniaturization and portability of electronic equipment can be met, high-density ultrahigh-voltage-resistant electrolytic paper and reasonably-arranged dielectric thin films are adopted for isolating positive and negative electrode aluminum foils, the insulativity between electrodes is ensured, and the service life of the capacitor is prolonged. According to the utility model, the electrolytic paper is used for preventing the short circuit phenomenon, especially the electrolytic paper has the characteristics of high density and ultrahigh voltage resistance, so that the capacitor can stably work in a high-voltage environment, the reliable operation of the capacitor is guaranteed, meanwhile, the leakage current of the capacitor can be obviously reduced, and the stable performance of the capacitor in the long-term use process is guaranteed.

The invention discloses a flexible Local diameter structure of a curved-surface display screen, and relates to the field of curved-surface display screens, the flexible Local diameter structure comprises a flexible substrate, and the flexible substrate is provided with a plurality of bowl-shaped mounting grooves arranged in a matrix; the light-emitting chip is mounted in the bowl-shaped mounting groove; the copper circuit is arranged on the flexible substrate and is provided with at least one positioning bracket for positioning the light-emitting chip; the heat dissipation piece is used for dissipating heat of the light-emitting chip; the surrounding edge is arranged outside the flexible substrate; according to the invention, the elastic contact element deforms due to extrusion at first, so that not only can a sealing effect be achieved, glue is prevented from overflowing, but also the flexible flow guide element can be inclined due to inflation, and after the optical glue layer is extruded, the glue flows towards the outer side and flows into the concentric-square-shaped accommodating groove along the flexible flow guide element, so that the glue can be further prevented from overflowing; therefore, the manufacturing process of the curved screen is simplified, and the probability that the liquid optical glue flows to the working table top during glue dispensing can be reduced by utilizing the two interception defense lines, namely the inner side edge and the outer side edge.

This application relates to the field of sensor encapsulation, specifically disclosing an encapsulation composition with both high hydrophobicity and easy permeability, its preparation method, and its application. The raw materials used include epoxy resin, a curing agent, and a hydrophobic additive in a weight ratio of 1:1:(3-4). The epoxy resin includes bisphenol A type epoxy resin or bisphenol F type epoxy resin. The hydrophobic additive is prepared from quartz sand and a surface-modified paraffin oil emulsion in a weight ratio of 100:(0.99-4.75), with the quartz sand having a mesh size of 10-1500 mesh. The preparation method involves continuously dispersing the quartz sand while simultaneously spray-mixing the surface-modified paraffin oil emulsion with the quartz sand until the surface-modified paraffin oil emulsion is completely consumed, followed by drying to obtain the hydrophobic additive. The composition of this application can be used for encapsulating sensors, exhibiting both good hydrophobicity and permeability, ensuring good insulation reliability and initial discharge voltage for the sensor.

The application relates to a thin film transistor structure for reducing off-state power consumption and a preparation method thereof, and relates to the technical field of thin film transistors.The structure comprises a source electrode and a drain electrode arranged on a substrate; an active layer is arranged in a spacing region between the source electrode and the drain electrode; and a drain electrode isolation layer is arranged on the side of the drain electrode in contact with the active layer.The application prepares an insulation layer in the active layer close to one end of the drain electrode, so that the purpose of reducing the drain current of the thin film transistor in the off state is achieved, and the problem of unstable liquid crystal bias in the holding stage of the thin film transistor is solved.

The application discloses a TBC battery and a preparation method thereof. The TBC battery comprises a substrate and a P-zone assembly arranged on the back of the substrate. The P-zone assembly comprises a first electrode, a first tunneling silicon oxide layer, a boron-doped polysilicon layer and a first passivation layer which are sequentially stacked on the back of the substrate. The first electrode penetrates through the first passivation layer and the boron-doped polysilicon layer. The P-zone assembly further comprises a tunneling silicon nitride layer arranged between the first tunneling silicon oxide layer and the boron-doped polysilicon layer. The tunneling silicon nitride layer is used to block the boron element in the boron-doped polysilicon layer from being precipitated to the first tunneling silicon oxide layer. The application inhibits the precipitation of the boron element in the boron-doped polysilicon layer through the silicon nitride layer, enhances the passivation effect, and further improves the final conversion efficiency and reliability of the battery.

A display substrate and a method for preparing the same, and a display device. The display substrate includes a driving structure layer disposed on a substrate, the driving structure layer includes a pixel driving circuit, the pixel driving circuit includes at least a first type transistor and a second type transistor, the first type transistor includes at least a first active layer, and the second type transistor includes at least a second active layer; the first active layer includes a first channel region and first source-drain connection regions located on both sides of the first channel region, the second active layer includes a second channel region and second source-drain connection regions located on both sides of the second channel region; the resistivity of the first active layer corresponding to the first source-drain connection region is different from the resistivity of the second active layer corresponding to the second source-drain connection region.

Embodiments of the present application relate to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate, a trench is formed in the substrate; a conductive layer is located in the trench, the conductive layer comprises a first conductive layer and a second conductive layer, the second conductive layer is located on the first conductive layer, and a projection area of a bottom of the second conductive layer in the trench is greater than a projection area of a top of the first conductive layer in the trench; a dielectric layer is located between the conductive layer and an inner wall of the trench, and a top of the dielectric layer is lower than a top of the first conductive layer; an isolation layer is located on the conductive layer; and a gap is enclosed by the isolation layer, the conductive layer, the dielectric layer and a side wall of the trench. A work function of the first conductive layer is greater than a work function of the second conductive layer. The opening speed of the transistor is improved, the gate-induced drain leakage current of the semiconductor structure is reduced, the reliability of the semiconductor structure is improved, and the power consumption of the semiconductor structure is reduced.