16results about How to "Increase the on-current" patented technology

The invention discloses a Schottky diode with a transverse structure, an in-situ sample preparation method and a processing technology. The cathode and the anode of the Schottky diode are in the same plane, the cathode ohmic contact layer is arranged on the periphery of the structure, the anode Schottky metal layer is arranged in the center of the structure, and the AlGaN barrier layer and the GaN substrate layer are sequentially arranged between the cathode ohmic contact layer and the anode Schottky metal layer. According to the in-situ sample preparation method, the FIB sample preparation technology and the selected area circuit breaking method are adopted to complete connection of the sample and the chip, the failure behavior of the device can be observed in real time under a transmission electron microscope, and the processing technology achieves effective isolation of the anode and the two-dimensional electron device through silicon oxide in the sample preparation process. Meanwhile, silicon oxide isolation can prevent short circuit of a power supply, so that a current passing path is shorter, the efficiency is higher, and the surface of a sample and a metal functional area below the sample can be effectively prevented from being damaged when ion beams are operated. The problems of low device power conversion efficiency, electrode short circuit and the like are solved.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method thereof, and relates to the technical field of semiconductors. The epitaxial layer is located on the first surface of the substrate; the first graphene layers are located on the surface, away from the substrate, of the epitaxial layer, and the two first graphene layers are arranged at intervals in the direction parallel to the substrate; the source electrodes are located on the surface, away from the substrate, of the first graphene layer, the two source electrodes are arranged at intervals in the direction parallel to the substrate, and the orthographic projection of the source electrodes is overlapped with the orthographic projection of the first graphene layer in the direction perpendicular to the substrate; the second graphene layer is located on the second surface of the substrate; wherein the first surface and the second surface of the substrate are oppositely arranged; the drain electrode is located on the surface, away from the substrate, of the second graphene layer; the gate dielectric layer is located on the surface, away from the substrate, of the epitaxial layer and located between the two source electrodes; and the gate is located on the surface, deviating from the substrate, of the gate dielectric layer. According to the invention, the performance of the SiC MOSFET device can be improved.

The invention relates to a high breakdown voltage enhanced gallium oxide field effect transistor and a preparation method thereof, the high breakdown voltage enhanced gallium oxide field effect transistor comprises a semi-insulating substrate, a buffer layer, a channel layer, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode, the buffer layer is located on the semi-insulating substrate; the channel layer is located on the buffer layer, and the channel layer is formed by sequentially connecting a first full-width channel, a plurality of first trapezoidal inclined channels, a multi-channel fin-type channel, a plurality of second trapezoidal inclined channels, a second full-width channel and a third full-width channel; the source electrode is located on the first full-width channel, and the drain electrode is located on the third full-width channel; the gate dielectric layer covers the plurality of first trapezoidal inclined channels, the multi-channel fin-type channel, the plurality of second trapezoidal inclined channels, the second full-width channel and the exposed surface of the buffer layer; the gate electrode wraps the gate dielectric layer on the surface of the multi-channel fin type channel. According to the transistor, high threshold voltage and good grid control capability of a device are ensured, on resistance of the device is reduced, breakdown voltage of the device is improved, and the transistor has better power characteristics.

The invention discloses a preparation method of a single-layer graphene field effect transistor with a conductive copper adhesive tape as a back gate. The method comprises the following steps: carrying out thermal oxidation on a silicon wafer, spin-coating photoresist, exposing and developing to obtain an electrode pattern; preparing a metal electrode through etching and thermal evaporation; transferring the graphene film to a prefabricated structure through wet transfer, and performing critical drying; and etching the back silicon dioxide, and taking the conductive copper adhesive tape as a back gate to obtain the graphene field effect transistor taking the conductive copper adhesive tape as the back gate. A method of transferring and prefabricating an electrode in advance is adopted in the preparation process of the device, so that the transferring quality of the graphene is effectively improved; in addition, a test result shows that the conductive copper adhesive tape is used as the back grid electrode, good contact is achieved by increasing the contact area with substrate silicon, good regulation and control on graphene can be achieved within a small grid electrode voltage range, and meanwhile the device shows a large conduction current value.

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate, a barrier layer, a P-type gallium nitride layer, a cap layer, an etching groove, a source electrode and a drain electrode, the substrate, the barrier layer, the P-type gallium nitride layer, the cap layer and the etching groove are stacked in sequence, the source electrode and the drain electrode are arranged on the cap layer and far away from the two sides of the etching groove, and the etching groove penetrates through the cap layer and etches part of the P-type gallium nitride layer. A surface oxidation modified aluminum nitride deposition layer is arranged at the bottom of the etching groove, and a grid electrode is arranged on the surface oxidation modified aluminum nitride deposition layer. The semiconductor device provided by the invention not only can maintain relatively high conduction current, but also can enhance the threshold voltage performance of the device, and successfully improves the threshold voltage during zero bias on the premise of not sacrificing on-state current.

The application provides a transistor structure and a preparation method thereof, relates to the technical field of semiconductors, and aims to improve the on performance of a transistor. The transistor structure comprises a substrate and a shallow trench isolation structure. The substrate comprises a containing groove, a first active region and a second active region. The containing groove is located on opposite sides of the first active region and the second active region. The opposite sides of the first active region comprise a step structure. The shallow trench isolation structure is at least partially arranged in the containing groove and is at least located on the opposite sides of the first active region and the opposite sides of the second active region. One side of the shallow trench isolation structure close to the first active region has a recess, and the recess exposes the step structure of the first active region. One side of the shallow trench isolation structure close to the second active region has a protrusion. The transistor structure is applied to a chip.

A display device and a method of manufacturing the same are provided. The display device includes: a substrate including a display area and a driving circuit area; a first transistor in the display area and including a first active layer on the substrate and a first gate electrode on the first active layer; a first gate insulating layer between the first active layer and the first gate electrode and entirely covering the first active layer; a second transistor in the driving circuit region and including a second active layer on the substrate and a second gate electrode on the second active layer; a second gate insulating layer between the second active layer and the second gate electrode, covering a portion of the second active layer overlapping the second gate electrode, and exposing other portions of the second active layer; and a first oxide semiconductor layer between the first gate insulating layer and the first gate electrode.

The present invention provides a semiconductor device and a method for preparing the same, the method comprising: providing a substrate, forming a drift region in the substrate; forming a plurality of channel spacing regions in the drift region, with a spacing between every two channel spacing regions to form a channel region; forming a source contact region, a drain contact region and a gate contact region in the drift region, and forming a substrate contact region in the substrate, with the substrate contact region and the drift region being spaced apart from each other, wherein the gate contact region is located between the source contact region and the drain contact region, and the channel region connects the source contact region and the drain contact region. The scheme of the present invention forms a plurality of channel spacing regions, with a spacing between every two channel spacing regions to form a channel region, and can adjust the pinch-off voltage of the device by adjusting the width of the channel region while ensuring that the device has a sufficiently high on-current when it is turned on, thereby reducing the on-resistance of the device, reducing the power consumption of the device, and improving the performance of the device.

A transistor structure includes a substrate, a gate structure, a first doped region, a second doped region, a drift region, a field plate, a charge storage layer and a first dielectric layer. The gate structure is located on the substrate. The first doped region and the second doped region are located in the substrate at two sides of the gate structure. The drift region is located in the substrate between the gate structure and the second doped region. The field plate is located on the substrate above the drift region. The charge storage layer is located between the field plate and the drift region. The first dielectric layer is located between the field plate and the charge storage layer.

A display device and a method of manufacturing the same are provided. The display device includes a substrate including a display area and a driving circuit area; a first insulating layer on the substrate; a second insulating layer on the first insulating layer; a first transistor in the display area and including a first semiconductor pattern layer formed as a semiconductor layer on the second insulating layer, a first gate electrode on the first semiconductor pattern layer, and a first lower electrode overlapping the first semiconductor pattern layer; and a second transistor in the driving circuit region and including a second semiconductor pattern layer formed as a semiconductor layer, a second gate electrode on the second semiconductor pattern layer, and a second lower electrode overlapping the second semiconductor pattern layer, in which the first lower electrode is between the substrate and the first insulating layer, and the second lower electrode is between the substrate and the second insulating layer. And the second lower electrode is between the first insulating layer and the second insulating layer.

The invention discloses a stator structure based on a disk-type permanent magnet motor winding, comprising: a PCB board with at least 6 layers or 6N layers, and a Hall sensor; each layer of the PCB board is provided with: multiple groups of outer ends, a winding setting part, and multiple groups of inner ends; each layer of the PCB board is provided with at least three-phase windings, and each phase of the winding is respectively provided with two wiring terminals; the wiring terminals are provided on the outer ends; each phase winding coil is printed and arranged from the corresponding outer end; the winding coil is uniformly printed on the winding setting part along the circumference, and the length of the winding coil is printed in parallel along the radial direction, and is arranged in parallel without overlapping; the winding coils of the same phase arranged on each layer of the PCB board are connected through the outer ends and the inner ends; the Hall sensor is arranged on the outer ends at an angle; and the layers in the PCB board are connected through vias.

The utility model provides an electrostatic discharge diode and a circuit structure. The electrostatic discharge diode comprises a substrate, an ion trap and a grid electrode. The ion trap is located in the substrate, the ion trap is provided with a first injection region and a second injection region which are arranged at an interval, and the ion trap extends to the interval between the first injection region and the second injection region; the grid electrode is located on the upper surface of the spaced ion trap between the first implantation region and the second implantation region. According to the above configuration, on one hand, the grid electrode is designed above the position of the isolation structure between the original first injection region and the second injection region of the diode, so that the isolation structure between the original first injection region and the second injection region of the diode is removed; according to the utility model, the conduction current of the diode is added with the conduction current of the lateral (left-right direction) cross section besides the original conduction current of the cross section downward to the bottom layer, so that the overall conduction current of the diode can be increased, and the electrostatic discharge capability of the diode is greatly improved.

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the manufacturing method of the semiconductor device comprises the steps: forming sacrificial layers and conductive layers which are sequentially and alternately arranged on a substrate in the thickness direction of the substrate, enabling the sacrificial layers and the conductive layers which are sequentially and alternately arranged to form a stacked structure, and enabling the lattice mismatch degree of the sacrificial layers and the conductive layers to be smaller than or equal to 0.5%; forming a groove extending along a direction perpendicular to the substrate in the stack structure through patterned etching, the groove exposing a side wall of the conductive layer and a side wall of the sacrificial layer; selectively etching the side wall of the exposed sacrificial layer, removing the sacrificial layer to form a cavity, reserving the conductive layer, and exposing at least part of the side surface of the conductive layer by the cavity; filling the cavity and the groove with an insulating layer; removing part of the insulating layer to form a channel which exposes at least part of the side surface of the conductive layer; and sequentially forming a gate insulating layer and a gate electrode on the side surface of the exposed conductive layer.

The application relates to an AlGaN / GaN vertical high electron mobility transistor and a manufacturing method thereof; solves the problem that when the field plate technology is applied to a device with a vertical drift region, the vertical drift region is easily affected by charge imbalance, thereby affecting the on-current; comprises a substrate of a GaN material; an N-type drift region, a GaN channel layer and an AlGaN barrier layer are sequentially grown above the substrate; a source region is formed on the upper surface of the AlGaN barrier layer, and a source electrode is arranged in the source region; the same number of P-type floating buried layers are formed on the left and right sides of the N-type drift region, and a P-type blocking layer is formed on the upper portion of the N-type drift region; a multilayer stepped dielectric groove is formed by etching through the middle portions of the N-type drift region, the P-type blocking layer, the GaN channel layer and the AlGaN barrier layer; a multilayer stepped oxide layer is arranged on the inner wall of each side of the dielectric groove; an SIPOS field plate is deposited between the oxide layers on the two sides; polycrystalline silicon is deposited above the SIPOS field plate; a gate electrode and a passivation layer are arranged above the polycrystalline silicon; and the two source electrodes are connected in common.

The application discloses a bidirectional thyristor structure electrostatic protection device, which comprises a substrate of a first conductive type, a buried layer and an epitaxial layer formed in the substrate, an isolation well region formed in the epitaxial layer, two first conductive type well regions one formed in a region surrounded by the isolation well region in the epitaxial layer, two second conductive type well regions two, a first conductive type intermediate well region between the two well regions two and spaced apart from the well regions two, a surface layer of the well region one formed with a heavily doped region one, a heavily doped region two and a floating heavily doped region, the floating heavily doped region extending to a surface layer of the adjacent well region two, an intermediate heavily doped region formed on the intermediate well region and extending to a surface layer of the adjacent well region two, a gate oxide layer formed on a surface layer of the substrate, and the gate oxide layer and the intermediate heavily doped region being short-circuited. The application can reduce the trigger voltage, improve the sustain voltage and reduce the risk of device latching.

The application discloses a kind of interpenetrating structure copolymer organic inverters and preparation method, including substrate, 2 organic field effect transistors, power supply end, ground terminal, output terminal, input terminal and interconnection line;Each organic field effect transistor includes organic semiconductor layer, photoetching dielectric barrier layer, source, drain and gate;Source includes n source fingers;Drain includes n drain fingers, n drain fingers and n source fingers equidistantly staggered, and form 2n-1 source-drain gap;Gate includes 2n-1 gate fingers arranged directly above source-drain gap.The application can effectively utilize photoetching dielectric barrier layer, introduce photoetching into the preparation of organic circuit, can effectively protect organic semiconductor material, and can be integrated on the same substrate Multiple organic field effect transistors are realized.In addition, interpenetrating structure can improve the on-current of circuit and reduce on-resistance, while the circuit opening voltage can be well reduced, and the power consumption of circuit is reduced.