4results about How to "Increase the on-current" patented technology

The invention relates to a high breakdown voltage enhanced gallium oxide field effect transistor and a preparation method thereof, the high breakdown voltage enhanced gallium oxide field effect transistor comprises a semi-insulating substrate, a buffer layer, a channel layer, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode, the buffer layer is located on the semi-insulating substrate; the channel layer is located on the buffer layer, and the channel layer is formed by sequentially connecting a first full-width channel, a plurality of first trapezoidal inclined channels, a multi-channel fin-type channel, a plurality of second trapezoidal inclined channels, a second full-width channel and a third full-width channel; the source electrode is located on the first full-width channel, and the drain electrode is located on the third full-width channel; the gate dielectric layer covers the plurality of first trapezoidal inclined channels, the multi-channel fin-type channel, the plurality of second trapezoidal inclined channels, the second full-width channel and the exposed surface of the buffer layer; the gate electrode wraps the gate dielectric layer on the surface of the multi-channel fin type channel. According to the transistor, high threshold voltage and good grid control capability of a device are ensured, on resistance of the device is reduced, breakdown voltage of the device is improved, and the transistor has better power characteristics.

The application provides a transistor structure and a preparation method thereof, relates to the technical field of semiconductors, and aims to improve the on performance of a transistor. The transistor structure comprises a substrate and a shallow trench isolation structure. The substrate comprises a containing groove, a first active region and a second active region. The containing groove is located on opposite sides of the first active region and the second active region. The opposite sides of the first active region comprise a step structure. The shallow trench isolation structure is at least partially arranged in the containing groove and is at least located on the opposite sides of the first active region and the opposite sides of the second active region. One side of the shallow trench isolation structure close to the first active region has a recess, and the recess exposes the step structure of the first active region. One side of the shallow trench isolation structure close to the second active region has a protrusion. The transistor structure is applied to a chip.

The application relates to an AlGaN / GaN vertical high electron mobility transistor and a manufacturing method thereof; solves the problem that when the field plate technology is applied to a device with a vertical drift region, the vertical drift region is easily affected by charge imbalance, thereby affecting the on-current; comprises a substrate of a GaN material; an N-type drift region, a GaN channel layer and an AlGaN barrier layer are sequentially grown above the substrate; a source region is formed on the upper surface of the AlGaN barrier layer, and a source electrode is arranged in the source region; the same number of P-type floating buried layers are formed on the left and right sides of the N-type drift region, and a P-type blocking layer is formed on the upper portion of the N-type drift region; a multilayer stepped dielectric groove is formed by etching through the middle portions of the N-type drift region, the P-type blocking layer, the GaN channel layer and the AlGaN barrier layer; a multilayer stepped oxide layer is arranged on the inner wall of each side of the dielectric groove; an SIPOS field plate is deposited between the oxide layers on the two sides; polycrystalline silicon is deposited above the SIPOS field plate; a gate electrode and a passivation layer are arranged above the polycrystalline silicon; and the two source electrodes are connected in common.

The application discloses a kind of interpenetrating structure copolymer organic inverters and preparation method, including substrate, 2 organic field effect transistors, power supply end, ground terminal, output terminal, input terminal and interconnection line;Each organic field effect transistor includes organic semiconductor layer, photoetching dielectric barrier layer, source, drain and gate;Source includes n source fingers;Drain includes n drain fingers, n drain fingers and n source fingers equidistantly staggered, and form 2n-1 source-drain gap;Gate includes 2n-1 gate fingers arranged directly above source-drain gap.The application can effectively utilize photoetching dielectric barrier layer, introduce photoetching into the preparation of organic circuit, can effectively protect organic semiconductor material, and can be integrated on the same substrate Multiple organic field effect transistors are realized.In addition, interpenetrating structure can improve the on-current of circuit and reduce on-resistance, while the circuit opening voltage can be well reduced, and the power consumption of circuit is reduced.