100results about How to "Improve breakdown voltage" patented technology

The invention discloses a cellular structure of a shield gate trench MOSFET and a manufacturing method thereof, the cellular structure of the shield gate trench MOSFET comprises a substrate, a drift region and an interlayer dielectric layer, the drift region is provided with a deep trench, and the deep trench is internally provided with a shield gate, an intermediate oxide layer and a control gate; a body region and a source region are formed at the upper part of the drift region through injection, the interlayer dielectric is provided with a source electrode contact hole which penetrates through the source region and extends into the body region, and highly doped contact regions are formed on the side wall and the bottom of the source electrode contact hole through injection; and a charge balance region is formed below the source electrode contact hole through high-energy ion implantation. According to the invention, by arranging the charge balance region, the lateral depletion of the shield gate to the adjacent drift region can be enhanced when the shield gate trench MOSFET device is in a reverse bias state, the specific on-resistance of the device is reduced, the depletion of the drift region of the epitaxial layer is accelerated, and the reliability and radiation resistance of the device are improved.

The invention discloses a homogeneous pn junction terminal gallium oxide Schottky barrier diode and a preparation method thereof. The problems that gallium oxide p-type doping is difficult, and heterojunction electric leakage is high and voltage resistance is low are solved. The semiconductor device comprises a cathode, an n-Ga2O3 substrate and an n-Ga2O3 epitaxial layer from bottom to top, ion implantation regions are arranged at the left end and the right end of the upper surface of the n-Ga2O3 epitaxial layer, and the upper surface of the n-Ga2O3 epitaxial layer is covered with an anode; the ion implantation region is subjected to annealing treatment to form a p-type Ga2O3 region, and the p-type Ga2O3 region and the n-Ga2O3 epitaxial layer form a homogeneous pn junction terminal, so that the gallium oxide Schottky barrier diode with high voltage resistance and low electric leakage is realized. The preparation method comprises the steps of cleaning an epitaxial wafer, photoetching to form a region to be implanted with ions, carrying out ion implantation, cleaning, carrying out rapid thermal annealing to form p-Ga2O3, and preparing a cathode and an anode. According to the invention, N / P ions are injected, annealing treatment is carried out, a gallium-oxygen-nitrogen-phosphorus compound with a p-type characteristic is generated in the n-Ga2O3 epitaxial layer, and the homogeneous pn junction terminal gallium oxide Schottky barrier diode is realized. The method can be used in high-voltage and high-power fields such as power grids and high-speed rails

The invention belongs to the technical field of insulation heat dissipation coatings, and particularly relates to a magnesium alloy high-pressure-resistance surface treatment liquid and a preparation method thereof. The coating comprises the following raw materials in parts by weight: 30-40 parts of organic silicon modified waterborne epoxy resin, 9-12 parts of modified hexagonal boron nitride, 10-15 parts of modified graphene, 2-4 parts of a curing agent, 0.5-2 parts of a flatting agent, 1-2 parts of a defoaming agent and 25-50 parts of acetone. A coating formed on the surface of a magnesium alloy base material through the magnesium alloy high-pressure-resistance surface treatment liquid has high volume resistance, high breakdown voltage resistance, high corrosion resistance and high heat conductivity coefficient, and the magnesium alloy high-pressure-resistance surface treatment liquid can be applied to the field of new energy and can also be applied to the fields of aerospace, 3C electronics and the like. And the market prospect is wide.

The invention discloses a gallium nitride heterojunction material structure and a growth method thereof, and relates to the technical field of semiconductor single crystal films, the material structure comprises a SiC substrate, an AlN nucleating layer, an AlGaN buffer layer, a GaN channel layer, an AlN insertion layer, a gradient component AlGaN barrier layer and a GaN cap layer from bottom to top; the material is prepared on a substrate in an epitaxial mode through a metal organic matter chemical vapor deposition method. AlGaN with gradually-changed Al components is adopted as the barrier layer, so that the electric field intensity of the barrier is reduced, the voltage endurance capability of the device is improved, and the power density and the reliability of the device are improved.

The invention discloses an additive molecule screening design method for optimizing the performance of ester-based insulating oil, and relates to the technical field of electrical insulating materials. The invention provides an additive molecule design method combined with a deep molecule generation model, aiming at solving the problems that the breakdown voltage performance is insufficient due to the fact that ester-based insulating oil is easy to generate rapid streamer under high-strength lightning impulse, and time and labor are consumed when an appropriate additive is found through an experiment. The method comprises the following steps: acquiring molecular data with target electronic attributes; taking the fragment of the molecular structure as the input of the model, and designing a new additive molecular structure by utilizing the molecular generation model; performing molecular screening according to target characteristics; and the performance of the screened molecules is verified through streamer discharge simulation. According to the method, generative design of ester-based insulating oil additive molecules is realized by using the deep autoregressive neural network, the molecular screening efficiency is remarkably improved, and a new technical route is provided for improving the breakdown voltage performance of the ester-based insulating oil.

The invention discloses a preparation method of a high-performance high-breakdown-voltage permanent magnetic ferrite, relates to the technical field of preparation of permanent magnetic ferrites, and aims to solve the problem that the breakdown voltage performance cannot meet the requirement when a high-performance ferrite is prepared on the basis of a 9-series strontium ferrite pre-sintering material added with lanthanum and cobalt. The preparation method comprises the following steps: uniformly mixing a lanthanum-cobalt-free 5-series strontium ferrite pre-sintered material, a lanthanum-cobalt-added 9-series strontium ferrite pre-sintered material and a recycled waste material according to a ratio to serve as raw materials, adding auxiliary materials, mixing, putting into a ball milling tank, adding water, carrying out sufficient ball milling, discharging from the tank, filtering water, magnetizing, pressurizing and forming in a pressing machine, heating and sintering a formed blank, and carrying out high-temperature sintering to obtain the lanthanum-cobalt-free strontium ferrite composite material. Grinding and drying to obtain the permanent magnetic ferrite; the process is simple, the breakdown voltage of the high-performance ferrite added with lanthanum and cobalt is greatly improved, the internal current of the ferrite under high voltage is reduced, meanwhile, the magnetic performance is ensured, and the application of the ferrite under high frequency is promoted.

The invention discloses a preparation method of environment-friendly plant-based transformer oil, and belongs to the technical field of high-temperature transformer oil. The lubricating oil comprises the following raw materials in percentage by mass: 1-8% of a viscosity index improver, 2-5% of an antioxidant, 0.05-0.2% of a demulsifying agent, 0.1-0.3% of an acid capturing agent and the balance of improved castor oil base oil. Various additives are added, so that the viscosity index and the oil-water separation capacity of the transformer oil can be improved, and hydrolysis can be inhibited; the castor oil is used as base oil, the transformer oil is endowed with degradability, and the castor oil base oil is improved, so that the flash point and breakdown voltage of the transformer oil can be improved; wherein the antioxidant and various groups in molecules can achieve a synergistic effect, so that the oxidation resistance of the transformer oil is remarkably enhanced; therefore, the prepared transformer oil is excellent in comprehensive performance, good in flash point, breakdown voltage and oxidation resistance and degradable, and has important application value in the technical field of high-temperature transformer oil.

The invention discloses a surface-modified composite fiber filter membrane as well as a preparation method and application thereof, and relates to the field of insulating oil filtration treatment. The preparation method comprises the following steps: uniformly stirring PVA powder, a solvent and ZrO2 nanoparticles to obtain a spinning solution; the spinning solution is prepared into the composite fiber filter membrane by adopting an electrostatic spinning technology, and the composite fiber filter membrane can be applied to the field of filtration and purification treatment of mineral insulating oil. The electrostatic spinning technology is adopted for preparing the filter membrane, the filter membrane has the advantages of being small in fiber diameter, good in uniformity, high in porosity and large in flux, ZrO2 nano particles are introduced into the filter membrane to increase the specific surface area and provide the impurity adsorption effect, trace moisture and micro impurities in the aged mineral insulating oil are adsorbed and intercepted, and the filter membrane has the advantages of being small in fiber diameter, good in uniformity, high in porosity and large in flux. Accurate filtering of the aged mineral insulating oil is achieved, the breakdown voltage of the aged insulating oil is effectively improved, and resource waste of the mineral insulating oil and pollution to the environment are reduced.

The present invention provides a terminal active region same design SiC power device and a preparation method thereof, and relates to the field of SiC power devices. In the terminal active region same design SiC power device, the channel injection region forming the cellular structure channel and the junction terminal injection region of the terminal region for forming the junction terminal are simultaneously formed by the same masking layer etching and ion implantation process. By adopting the same ion implantation structure in the terminal region and the active region, the problem of uncontrollable channel size during ion implantation of the corresponding channel caused by different etching side wall angles due to different pattern area densities is solved.

The application discloses a super-junction LDMOS device with high-resistance substrate TSV grounding and a manufacturing method thereof. The super-junction LDMOS device comprises a high-resistance substrate, a body region and a drift region formed in the high-resistance substrate, a body region contact region and a source region formed in the body region, a polysilicon gate formed on a substrate surface above the body region, and a drain region formed in the drift region. The drift region comprises a super-junction structure formed by a first column region and a second column region arranged at intervals in a gate width direction. A first buffer layer is arranged between the first column region and the drain region, a second buffer layer is arranged between the second column region and the drain region, and the first buffer layer and the second buffer layer are arranged to surround the drain region. The super-junction LDMOS device can effectively suppress substrate auxiliary effect, can realize optimal design of device breakdown voltage and on-resistance, and can reduce output capacitance of the device.

The invention relates to a load bearing plate for a high-voltage ceramic capacitor and a preparation method thereof, the load bearing plate for the high-voltage ceramic capacitor comprises a main body layer, and the surface of the main body layer is sequentially coated with a transition layer and an anti-sticking layer; the composition of the main body layer comprises Al2O3 and SiO2, the composition of the transition layer comprises Al2O3, SiO2, BaTiO3 and SrTiO3, and the composition of the anti-sticking layer comprises BaTiO3 and SrTiO3; and the high-voltage ceramic capacitor is composed of BaTiO3. According to the invention, the transition layer and the anti-sticking layer are sequentially coated on the main body layer, and the anti-sticking layer and the high-voltage ceramic capacitor are designed to have the same composition material, so that adhesion between the load bearing plate and the high-voltage ceramic capacitor can be prevented, the uniformity degree of the product is improved, and the breakdown voltage of the ceramic capacitor is improved.

The invention provides a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof. According to the transistor, a collector region, a field region silicon oxide layer, an outer base isolation layer, an outer base region polycrystalline silicon layer and an emitter region are sequentially formed on a substrate; afterwards, a metal or metal silicide shielding layer is arranged on the first dielectric layer covering the surface of the device, and the shielding layer is located above an area between any two of the collector electrode, the base electrode and the emitter electrode and then is covered by a second dielectric layer. The shielding layer can optimize the electric field distribution between the electrodes, significantly improve the breakdown voltage between the emitter and the base, between the collector and the base and between the collector and the emitter, and enhance the power capability and reliability of the device. Meanwhile, electric field coupling between the electrodes is effectively shielded, and related parasitic capacitance is greatly reduced. The improvement of the breakdown voltage and the reduction of the parasitic capacitance act together, and the current gain cut-off frequency, the maximum oscillation frequency and other core electrical properties of the transistor are directly improved.

The invention discloses a high-voltage strontium titanate ceramic material and application thereof, and belongs to the technical field of lead-free dielectric ceramic materials. The chemical general formula of the high-voltage strontium titanate ceramic material is (SrmAnBnCqDs) (TixEyFy) O3, wherein m + 2n + q + s = 1, m, n, q, sgt; 0, x + 2y = 1, xgt; 0, 0 < y < = 0.2; the element A and the element B form an A-B heterovalent element pair, the sum of element valence states of the A-B heterovalent element pair is 4, and at least one A-B heterovalent element pair is arranged; the element C and the element D are not element pairs, the valence states of the elements are positive bivalent, and the element A, the element B, the element C and the element D are different in composition elements; the element E and the element F form an EF hetero-valent element pair, the sum of element valence states of the EF hetero-valent element pair is 8, and at least one EF hetero-valent element pair is arranged. The breakdown voltage and capacitance of the high-voltage ceramic capacitor can be improved while the miniaturization of the high-voltage ceramic capacitor is maintained.

Disclosed are a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a semiconductor substrate; etching the substrate to form a trench in the substrate; filling the trench with insulating material; etching the insulating material to expose a sharp corner at the intersection of the trench sidewall and the upper surface of the substrate; and forming a field oxide layer on part of the upper surface of the substrate and the insulating material, wherein the sharp corner at the intersection of the trench sidewall and the upper surface of the substrate is oxidized in the step of forming the field oxide layer. The method exposes a sharp corner at the intersection of the shallow trench isolation structure and the substrate surface by etching back the shallow trench isolation structure, and eliminates the sharp corner in the step of forming the field oxide layer, thereby avoiding charge accumulation at the sharp corner and improving the breakdown voltage and reliability of the device.

The utility model relates to an integrated circuit. The integrated circuit mainly comprises a first groove and a second groove which are formed in the front face of a substrate and are in an annular shape, and the first groove and the second groove are filled with insulating materials. The first drift layer is implanted in the position, located on the inner side of the first groove, of the front face of the substrate, and the second drift layer is implanted in the position, located between the first groove and the second groove, of the front face of the substrate. The integrated circuit further comprises a connecting ring of the second conduction type implanted in the first drift layer and internally wound on the inner side of the top of the first groove, and a first emitter region and a contact region implanted in the first drift layer and located on the inner side of the connecting ring. The integrated circuit further comprises a doped ring of the first conductivity type implanted in the second drift layer and internally wound on the inner side of the second trench, and a second emitter region implanted in the second drift layer and externally wound on the outer side of the first trench. The first buried region and the second buried region are arranged alternately with each other and are arranged in the first drift layer and below the tie ring.

The application provides a detector pixel structure and an electronic detector. The detector pixel structure comprises a semiconductor substrate, a first and a second conductive type heavily doped layer, an insulating layer, an upper electrode, a lower electrode, an electron channel hole electrode, a metal protection ring and a doped ring; the doped ring is located in the semiconductor substrate and outside the first conductive type heavily doped layer and is exposed on the first surface of the semiconductor substrate; the insulating layer extends from the surface of a non-detection area to the surface of the semiconductor substrate, and the upper electrode extends from the surface of the non-detection area to the surface of the insulating layer; the electron channel hole electrode is located on the sidewall of the semiconductor substrate and is electrically connected to the lower electrode at one end and extends to the side surface of the insulating layer at the other end; and the metal protection ring is located on the surface of the semiconductor substrate and outside the upper electrode. The application can effectively avoid the image distortion caused by the deviation of the electron beam propagation direction, reduce the leakage current of the detector, improve the breakdown voltage and thus improve the detection performance.

The application discloses a metal oxide semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The metal oxide semiconductor device comprises a substrate, an N-type drift region and a P-type body region in the substrate, the N-type drift region and the P-type body region are arranged adjacently along the surface direction of the substrate, a drain electrode is formed on the N-type drift region, a first lightly-doped part, a heavily-doped part and a second lightly-doped part are sequentially arranged in the P-type body region along the direction perpendicular to the substrate, and the projection of the heavily-doped part on the substrate is located in the projection range of the first lightly-doped part and the second lightly-doped part on the substrate, a gate electrode is located on the substrate and covers the interface between the N-type drift region and the P-type body region, and an active electrode is formed in the second lightly-doped part. The metal oxide semiconductor device can improve the reliability of the device while keeping the performance of the device.

This application relates to the field of electrophoretic coating technology, and discloses a low-temperature curing epoxy cathodic electrophoretic coating and its preparation method. The low-temperature curing epoxy cathodic electrophoretic coating comprises 40-60 parts of cationic epoxy main resin, 10-25 parts of low-temperature blocked isocyanate curing agent, 15-30 parts of pigment and filler paste, 0.5-3 parts of neutralizing agent, 20-40 parts of deionized water, and 0.2-2 parts of additives; the cationic epoxy main resin is an amine-modified bisphenol A type epoxy resin with a number average molecular weight of 2500-5000; the unblocking temperature of the low-temperature blocked isocyanate curing agent is 90-120℃. The preparation method includes a first neutralization, pre-emulsion formation, pre-emulsion maturation, a second neutralization, and a second dispersion step. The low-temperature curing epoxy cathodic electrophoretic coating of this application has good dispersion and stability, and can form a continuous coating film.

This invention provides a field-effect transistor (FET), its fabrication method, and a power device thereof. The FET includes a substrate, a functional body, a gate dielectric, and a gate. The functional body includes a drift epitaxial region, a channel region, a source region, a first shielding region, and a second shielding region. Multiple gate trenches with their openings located on the surface away from the substrate are formed within the functional body. Each gate trench contains a gate and a gate dielectric. The channel region contacts the gate dielectric in one of the gate trenches and has a channel. The first shielding region is located between the channel region and another gate trench, and it contacts the gate dielectric in the other gate trench. The second shielding region is located below the gate trench and is connected to the first shielding region. The first and second shielding regions can significantly reduce the on-resistance of the device and increase its breakdown voltage.

This invention discloses a semiconductor device and a method for forming the same, wherein the semiconductor device includes: a semiconductor substrate; a gate structure located on the semiconductor substrate; a source region and a drain region located in the semiconductor substrate and on opposite sides of the gate structure; a sacrificial oxide layer located on the semiconductor substrate; a contact etch stop layer located on the sacrificial oxide layer; a lower interlayer dielectric layer located on the contact etch stop layer; a high-resistivity dielectric layer located on the gate structure and the lower interlayer dielectric layer; and a high-resistivity field plate, wherein the high-resistivity field plate is at least partially located on the high-resistivity dielectric layer.

The invention discloses a high electron mobility transistor chip and a preparation method thereof, and belongs to the technical field of semiconductors. The high electron mobility transistor chip comprises a substrate, and an alternating polarization layer, a first buffer layer, a second buffer layer, a channel layer, a barrier layer, a super junction layer and a cap layer which are sequentially stacked on the substrate, the alternate polarization layer comprises GaN layers and AlGaN layers which are periodically and alternately stacked to form a superlattice structure; the first buffer layer is a GaN layer; the second buffer layer is a C-doped GaN layer, and the C doping concentration of the second buffer layer is gradually increased along the epitaxial growth direction. According to the embodiment of the invention, the structure process can be effectively simplified, and the preparation cost is reduced.

The application provides an LDMOS device and a manufacturing method thereof. The LDMOS device comprises a substrate, a drift region of a first conductive type and a body region of a second conductive type in the substrate, a drain region of the first conductive type in the drift region, a source region of the first conductive type in the body region, the source region being spaced apart from the drift region, a gate structure on the substrate and covering part of surfaces of the drift region and the body region, the source region and the drain region being respectively on two sides of the gate structure, and the drain region being spaced apart from the gate structure, a self-aligned silicide blocking layer covering part of surfaces of the gate structure and part of surfaces of the drift region between the gate structure and the drain region, and a field plate at least partially arranged on the self-aligned silicide blocking layer between the gate structure and the drain region, wherein the field plate comprises an alloy compound layer. The application can reduce the difficulty of contact hole etching process and improve the switching speed of the LDMOS device.

The utility model provides a kind of LDMOS device.The LDMOS device, the recess and the convex part defined by recess have on the top surface of base, drain region is located in convex part, drift region is located in the base below recess bottom surface and part is located below drain region, the side surface of drain region is located above the top surface of drift region and the top surface of drift region is connected with the bottom surface of drain region, body region is located in the base below recess bottom surface and is located on the side of drift region away from drain region, gate structure is located in recess and covers part body region and part drift region, source region is located on the side of gate structure away from drain region, in the base below recess bottom surface and is located above body region.In this way, by setting recess on the top surface of base to raise drain region, the drain curvature effect disappears, and better surface electric field reduction effect is achieved.

The utility model relates to the technical field of transistor protection, and discloses a high-voltage MOS terminal protection structure with high avalanche tolerance, which comprises a high-voltage MOS device, the high-voltage MOS device is provided with a cellular area and a terminal protection area, the cellular area is also provided with a shield grid used for reducing on-resistance and increasing breakdown voltage, and the terminal protection area is provided with a terminal protection area. The longitudinal section of the shield grid is arranged in a trapezoid shape, the field limiting rings with the gradually-decreased spacing can widen the width of a depletion region, improve the transverse voltage endurance capability of the MOS device, reduce the peak value of an edge electric field, transfer the peak point of an electric field through a slope field plate and eliminate a grid angle distortion electric field, and the shield grid reconstructs the electric field to be distributed in a trapezoid shape and optimizes a longitudinal electric field. Therefore, the breakdown voltage of the MOS device is improved, and the avalanche trigger threshold is remarkably improved; through the design of the drain buffer layer, a large amount of high-energy carrier kinetic energy can be absorbed, the channel thermal shock can be reduced, the local temperature peak value can be reduced, the two metal layers are utilized to assist heat dissipation, double-path heat conduction is realized, and the avalanche tolerance is improved.

The present application relates to a kind of high-voltage Schottky diode with vertical AlGaN / GaN heterojunction and its preparation method, the preparation method includes the following steps: one, epitaxial material growth;Two, re-growth groove production and re-growth;Three, cathode production;Four, dielectric layer growth;Five, anode production.It utilizes the 2DEG (two-dimensional electron gas) in vertical direction formed by re-growth, can significantly improve the forward current of diode;While utilizing the PN junction formed by re-growth, can uniformly disperse peak electric field, improve electric field concentration effect, improve breakdown voltage, and, when reverse, PN junction can be more effectively reduced reverse leakage than Schottky junction.

This invention relates to a superjunction semiconductor device, comprising a first conductivity type substrate, a first conductivity type epitaxial layer, multiple layers disposed on the front side of the first conductivity type substrate, second conductivity type ions implanted into the first conductivity type epitaxial layer to form second conductivity type first pillar regions, at least two rows of second conductivity type first pillar regions, each row of second conductivity type first pillar regions connected to form second conductivity type first pillars, a first conductivity type second epitaxial layer disposed on the front side of the first conductivity type first epitaxial layer, a first trench formed on the first conductivity type second epitaxial layer, the first trench filled with a second conductivity type material to form second conductivity type second pillars, the second conductivity type second pillars and the second conductivity type first pillars being correspondingly disposed and connected to the corresponding second conductivity type first pillars. This invention has the effect of reducing uneven electric field distribution and reducing electromagnetic interference.

A semiconductor structure and a method for forming the same, wherein the semiconductor structure includes: a substrate comprising a plurality of first regions and an isolation region located between adjacent first regions; a first doped well region located within the first regions; an initial well region located within the isolation region, the initial well region having a conductivity type opposite to that of the first doped well regions, and the initial well region being in contact with the first doped well regions; and a first isolation well region located within the first doped well regions, the first isolation well region having a conductivity type opposite to that of the first doped well regions, wherein the distance from the edge of the first isolation well region to the edge of the initial well region is greater than zero and less than half the width of the initial well region, the width being the dimension of the initial well region along a direction parallel to the substrate and located between adjacent first regions. The semiconductor structure and the method for forming the same improve the electrical isolation effect of different regions in a transistor device, thereby improving device stability.

The present application relates to semiconductor devices and methods of manufacturing the same. A semiconductor device according to one embodiment of the present disclosure includes a conductive region, a terminal region at a termination portion of the conductive region, and a connection region between the conductive region and the terminal region. The conductive region includes an n+ type substrate, an n- type layer at a first surface of the n+ type substrate, and a p type region on the n- type layer, and a gate electrode filling an inside of a trench penetrating the p type region and located in the n- type layer, and a side wall of the trench at the termination portion of the conductive region is inclined.

This invention discloses a composite-terminated vertical Schottky diode combining a BaTiO3 / Si3N4 dielectric field plate and ion implantation. A composite dielectric layer composed of Si3N4 and BaTiO3 layers is used, with an anode field plate disposed on the composite dielectric layer. Fluorine ions are implanted into a drift layer below the anode to form a fluorine implantation region. Part of the fluorine implantation region is located below the anode, and another part is located below the composite dielectric layer, forming a composite termination. This composite termination structure effectively modulates the electric field distribution on the device surface and within the device bulk, ultimately effectively reducing the electric field strength at the anode edge and achieving a higher breakdown voltage. This provides an effective solution for the termination design of high-performance high-voltage Schottky diode power devices.

The invention relates to a high breakdown voltage enhanced gallium oxide field effect transistor and a preparation method thereof, the high breakdown voltage enhanced gallium oxide field effect transistor comprises a semi-insulating substrate, a buffer layer, a channel layer, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode, the buffer layer is located on the semi-insulating substrate; the channel layer is located on the buffer layer, and the channel layer is formed by sequentially connecting a first full-width channel, a plurality of first trapezoidal inclined channels, a multi-channel fin-type channel, a plurality of second trapezoidal inclined channels, a second full-width channel and a third full-width channel; the source electrode is located on the first full-width channel, and the drain electrode is located on the third full-width channel; the gate dielectric layer covers the plurality of first trapezoidal inclined channels, the multi-channel fin-type channel, the plurality of second trapezoidal inclined channels, the second full-width channel and the exposed surface of the buffer layer; the gate electrode wraps the gate dielectric layer on the surface of the multi-channel fin type channel. According to the transistor, high threshold voltage and good grid control capability of a device are ensured, on resistance of the device is reduced, breakdown voltage of the device is improved, and the transistor has better power characteristics.