69results about How to "Improve breakdown voltage" patented technology

The application discloses a super-junction LDMOS device with high-resistance substrate TSV grounding and a manufacturing method thereof. The super-junction LDMOS device comprises a high-resistance substrate, a body region and a drift region formed in the high-resistance substrate, a body region contact region and a source region formed in the body region, a polysilicon gate formed on a substrate surface above the body region, and a drain region formed in the drift region. The drift region comprises a super-junction structure formed by a first column region and a second column region arranged at intervals in a gate width direction. A first buffer layer is arranged between the first column region and the drain region, a second buffer layer is arranged between the second column region and the drain region, and the first buffer layer and the second buffer layer are arranged to surround the drain region. The super-junction LDMOS device can effectively suppress substrate auxiliary effect, can realize optimal design of device breakdown voltage and on-resistance, and can reduce output capacitance of the device.

The invention relates to a load bearing plate for a high-voltage ceramic capacitor and a preparation method thereof, the load bearing plate for the high-voltage ceramic capacitor comprises a main body layer, and the surface of the main body layer is sequentially coated with a transition layer and an anti-sticking layer; the composition of the main body layer comprises Al2O3 and SiO2, the composition of the transition layer comprises Al2O3, SiO2, BaTiO3 and SrTiO3, and the composition of the anti-sticking layer comprises BaTiO3 and SrTiO3; and the high-voltage ceramic capacitor is composed of BaTiO3. According to the invention, the transition layer and the anti-sticking layer are sequentially coated on the main body layer, and the anti-sticking layer and the high-voltage ceramic capacitor are designed to have the same composition material, so that adhesion between the load bearing plate and the high-voltage ceramic capacitor can be prevented, the uniformity degree of the product is improved, and the breakdown voltage of the ceramic capacitor is improved.

The invention provides a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof. According to the transistor, a collector region, a field region silicon oxide layer, an outer base isolation layer, an outer base region polycrystalline silicon layer and an emitter region are sequentially formed on a substrate; afterwards, a metal or metal silicide shielding layer is arranged on the first dielectric layer covering the surface of the device, and the shielding layer is located above an area between any two of the collector electrode, the base electrode and the emitter electrode and then is covered by a second dielectric layer. The shielding layer can optimize the electric field distribution between the electrodes, significantly improve the breakdown voltage between the emitter and the base, between the collector and the base and between the collector and the emitter, and enhance the power capability and reliability of the device. Meanwhile, electric field coupling between the electrodes is effectively shielded, and related parasitic capacitance is greatly reduced. The improvement of the breakdown voltage and the reduction of the parasitic capacitance act together, and the current gain cut-off frequency, the maximum oscillation frequency and other core electrical properties of the transistor are directly improved.

The invention discloses a high-voltage strontium titanate ceramic material and application thereof, and belongs to the technical field of lead-free dielectric ceramic materials. The chemical general formula of the high-voltage strontium titanate ceramic material is (SrmAnBnCqDs) (TixEyFy) O3, wherein m + 2n + q + s = 1, m, n, q, sgt; 0, x + 2y = 1, xgt; 0, 0 < y < = 0.2; the element A and the element B form an A-B heterovalent element pair, the sum of element valence states of the A-B heterovalent element pair is 4, and at least one A-B heterovalent element pair is arranged; the element C and the element D are not element pairs, the valence states of the elements are positive bivalent, and the element A, the element B, the element C and the element D are different in composition elements; the element E and the element F form an EF hetero-valent element pair, the sum of element valence states of the EF hetero-valent element pair is 8, and at least one EF hetero-valent element pair is arranged. The breakdown voltage and capacitance of the high-voltage ceramic capacitor can be improved while the miniaturization of the high-voltage ceramic capacitor is maintained.

Disclosed are a semiconductor device and a manufacturing method thereof. The manufacturing method comprises: providing a semiconductor substrate; etching the substrate to form a trench in the substrate; filling the trench with insulating material; etching the insulating material to expose a sharp corner at the intersection of the trench sidewall and the upper surface of the substrate; and forming a field oxide layer on part of the upper surface of the substrate and the insulating material, wherein the sharp corner at the intersection of the trench sidewall and the upper surface of the substrate is oxidized in the step of forming the field oxide layer. The method exposes a sharp corner at the intersection of the shallow trench isolation structure and the substrate surface by etching back the shallow trench isolation structure, and eliminates the sharp corner in the step of forming the field oxide layer, thereby avoiding charge accumulation at the sharp corner and improving the breakdown voltage and reliability of the device.

The application provides a detector pixel structure and an electronic detector. The detector pixel structure comprises a semiconductor substrate, a first and a second conductive type heavily doped layer, an insulating layer, an upper electrode, a lower electrode, an electron channel hole electrode, a metal protection ring and a doped ring; the doped ring is located in the semiconductor substrate and outside the first conductive type heavily doped layer and is exposed on the first surface of the semiconductor substrate; the insulating layer extends from the surface of a non-detection area to the surface of the semiconductor substrate, and the upper electrode extends from the surface of the non-detection area to the surface of the insulating layer; the electron channel hole electrode is located on the sidewall of the semiconductor substrate and is electrically connected to the lower electrode at one end and extends to the side surface of the insulating layer at the other end; and the metal protection ring is located on the surface of the semiconductor substrate and outside the upper electrode. The application can effectively avoid the image distortion caused by the deviation of the electron beam propagation direction, reduce the leakage current of the detector, improve the breakdown voltage and thus improve the detection performance.

The application discloses a metal oxide semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The metal oxide semiconductor device comprises a substrate, an N-type drift region and a P-type body region in the substrate, the N-type drift region and the P-type body region are arranged adjacently along the surface direction of the substrate, a drain electrode is formed on the N-type drift region, a first lightly-doped part, a heavily-doped part and a second lightly-doped part are sequentially arranged in the P-type body region along the direction perpendicular to the substrate, and the projection of the heavily-doped part on the substrate is located in the projection range of the first lightly-doped part and the second lightly-doped part on the substrate, a gate electrode is located on the substrate and covers the interface between the N-type drift region and the P-type body region, and an active electrode is formed in the second lightly-doped part. The metal oxide semiconductor device can improve the reliability of the device while keeping the performance of the device.

This application relates to the field of electrophoretic coating technology, and discloses a low-temperature curing epoxy cathodic electrophoretic coating and its preparation method. The low-temperature curing epoxy cathodic electrophoretic coating comprises 40-60 parts of cationic epoxy main resin, 10-25 parts of low-temperature blocked isocyanate curing agent, 15-30 parts of pigment and filler paste, 0.5-3 parts of neutralizing agent, 20-40 parts of deionized water, and 0.2-2 parts of additives; the cationic epoxy main resin is an amine-modified bisphenol A type epoxy resin with a number average molecular weight of 2500-5000; the unblocking temperature of the low-temperature blocked isocyanate curing agent is 90-120℃. The preparation method includes a first neutralization, pre-emulsion formation, pre-emulsion maturation, a second neutralization, and a second dispersion step. The low-temperature curing epoxy cathodic electrophoretic coating of this application has good dispersion and stability, and can form a continuous coating film.

This invention provides a field-effect transistor (FET), its fabrication method, and a power device thereof. The FET includes a substrate, a functional body, a gate dielectric, and a gate. The functional body includes a drift epitaxial region, a channel region, a source region, a first shielding region, and a second shielding region. Multiple gate trenches with their openings located on the surface away from the substrate are formed within the functional body. Each gate trench contains a gate and a gate dielectric. The channel region contacts the gate dielectric in one of the gate trenches and has a channel. The first shielding region is located between the channel region and another gate trench, and it contacts the gate dielectric in the other gate trench. The second shielding region is located below the gate trench and is connected to the first shielding region. The first and second shielding regions can significantly reduce the on-resistance of the device and increase its breakdown voltage.

This invention discloses a semiconductor device and a method for forming the same, wherein the semiconductor device includes: a semiconductor substrate; a gate structure located on the semiconductor substrate; a source region and a drain region located in the semiconductor substrate and on opposite sides of the gate structure; a sacrificial oxide layer located on the semiconductor substrate; a contact etch stop layer located on the sacrificial oxide layer; a lower interlayer dielectric layer located on the contact etch stop layer; a high-resistivity dielectric layer located on the gate structure and the lower interlayer dielectric layer; and a high-resistivity field plate, wherein the high-resistivity field plate is at least partially located on the high-resistivity dielectric layer.

The invention discloses a high electron mobility transistor chip and a preparation method thereof, and belongs to the technical field of semiconductors. The high electron mobility transistor chip comprises a substrate, and an alternating polarization layer, a first buffer layer, a second buffer layer, a channel layer, a barrier layer, a super junction layer and a cap layer which are sequentially stacked on the substrate, the alternate polarization layer comprises GaN layers and AlGaN layers which are periodically and alternately stacked to form a superlattice structure; the first buffer layer is a GaN layer; the second buffer layer is a C-doped GaN layer, and the C doping concentration of the second buffer layer is gradually increased along the epitaxial growth direction. According to the embodiment of the invention, the structure process can be effectively simplified, and the preparation cost is reduced.

The utility model provides a kind of LDMOS device.The LDMOS device, the recess and the convex part defined by recess have on the top surface of base, drain region is located in convex part, drift region is located in the base below recess bottom surface and part is located below drain region, the side surface of drain region is located above the top surface of drift region and the top surface of drift region is connected with the bottom surface of drain region, body region is located in the base below recess bottom surface and is located on the side of drift region away from drain region, gate structure is located in recess and covers part body region and part drift region, source region is located on the side of gate structure away from drain region, in the base below recess bottom surface and is located above body region.In this way, by setting recess on the top surface of base to raise drain region, the drain curvature effect disappears, and better surface electric field reduction effect is achieved.

The utility model relates to the technical field of transistor protection, and discloses a high-voltage MOS terminal protection structure with high avalanche tolerance, which comprises a high-voltage MOS device, the high-voltage MOS device is provided with a cellular area and a terminal protection area, the cellular area is also provided with a shield grid used for reducing on-resistance and increasing breakdown voltage, and the terminal protection area is provided with a terminal protection area. The longitudinal section of the shield grid is arranged in a trapezoid shape, the field limiting rings with the gradually-decreased spacing can widen the width of a depletion region, improve the transverse voltage endurance capability of the MOS device, reduce the peak value of an edge electric field, transfer the peak point of an electric field through a slope field plate and eliminate a grid angle distortion electric field, and the shield grid reconstructs the electric field to be distributed in a trapezoid shape and optimizes a longitudinal electric field. Therefore, the breakdown voltage of the MOS device is improved, and the avalanche trigger threshold is remarkably improved; through the design of the drain buffer layer, a large amount of high-energy carrier kinetic energy can be absorbed, the channel thermal shock can be reduced, the local temperature peak value can be reduced, the two metal layers are utilized to assist heat dissipation, double-path heat conduction is realized, and the avalanche tolerance is improved.

The present application relates to a kind of high-voltage Schottky diode with vertical AlGaN / GaN heterojunction and its preparation method, the preparation method includes the following steps: one, epitaxial material growth;Two, re-growth groove production and re-growth;Three, cathode production;Four, dielectric layer growth;Five, anode production.It utilizes the 2DEG (two-dimensional electron gas) in vertical direction formed by re-growth, can significantly improve the forward current of diode;While utilizing the PN junction formed by re-growth, can uniformly disperse peak electric field, improve electric field concentration effect, improve breakdown voltage, and, when reverse, PN junction can be more effectively reduced reverse leakage than Schottky junction.

This invention relates to a superjunction semiconductor device, comprising a first conductivity type substrate, a first conductivity type epitaxial layer, multiple layers disposed on the front side of the first conductivity type substrate, second conductivity type ions implanted into the first conductivity type epitaxial layer to form second conductivity type first pillar regions, at least two rows of second conductivity type first pillar regions, each row of second conductivity type first pillar regions connected to form second conductivity type first pillars, a first conductivity type second epitaxial layer disposed on the front side of the first conductivity type first epitaxial layer, a first trench formed on the first conductivity type second epitaxial layer, the first trench filled with a second conductivity type material to form second conductivity type second pillars, the second conductivity type second pillars and the second conductivity type first pillars being correspondingly disposed and connected to the corresponding second conductivity type first pillars. This invention has the effect of reducing uneven electric field distribution and reducing electromagnetic interference.

A semiconductor structure and a method for forming the same, wherein the semiconductor structure includes: a substrate comprising a plurality of first regions and an isolation region located between adjacent first regions; a first doped well region located within the first regions; an initial well region located within the isolation region, the initial well region having a conductivity type opposite to that of the first doped well regions, and the initial well region being in contact with the first doped well regions; and a first isolation well region located within the first doped well regions, the first isolation well region having a conductivity type opposite to that of the first doped well regions, wherein the distance from the edge of the first isolation well region to the edge of the initial well region is greater than zero and less than half the width of the initial well region, the width being the dimension of the initial well region along a direction parallel to the substrate and located between adjacent first regions. The semiconductor structure and the method for forming the same improve the electrical isolation effect of different regions in a transistor device, thereby improving device stability.

This invention discloses a composite-terminated vertical Schottky diode combining a BaTiO3 / Si3N4 dielectric field plate and ion implantation. A composite dielectric layer composed of Si3N4 and BaTiO3 layers is used, with an anode field plate disposed on the composite dielectric layer. Fluorine ions are implanted into a drift layer below the anode to form a fluorine implantation region. Part of the fluorine implantation region is located below the anode, and another part is located below the composite dielectric layer, forming a composite termination. This composite termination structure effectively modulates the electric field distribution on the device surface and within the device bulk, ultimately effectively reducing the electric field strength at the anode edge and achieving a higher breakdown voltage. This provides an effective solution for the termination design of high-performance high-voltage Schottky diode power devices.

The invention relates to a high breakdown voltage enhanced gallium oxide field effect transistor and a preparation method thereof, the high breakdown voltage enhanced gallium oxide field effect transistor comprises a semi-insulating substrate, a buffer layer, a channel layer, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode, the buffer layer is located on the semi-insulating substrate; the channel layer is located on the buffer layer, and the channel layer is formed by sequentially connecting a first full-width channel, a plurality of first trapezoidal inclined channels, a multi-channel fin-type channel, a plurality of second trapezoidal inclined channels, a second full-width channel and a third full-width channel; the source electrode is located on the first full-width channel, and the drain electrode is located on the third full-width channel; the gate dielectric layer covers the plurality of first trapezoidal inclined channels, the multi-channel fin-type channel, the plurality of second trapezoidal inclined channels, the second full-width channel and the exposed surface of the buffer layer; the gate electrode wraps the gate dielectric layer on the surface of the multi-channel fin type channel. According to the transistor, high threshold voltage and good grid control capability of a device are ensured, on resistance of the device is reduced, breakdown voltage of the device is improved, and the transistor has better power characteristics.

The present invention is a laminated structure having at least a base substrate and a crystalline oxide film containing gallium oxide as a main component, wherein an average value of reflectance of light having a wavelength of 400 to 800 nm is 16% or greater on a surface on a side of the crystalline oxide film of the laminated structure. Thus, the present invention provides a laminated structure having a crystalline oxide film containing gallium oxide as a main component with extremely few crystal defects, excellent crystallinity, and excellent semiconductor properties when applied to a semiconductor device.

The invention discloses a gallium oxide heterojunction diode with a vertical structure and a preparation method. The gallium oxide heterojunction diode comprises a gallium oxide epitaxial wafer; the P-type oxide is located in the middle area of the upper surface of the gallium oxide epitaxial wafer; the two sides of the P-type oxide are of an arc-shaped structure, and the curvature radius of the arc-shaped structure is smaller than 3 microns. The SiO2 field plates are located on the two sides of the P-type oxide and make contact with the P-type oxide; the anode electrode is located on the P-type oxide and part of the SiO2 field plate; and the cathode electrode is positioned on the lower surface of the gallium oxide epitaxial wafer. According to the device structure designed by the invention, reverse leakage current is effectively inhibited, the breakdown voltage of the device is effectively improved, and the performance and reliability of the device are greatly improved.

The application discloses a GPP rectifier diode chip with a gradient-doped composite glass passivation layer, and belongs to the technical field of semiconductor devices. The GPP rectifier diode chip with the gradient-doped composite glass passivation layer comprises a base substrate, a gradient diffusion zone and a composite glass passivation layer. The application solves the problems of poor interface charge stability, large leakage current and insufficient long-term reliability of a conventional single-layer or multi-layer glass passivation layer of an existing GPP rectifier diode chip. The first gradient distribution of the resistivity of the base substrate along the thickness direction, the second gradient distribution of the impurity concentration of the gradient diffusion zone surface along the transverse direction and the composite glass passivation layer with periodic fluctuation of carbon content inhibit the concentration effect of the junction edge electric field, improve the interface matching property and compactness of the passivation layer and the semiconductor surface, thereby reducing the leakage current, and improving the voltage resistance and long-term working stability of the device.

The invention discloses a process method and process equipment of a semiconductor device. The process method comprises the following steps: acquiring a substrate with an original thin film; introducing a first gas into the process cavity; high-temperature plasma treatment is conducted on the first gas, so that the first gas is ionized and excited to release ultraviolet photons, the ultraviolet photons penetrate through the surface of the original thin film, impurity atoms in the original thin film are removed, and the energy of the ultraviolet photons generated by the first gas is larger than the chemical bond energy of the impurity atoms. By executing the steps, the defect density in the tunneling layer thin film can be reduced, so that the overall quality of the thin film is improved, the occurrence of leakage current of the memory can be effectively reduced, the service life of the memory is prolonged, the breakdown voltage of the memory can be improved, and the reliability of the memory is improved.

This application discloses a dielectric gradient coating for insulating separators, its preparation method, and its application, belonging to the technical field of electrical equipment insulation materials. The method includes the following steps: (1) adding ethylenediamine and perfluorooctyltrimethoxysilane to a solvent to obtain a modified solution, and then adding nano-graphene to the modified solution to obtain fluoroammonia-modified graphene; (2) mixing the first and second dispersions prepared from the fluoroammonia-modified graphene and magnesium-aluminum hydrotalcite respectively to obtain electrostatic spraying liquids with different concentration gradients; (3) sequentially electrostatically spraying the electrostatic spraying liquids with different concentration gradients onto the surface of the separator to form a dielectric gradient coating, wherein the dielectric constant in the dielectric gradient coating increases from the inside to the outside. In this method, the fluoroammonia-modified graphene is uniformly dispersed in epoxy resin and improves the density of the epoxy resin, thereby increasing the bonding force between the coating and the substrate, and thus improving the service life of the insulating separator under high temperature and high humidity conditions.

The present disclosure relates to a HEMT device and a manufacturing method thereof, the HEMT device comprising: a substrate; an epitaxial layer disposed on the substrate, the epitaxial layer comprising: a first semiconductor stack and a second semiconductor layer disposed on the first semiconductor stack; a two-dimensional electron gas formed at an interface between the first semiconductor stack and the second semiconductor layer; a terminal layer comprising a source, a drain and a gate disposed on the second semiconductor layer and arranged at intervals; a conductive layer disposed within the epitaxial layer and located between the substrate and the two-dimensional electron gas; an electrical coupling structure extending from the gate into the epitaxial layer and connected with the conductive layer, for electrically coupling the conductive layer to the gate; a high-resistance structure at least partially disposed between the conductive layer and the two-dimensional electron gas, and between the electrical coupling structure and the two-dimensional electron gas. The HEMT device can effectively reduce the electric field intensity of the gate under high voltage of the HEMT device, thereby improving the breakdown voltage of the device.

The application provides an insulation device for isolating high-voltage electrodes in a vacuum environment, comprising: an insulator comprising a first end face and a second end face opposite to each other, the first end face being connected with a first electrode, the second end face being connected with a second electrode, the first electrode and the second electrode being located in the vacuum environment, and the electric potential of the first electrode being less than that of the second electrode; wherein the surface layer of the first end face of the insulator and the surface layer in the vicinity of the side face of the first end face are covered with a conductive layer. The application improves the electric field at the electrode, the insulator and the vacuum contact surface, thereby improving the voltage resistance performance of the insulator in the vacuum environment.

The invention provides a ceramic glaze composition, a preparation method of a semiconductor equipment part, the semiconductor equipment part and semiconductor equipment. The preparation method comprises the following steps: providing a first melting material, a second melting material and a semiconductor equipment part body; the first melting material comprises Al2O3, a corrosion-resistant additive and SiO2; the second melting material comprises SiO2, SiC and boride; respectively melting the first melting material and the second melting material, and uniformly mixing to obtain a ceramic glaze composition; applying a ceramic glaze composition to enable the ceramic glaze composition to at least cover part of the surface of the semiconductor equipment part body; and sintering to form a ceramic glaze layer on the surface of the semiconductor equipment part body. The mixed melting material is applied to the surface of the semiconductor equipment part body, and then the ceramic glaze layer is formed through high-temperature sintering, so that compared with a traditional anodic oxidation layer, the corrosion resistance is improved, the breakdown voltage resistance is improved, and the thermal cycle performance is also obviously improved.

The invention relates to a gallium oxide heterojunction diode with high voltage resistance. The JBS comprises an active region and at least one JBS unit, and the JBS unit comprises a cellular groove prepared in the N-type gallium oxide drift layer and anode metal located in the cellular groove and electrically connected with a gallium oxide heterojunction of the active region; the source region gallium oxide heterojunction comprises a source region first doped p-type nickel oxide region which is at least distributed below the groove bottom of the cellular groove and is in contact with the N-type gallium oxide drift layer; and a source region protection unit which at least covers a corner region of the first doped p-type nickel oxide region of the source region and forms a gradient JTE effect with the first doped p-type nickel oxide region of the source region is arranged on the cross section of the diode. According to the gallium oxide heterojunction diode, the electric field distribution of the gallium oxide heterojunction diode can be optimized, the breakdown voltage of the gallium oxide heterojunction diode is improved, and the requirement of a high-voltage power electronic application scene for the voltage resistance performance of the diode is met.

The utility model provides a kind of ultrahigh pressure MOSFET terminal structure, above-mentioned terminal structure includes: substrate, it is in and set up main knot and VLD knot, the depth of the VLD knot gradually becomes smaller along the direction away from the main knot;Oxide layer is located on the substrate;Polysilicon field plate is located on the oxide layer;Dielectric layer is located on the polysilicon field plate;And metal field plate is located on the dielectric layer.The utility model embodiment is changed by setting VLD knot and its depth, and is matched with polysilicon field plate and metal field plate, while guaranteeing high pressure resistance, so that terminal structure is shorter, cost is less, and reliability is higher.

According to the preparation method of the novel split-gate power MOSFET device and the device provided by the embodiment of the invention, a PN junction can be directly formed between an N-type epitaxial layer and the P-type second source polycrystalline silicon mainly by filling a cell region groove with the P-type second source polycrystalline silicon, the electric field intensity near the side wall is improved by the structure by utilizing the large-area PN junction, and the performance of the device is improved. The overall breakdown voltage of the device is improved; meanwhile, the concentration of the epitaxial layer is improved or the thickness of the epitaxial layer is reduced, so that the conduction impedance is reduced, the injection concentration of the second source polycrystalline silicon is adjusted through a process, so that a reverse biased PN junction electric field formed by the second source polycrystalline silicon and the epitaxial layer is adjusted, the device performance can be balanced and adjusted, and the conduction resistance can be optimized; the electric field of the device can reach a peak value, the waste of the depth of the groove is avoided, and the whole electric field distribution can reach a balanced state.

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.