538results about How to "Improve breakdown voltage" patented technology

A silicon carbide semiconductor device capable of achieving a decrease in ON resistance and an increase in breakdown voltage and a method for manufacturing a silicon carbide semiconductor device. A silicon carbide semiconductor device includes a silicon carbide substrate and a drift layer. The drift layer includes a breakdown voltage holding layer extending from a point where a doping concentration has a predetermined value to a surface of the drift layer. The doping concentration in the breakdown voltage holding layer continuously decreases from the point where the doping concentration has the predetermined value to a modulation point located further toward the surface of the drift layer than a midpoint in a film thickness direction of the breakdown voltage holding layer. The doping concentration in the breakdown voltage holding layer continuously increases from the modulation point to the surface of the drift layer.

An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.

Methods and devices for fabricating AlGaN/GaN normally-off high electron mobility transistors (HEMTs). A fluorine-based (electronegative ions-based) plasma treatment or low-energy ion implantation is used to modify the drain-side surface field distribution without the use of a field plate electrode. The off-state breakdown voltage can be improved and current collapse can be completely suppressed in LDD-HEMTs with no significant degradation in gains and cutoff frequencies.

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.

In accordance with an embodiment of the invention, a superjunction semiconductor device includes an active region and a termination region surrounding the active region. A central vertical axis of a boundary column of a second conductivity type material defines the boundary between the active region and the termination region. The active and termination regions include columns of first and second conductivity type material alternately arranged along a horizontal direction in a semiconductor region having top and bottom surfaces. At least one of the columns of the first conductivity type material in the termination region has a different width than a width of the columns of the first conductivity type material in the active region.

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

A MOS-gated power semiconductor device is described. The MOS-gated power semiconductor device includes a semiconductor substrate that is heavily doped with impurities of a first conductivity type and used as a collector region, a drift region lightly doped with impurities of a second conductivity type on the substrate, a gate insulating layer on the drift region having a center thicker than its edges, a gate electrode on the gate insulating layer, a well region that is lightly doped with impurities of a first conductivity type on the drift region and that has a channel region overlapping a portion of the gate electrode, an emitter region that is heavily doped with impurities of a second conductivity type and that contacts the channel region, an emitter electrode electrically connected to the emitter region and isolated from the gate electrode, and a collector electrode electrically connected to the semiconductor substrate.

A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base.

This invention discloses configurations and methods to manufacture lateral power device including a super junction structure with an avalanche clamp diode formed between the drain and the gate. The lateral super-junction structure reduces on-resistance, while the structural enhancements, including an avalanche clamping diode and an N buffer region, increase the breakdown voltage between substrate and drain and improve unclamped inductive switching (UIS) performance.

The invention relates to a carrier-storing grooved gate IGBT with a P-type floating layer, belonging to the technical field of semiconductor power devices. On a basis of the prior carrier-storing grooved gate bipolar transistor, a P-type floating layer (13) is introduced to almost free a carrier-storing layer from bearing a withstanding voltage and decrease a forward conducted voltage drop; and the P-type floating layer (13) also improves the electric-field integration effect of the bottom of the grooved gate, thereby effectively decreasing an electric filed with a maximum peak value, preventing the bottom of the grooved gate and the vicinity of the high-concentration carrier-storing layer from being broken down by an overhigh electric field and greatly increasing the breakdown voltage of the device. A JFET zone is introduced due to the existence of the P-type floating layer. When the device is forwardly conducted, the resistance of the JFET zone continuously increases along with the continuously increasing voltage of a collector so that the saturation current of the device is decreased, and a lower conducted voltage drop is obtained while maintaining a greater short-circuit safety operation area (SCSOA).

A semiconductor device includes a first conductive type first semiconductor region, a second semiconductor region, and a second conductive type lateral RESURF region. The first semiconductor region is arranged on a first electrode side. The second semiconductor region includes first conductive type first pillar regions and a terminal part. The second pillar regions are alternately arranged on an element part. The terminal part is formed around the element part along a surface of the first semiconductor region on a second electrode side opposite to the first electrode side of the first semiconductor region. Furthermore, the second conductive type lateral RESURF region is formed in the second semiconductor region on the terminal part.

A method and apparatus are provided for improving a breakdown voltage of a semiconductor device. The method includes the steps of coupling an electrode of the silicon-carbide diode to a drift layer of the semiconductor device through a charge transfer junction, said drift layer being of a first doping type and providing a junction termination layer of a relatively constant thickness in direct contact with the drift layer of the semiconductor device and in direct contact with an outside edge of the charge transfer junction, said junction termination layer extending outwards from the outside edge of the charge transfer junction, said junction termination layer also being doped with a doping material of a second doping type in sufficient concentration to provide a charge depletion region adjacent the outside edge of the charge transfer junction when the charge transfer junction is reverse biased.

The invention relates to a stuffing for a capacitor. The stuffing for the capacitor, according to the quality percentage, comprises 20% to 40% of vegetable oil, 2% to10% of paraffin, 45% to75% of stuffing, and 0.5% to 5% of vegetable oil antioxidant additives. The preparation method of the stuffing for the capacitor includes the following procedures: the vegetable oil is heated up to 80 DEG C to 120 DEG C, is under vacuum treatment at least 8 hours, then breaking the vacuum, is added into vegetable oil antioxidant additives, and is under vacuum treatment again at least 8 hours with the temperature keeping in the range of 80 DEG C to 120 DEG C. The paraffin is heated up to 70 DEG C to 120 DEG C to melt. The stuffing for the capacitor can be obtained through mixing the vegetable oil after the heat treatment, melted paraffin and the stuffing together. The stuffing for the capacitor has electrical performance and physics and chemistry performance.

The invention relates to a SiGe bipolar complementary metal oxide semiconductor (BiCMOS) radio-frequency power amplifier. The amplifier comprises a first-stage pre-amplification transistor, a second-stage power amplification transistor, a first-stage biasing circuit, a second-stage biasing circuit, an input matching network and an impedance conversion network. The circuit structure of the invention consists of a first-stage pre-amplification circuit and a second-stage power amplification circuit which are connected with each other through a coupling capacitor. The first-stage pre-amplification transistor is a standard SiGe transistor, and the linearity of the circuit is enhanced by a remote control (RC) serial feedback circuit; and the second-stage power amplification transistor is a high-voltage SiGe transistor and can reach relatively high output power. Both the first biasing circuit and the second biasing circuit have bipolar transistor current mirror structures, and temperature stability is enhanced by temperature negative feedback technology. The amplifier has high linearity and relatively high output power.

The invention discloses an edge terminal structure of a high-voltage power semiconductor device. The edge terminal structure comprises a plurality of field limiting rings which wind the power semiconductor device and have a conduction type opposite to that of a substrate; one or two side of each field limiting ring is provided with a doped region which has a conduction type the same as that of the field limiting ring and the doping concentration smaller than that of the field limiting ring; the field limiting rings are coated with field plates; and the field limiting rings and the field plates are separated by silicon dioxide layers. The material of the field plate can be selected from copper, aluminum, polysilicon, oxygen-doped polysilicon and the like. The doped regions with lower concentration are added around the conventional field limiting rings, so the intensity of electric field lines of an edge cellular can be effectively reduced, the electric field strength borne by the edge cellular is reduced, the breakdown voltage is improved, the area efficiency of the edge terminal structure is effectively improved, the chip area is saved, and the chip cost is reduced.

A polysilicon layer and a first patterned photoresist layer are formed on a substrate. An ultraviolet curing process is performed to cure the first patterned photoresist layer. Then, a gate structure is formed by using the first patterned photoresist layer as a hard mask. A second patterned photoresist layer is formed on the substrate. The second patterned photoresist layer, the cured remaining first patterned photoresist layer and the gate form two openings alongside the gate structure. Finally, via the openings, two consecutive ion implantation processes are performed to form a double diffuse drain (DDD) structure.

The invention relates to a deep trench high-power MOS device and the manufacturing method. The MOS device is arranged on an overlooking plane, a central area is provided with an array which consists of parallel connected single cells, the periphery of the single-cell array is provided with a terminal protection structure, the terminal protection structure consists of at least one protection ring which is arranged at an inner ring and a stop ring which is positioned at an outer ring; as both the protection ring and the stop ring adopt trench type conductive polysilicon, and a single-cell grid electrode lead wire adopts the method of directly opening a hole to lead the wire on the trench type conductive polysilicon in the manufacturing process of the device; compared with the manufacturing method of existing common plane type deep trench high-power MOS device with a field-plate structure, the invention can reduce two lithographys and corresponding processes under the premise of not affecting the performances of the device, thus greatly reducing manufacturing cost. At the same time, the invention adopts one time phosphorus injection, then one time boron injection and matching annealing processes are adopted to regulate the conductive polysilicon resistance, thereby greatly reducing the leakage current between a grid and a source and ensuring to obtain a reasonable threshold voltage under the premise of not increasing the concentration of an N-well.

A semiconductor device includes: a semiconductor layer of a first conductivity type; a base region of a second conductivity type formed on a surface of the semiconductor layer of the first conductivity type; a plurality of first column regions of the second conductivity type formed in a matrix fashion in the semiconductor layer when seen in a plan view; a trench gate formed in a grid fashion in the semiconductor layer so that each of the first column regions is surrounded by the trench gate when seen in a plan view, the trench gate penetrating through the base region to reach the semiconductor layer of the first conductivity type; and a plurality of second column regions of the second conductivity type selectively formed below each intersection of the grid of the trench gate except line section of the trench gate.

A mask-configurable smart power integrated circuit includes arrays of associated NMOS FETs that perform functions such as control, amplification and sampling of output variables. The arrays include NMOS basic cells using FET arrangements such as LDD, LDSD-NMOS, LDMOS, or N-channel DMOS. The smart power integrated circuits are useful to provide switching to power cells and drives, and protection from overload conditions.

A voltage converting circuit and a battery device, aimed at the problem that the breakdown voltage required for the driving input of the selected switch element is increased as the potential of the selected power storage device is increased when a power storage device is selected from a plurality of power storage devices that are connected in series. A certain drive voltage for turning on p-type MOS transistors Q3, Q4 of selection circuit 121 is generated based on a certain drive current Ion flowing from one power storage element to ground level GND. In other words, even if the power storage device selected by selection circuit 121 has a high potential with respect to ground level GND, the drive voltage applied between the gate and source of MOS transistors Q3, Q4 can be held substantially constant.

Embodiments of a high temperature electromagnetic coil assembly are provided, as are embodiments of a method for fabricating such a high temperature electromagnetic coil assembly. In one embodiment, the method includes the steps of applying a high thermal expansion ceramic coating over an anodized aluminum wire, coiling the coated anodized aluminum wire around a support structure, and curing the high thermal expansion ceramic coating after coiling to produce an electrically insulative, high thermal expansion ceramic body in which the coiled anodized aluminum wire is embedded.

The invention relates to a super junction lateral double-diffused metal-oxide semiconductor (LDMOS) device and belongs to the field of semiconductor power devices. By means of the super junction LDMOS device, evenly distributed N+ islands are embedded in a P type substrate of a traditional super junction LDMOS device, and a P type electric field screening buried layer is added between an active area and the substrate. An N+ island (2) can improve longitudinal withstand voltage of the device by enhancing internal electric field, simultaneously generates extra electric charge to eliminate substrate auxiliary depletion effect, and further improves breakdown voltage of the device. The P type electric field screening buried layer (3) can screen high electric fields generated by an N+ island near an active end, lower electric field peak value near the active area, and form super junction with an N type cushion layer; and a super junction drift area is provided, the device is enabled to have multiple super junction structures, accordingly electric field distribution inside the device can be effectively improved, breakdown voltage of the device is improved, conduction ratio resistance of the device is simultaneously lowered by improving dosage concentration of the drift area, and finally the aim of effectively reducing device area and lower device cost can be achieved.

Provided is a semiconductor device and a method for forming the same. The device has a substrate including one and another surfaces. A first semiconductor region of a first conductivity type is formed in the substrate. A second conductivity type, second semiconductor region is provided in a first surface layer, that includes the one surface, of the substrate. A first electrode is in contact with the second semiconductor region to form a junction therebetween. A first conductivity type, third semiconductor region is provided in a second surface layer, that includes the another surface, of the substrate. The third semiconductor region has a higher impurity concentration than the first semiconductor region. A fourth semiconductor region of the second conductivity type is provided in the first semiconductor region at a location deeper than the third semiconductor region from the another surface. A second electrode is in contact with the third semiconductor region.

Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a bird's beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the bird's beak region and terminating at the inner edge of the bird's beak region, a gate crossing the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the guard region. A variation of a local oxidation of silicon process is used with an additional bird's beak implantation mask as well as minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.

The invention discloses a high-breakdown gallium nitride-based field effect transistor device and a manufacturing method thereof. The manufacturing method comprises the following steps of: growing a nucleating layer on a substrate; growing an aluminum-gallium-nitrogen high-resistance buffering layer with a low aluminum component on the nucleating layer; growing a high-mobility gallium nitride channel layer on the aluminum-gallium-nitrogen high-resistance buffering layer; growing a thin aluminum nitride isolating layer on the gallium nitride channel layer; growing an aluminum-gallium-nitrogen barrier layer on the aluminum nitride isolating layer; growing a thin nitride cap layer on the aluminum-gallium-nitrogen barrier layer; and forming a source electrode, a drain electrode and a grid electrode on the nitride cap layer. According to the method, the process complexity is lowered, the breakdown voltage of the gallium nitride-based field effect transistor device is increased effectively, and the mobility of electrons in a channel is increased simultaneously.

A semiconductor device 10 may comprise an element domain 40 and a termination domain 50 that surrounds the element domain 40. The element domain 40 and the termination domain 50 respectively may comprise a second conductive type drift region 18. A gate trench 38 may be provided in the element domain 40. The termination domain 50 may be provided with a termination trench 22 surrounding the element domain. A first conductive type floating region surrounded by the drift region 18 is not provided at a bottom of the gate trench 38, and a first conductive type floating region 20 surrounded by the drift region 18 is provided at a bottom of the termination trench 22.

A laterally double diffused metal oxide semiconductor transistor of an N-shaped silicon-on-insulator (SOI) comprises a semiconductor substrate. A buried oxide is arranged on the semiconductor substrate, an N-shaped doped semiconductor drift region is arranged on the buried oxide and a P-shaped well region is arranged above the N-shaped doped semiconductor drift region, and a field oxide, a metal layer, a gate oxide, a polysilicon gate and an oxide layer are arranged on the surface of the transistor. An N-shaped source region and a P-shaped contact region are arranged in a P-shaped well. The transistor is characterized in that the transistor also comprises at least a layer of floating oxide structure which is positioned in the N-shaped doped semiconductor drift region between a drain region and the buried oxide; moreover, a plurality of layers of floating oxide structure are allowed to further optimize the distribution of longitudinal electric fields in the drain region, thereby increasing the entire breakdown voltage of the transistor.

The invention discloses a groove-gate type gate-drain composite field plate transistor with high electron mobility. The transistor comprises, from bottom to top, a substrate (1), a transition layer (2), a barrier layer (3), a source electrode (4), a drain electrode (5), a groove gate (7), a passivation layer (8), a gate field plate (9), a drain field plate (11) and a protection layer (12); the drain field plate (11) is electrically connected with the drain electrode (5), the groove gate (7) is electrically connected with the gate field plate (9), wherein, a groove (6) is opened on the barrier layer (3); and n floating field plates (10) are deposited on the passivation layer arranged between the gate field plate and the drain field plate. All the floating field plates have the same size and are in a floating state, and the floating field plates are equidistantly distributed between the gate field plate and the drain field plate. The n floating plates, the gate field plate and the drain plate are completed on the passivation layer by one-time process. The transistor has the advantages of simple process, good reliability and high breakdown voltage, and can be used for fabricating high power devices based on a wide band gap compound semiconductor material heterojunction.