24results about How to "Improve breakdown voltage" patented technology

The application provides a detector pixel structure and an electronic detector. The detector pixel structure comprises a semiconductor substrate, a first and a second conductive type heavily doped layer, an insulating layer, an upper electrode, a lower electrode, an electron channel hole electrode, a metal protection ring and a doped ring; the doped ring is located in the semiconductor substrate and outside the first conductive type heavily doped layer and is exposed on the first surface of the semiconductor substrate; the insulating layer extends from the surface of a non-detection area to the surface of the semiconductor substrate, and the upper electrode extends from the surface of the non-detection area to the surface of the insulating layer; the electron channel hole electrode is located on the sidewall of the semiconductor substrate and is electrically connected to the lower electrode at one end and extends to the side surface of the insulating layer at the other end; and the metal protection ring is located on the surface of the semiconductor substrate and outside the upper electrode. The application can effectively avoid the image distortion caused by the deviation of the electron beam propagation direction, reduce the leakage current of the detector, improve the breakdown voltage and thus improve the detection performance.

This application relates to the field of electrophoretic coating technology, and discloses a low-temperature curing epoxy cathodic electrophoretic coating and its preparation method. The low-temperature curing epoxy cathodic electrophoretic coating comprises 40-60 parts of cationic epoxy main resin, 10-25 parts of low-temperature blocked isocyanate curing agent, 15-30 parts of pigment and filler paste, 0.5-3 parts of neutralizing agent, 20-40 parts of deionized water, and 0.2-2 parts of additives; the cationic epoxy main resin is an amine-modified bisphenol A type epoxy resin with a number average molecular weight of 2500-5000; the unblocking temperature of the low-temperature blocked isocyanate curing agent is 90-120℃. The preparation method includes a first neutralization, pre-emulsion formation, pre-emulsion maturation, a second neutralization, and a second dispersion step. The low-temperature curing epoxy cathodic electrophoretic coating of this application has good dispersion and stability, and can form a continuous coating film.

This invention provides a field-effect transistor (FET), its fabrication method, and a power device thereof. The FET includes a substrate, a functional body, a gate dielectric, and a gate. The functional body includes a drift epitaxial region, a channel region, a source region, a first shielding region, and a second shielding region. Multiple gate trenches with their openings located on the surface away from the substrate are formed within the functional body. Each gate trench contains a gate and a gate dielectric. The channel region contacts the gate dielectric in one of the gate trenches and has a channel. The first shielding region is located between the channel region and another gate trench, and it contacts the gate dielectric in the other gate trench. The second shielding region is located below the gate trench and is connected to the first shielding region. The first and second shielding regions can significantly reduce the on-resistance of the device and increase its breakdown voltage.

This invention discloses a semiconductor device and a method for forming the same, wherein the semiconductor device includes: a semiconductor substrate; a gate structure located on the semiconductor substrate; a source region and a drain region located in the semiconductor substrate and on opposite sides of the gate structure; a sacrificial oxide layer located on the semiconductor substrate; a contact etch stop layer located on the sacrificial oxide layer; a lower interlayer dielectric layer located on the contact etch stop layer; a high-resistivity dielectric layer located on the gate structure and the lower interlayer dielectric layer; and a high-resistivity field plate, wherein the high-resistivity field plate is at least partially located on the high-resistivity dielectric layer.

The utility model provides a kind of LDMOS device.The LDMOS device, the recess and the convex part defined by recess have on the top surface of base, drain region is located in convex part, drift region is located in the base below recess bottom surface and part is located below drain region, the side surface of drain region is located above the top surface of drift region and the top surface of drift region is connected with the bottom surface of drain region, body region is located in the base below recess bottom surface and is located on the side of drift region away from drain region, gate structure is located in recess and covers part body region and part drift region, source region is located on the side of gate structure away from drain region, in the base below recess bottom surface and is located above body region.In this way, by setting recess on the top surface of base to raise drain region, the drain curvature effect disappears, and better surface electric field reduction effect is achieved.

The utility model relates to the technical field of transistor protection, and discloses a high-voltage MOS terminal protection structure with high avalanche tolerance, which comprises a high-voltage MOS device, the high-voltage MOS device is provided with a cellular area and a terminal protection area, the cellular area is also provided with a shield grid used for reducing on-resistance and increasing breakdown voltage, and the terminal protection area is provided with a terminal protection area. The longitudinal section of the shield grid is arranged in a trapezoid shape, the field limiting rings with the gradually-decreased spacing can widen the width of a depletion region, improve the transverse voltage endurance capability of the MOS device, reduce the peak value of an edge electric field, transfer the peak point of an electric field through a slope field plate and eliminate a grid angle distortion electric field, and the shield grid reconstructs the electric field to be distributed in a trapezoid shape and optimizes a longitudinal electric field. Therefore, the breakdown voltage of the MOS device is improved, and the avalanche trigger threshold is remarkably improved; through the design of the drain buffer layer, a large amount of high-energy carrier kinetic energy can be absorbed, the channel thermal shock can be reduced, the local temperature peak value can be reduced, the two metal layers are utilized to assist heat dissipation, double-path heat conduction is realized, and the avalanche tolerance is improved.

This invention relates to a superjunction semiconductor device, comprising a first conductivity type substrate, a first conductivity type epitaxial layer, multiple layers disposed on the front side of the first conductivity type substrate, second conductivity type ions implanted into the first conductivity type epitaxial layer to form second conductivity type first pillar regions, at least two rows of second conductivity type first pillar regions, each row of second conductivity type first pillar regions connected to form second conductivity type first pillars, a first conductivity type second epitaxial layer disposed on the front side of the first conductivity type first epitaxial layer, a first trench formed on the first conductivity type second epitaxial layer, the first trench filled with a second conductivity type material to form second conductivity type second pillars, the second conductivity type second pillars and the second conductivity type first pillars being correspondingly disposed and connected to the corresponding second conductivity type first pillars. This invention has the effect of reducing uneven electric field distribution and reducing electromagnetic interference.

A semiconductor structure and a method for forming the same, wherein the semiconductor structure includes: a substrate comprising a plurality of first regions and an isolation region located between adjacent first regions; a first doped well region located within the first regions; an initial well region located within the isolation region, the initial well region having a conductivity type opposite to that of the first doped well regions, and the initial well region being in contact with the first doped well regions; and a first isolation well region located within the first doped well regions, the first isolation well region having a conductivity type opposite to that of the first doped well regions, wherein the distance from the edge of the first isolation well region to the edge of the initial well region is greater than zero and less than half the width of the initial well region, the width being the dimension of the initial well region along a direction parallel to the substrate and located between adjacent first regions. The semiconductor structure and the method for forming the same improve the electrical isolation effect of different regions in a transistor device, thereby improving device stability.

This invention discloses a composite-terminated vertical Schottky diode combining a BaTiO3 / Si3N4 dielectric field plate and ion implantation. A composite dielectric layer composed of Si3N4 and BaTiO3 layers is used, with an anode field plate disposed on the composite dielectric layer. Fluorine ions are implanted into a drift layer below the anode to form a fluorine implantation region. Part of the fluorine implantation region is located below the anode, and another part is located below the composite dielectric layer, forming a composite termination. This composite termination structure effectively modulates the electric field distribution on the device surface and within the device bulk, ultimately effectively reducing the electric field strength at the anode edge and achieving a higher breakdown voltage. This provides an effective solution for the termination design of high-performance high-voltage Schottky diode power devices.

The utility model provides a kind of ultrahigh pressure MOSFET terminal structure, above-mentioned terminal structure includes: substrate, it is in and set up main knot and VLD knot, the depth of the VLD knot gradually becomes smaller along the direction away from the main knot;Oxide layer is located on the substrate;Polysilicon field plate is located on the oxide layer;Dielectric layer is located on the polysilicon field plate;And metal field plate is located on the dielectric layer.The utility model embodiment is changed by setting VLD knot and its depth, and is matched with polysilicon field plate and metal field plate, while guaranteeing high pressure resistance, so that terminal structure is shorter, cost is less, and reliability is higher.

The application discloses a high-mobility silicon carbide N-type LDMOS device with reduced on-resistance, which comprises an N-type substrate, a P-type epitaxial layer arranged on the N-type substrate, an N-type well region, a first P-type heavily doped region, a first N-type heavily doped region, a second P-type heavily doped region connected to a source, a second N-type heavily doped region connected to a drain arranged in the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region and the second P-type heavily doped region being connected, an oxide layer arranged on the surface of the second N-type heavily doped region, the N-type well region, the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region and the P-type epitaxial layer, a polycrystalline silicon trench gate serving as a gate of the device and extending into the P-type epitaxial layer, and an N-type buried layer arranged in the P-type epitaxial layer, one end of the N-type buried layer being connected to a channel of the device and the other end being connected to the N-type well region.

The application provides a vertical floating and resistive field plate terminal silicon carbide IGBT device and a preparation method, a vertical groove type metal-insulator-semiconductor (MIS) structure is introduced in a cell terminal area, a multi-region junction terminal expansion / multi-floating field limiting ring / half-insulating polysilicon SIPOS resistance field plate technology is combined, and a high-efficiency super-high-voltage silicon carbide IGBT device terminal is realized: in a blocking state, the resistance field plate performs lateral voltage division, the groove type MIS structure keeps the same potential with the half-insulating polysilicon connected with the resistance field plate, the device front Ptop multi-region junction terminal expansion and Pshield multi-floating field limiting ring structure are combined to modulate the body and surface electric field, the terminal area is continuously and fully depleted, the main junction electric field concentration is relieved, and the area occupied by the terminal area is reduced. Under the premise of ensuring the high-efficiency terminal of the groove type silicon carbide IGBT device, the high breakdown voltage and the reliability of the oxide layer are maintained.

The application belongs to the technical field of semiconductor manufacturing, and provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, an epitaxial layer, a shielding gate, a gate, a body region, an injection region and a deep buried layer. The epitaxial layer is located on the front surface of the substrate. A plurality of grooves are arranged in the epitaxial layer. The shielding gate and the gate are arranged at intervals and located in the grooves. The body region is located on the side of the epitaxial layer away from the substrate. The injection region is located on the side of the body region away from the epitaxial layer. The deep buried layer is located in the epitaxial layer and on the opposite sides of the grooves along a first direction. By introducing the deep buried layer, a depleted electric field shielding layer can be formed on both sides below the grooves, thereby avoiding the concentration of the electric field in the weak areas such as the bottom of the grooves, reducing the high peak electric field around the shielding gate, making the electric field distribution in the device more uniform, and improving the breakdown voltage of the device.

The invention discloses a gallium oxide nonlinear photoconductive switch device with high electric field tolerance, which comprises a substrate, one side of the upper surface of the substrate is provided with a groove or a table board with an inverted trapezoidal section, and the other side of the lower surface of the substrate is provided with a groove or a table board with a trapezoidal section. The section of the groove or the table top on the lower surface of the substrate is congruently symmetrical with the section of the groove or the table top on the upper surface, a front passivation layer is deposited on the outer side of the groove or the table top above the upper surface of the substrate, and a back passivation layer is arranged on the substrate on the outer side of the groove or the table top on the lower surface of the substrate. The invention also discloses a manufacturing method of the gallium oxide nonlinear photoconductive switch device with high electric field tolerance. The problems that in the prior art, a Ga2O3 photoconductive switch device is concentrated in electric field, low in peak voltage and incapable of working in a nonlinear mode are solved.

This invention relates to an enhancement-mode GaN HEMT device based on RESURF electric field modulation, belonging to the field of semiconductor power device technology. The invention aims to solve the technical problem of limited breakdown voltage caused by concentrated electric field at the gate edge in traditional enhancement-mode GaN HEMTs. The main technical solution involves introducing a p-type doped region within the AlGaN barrier layer of the device, located between the gate and drain. This structure utilizes the RESURF effect to effectively modulate and homogenize the electric field distribution in the gate-drain drift region when the device is off, thereby significantly improving the breakdown voltage of the device and optimizing the power factor while maintaining good switching characteristics.

This invention provides a high-voltage enhancement-mode HEMT device that suppresses current collapse, comprising a substrate, a GaN layer, and an Al layer. x Ga 1‑x N layer, Al x Ga 1‑x From left to right, the N-layer consists of a source, a P-GaN gate, a P-GaN hole injection structure, and a drain. A high-resistivity capping layer covers the P-GaN gate, gate metal, P-GaN hole injection structure, the upper surface of the drain, and the Al layer between the P-GaN gate source side and the drain. x Ga 1‑x In the upper surface region of the N-layer, the hole injection structure in this invention can be sufficiently close to the gate, allowing for more complete surface trap recombination. Simultaneously, it avoids long-distance surface charge transport, resulting in faster surface charge transfer and improved surface trap recombination efficiency, achieving the optimal hole injection effect. This invention suppresses current collapse without shortening the device drift region, thus avoiding a decrease in device breakdown voltage.

The application provides an epsilon phase gallium oxide based material and a crystal student growth method and use thereof, the crystal student growth method comprising epitaxial growth of the epsilon phase gallium oxide based material on a substrate with a polar surface, so that the epsilon phase gallium oxide based material has the same polarization direction as the polar surface. The application selects a substrate with a specific surface polarity and controls the growth of high-quality crystals through substrate and template engineering, thereby guiding controllable polarity growth by using the specific substrate as a template. Thus, active regulation of the polarization direction of the epsilon phase gallium oxide based material can be supported, the bottleneck of single polarization characteristics of the material system is broken, a key material foundation for developing a new generation of high-performance functional devices based on polarization engineering is laid, and the application has important scientific and application values.

The application relates to a high-voltage BJT device applying a SiC BCD process and a preparation method thereof, and the high-voltage BJT device comprises a drift region, a collector region extending from the surface of the drift region to the inside of the drift region, a collector electrode located on the collector region, a current guide layer located on the drift region and spaced apart from the collector region, a JTE-GR terminal junction extending from the surface of the drift region to the inside of the drift region and located between the collector region and the current guide layer, a base region located on the current guide layer, a base region ohmic contact region extending from the surface of the base region to the inside of the base region, a base electrode located on the base region ohmic contact region, an emitter region located on the base region and spaced apart from the base region ohmic contact region, an emitter electrode located on the emitter region, and the base electrode is located between the emitter electrode and the collector electrode. The embodiment of the application combines the advantages of the JTE terminal and the GR terminal, so that the terminal junction can bear higher blocking voltage, and the sensitivity of the terminal junction to the concentration is reduced.

This invention provides a high-voltage device and its fabrication method. The method involves providing a pre-etched photomask before the active region photomask, forming a high-voltage gate trench and an adjustment trench in a substrate based on the pre-etched photomask, and then forming first isolation trenches on both sides of the high-voltage gate trench based on the active region photomask. The presence of the high-voltage gate trench improves the initial height of the active region in the area where the high-voltage gate dielectric layer is located, thereby controlling the step height of subsequent high-voltage gate dielectric layers, reducing step height differences between different devices, and thus reducing the load on subsequent processes. Furthermore, the presence of the adjustment trench increases the depth of the final isolation trench, thereby increasing the electron transport path of the high-voltage device and improving its breakdown voltage. In addition, the fabrication method of this invention also helps to optimize the corner rounding of the high-voltage active region. In summary, the fabrication method of this invention is simple, controllable, and effective, and the resulting high-voltage device has better performance.

The application discloses an LDMOS device and a manufacturing method thereof. The LDMOS device comprises a substrate and an epitaxial layer, an active region arranged on the epitaxial layer, the active region comprising a source region, a gate region and a drain region, a drain drift region and a high-concentration ion implantation region arranged in the drain region, an ohmic contact metal layer arranged on the surface of the epitaxial layer in the high-concentration ion implantation region, the ohmic contact metal layer connected with an upper metal layer through a via, and a drain field plate arranged on the surface of the epitaxial layer in the drain drift region. The drain field plate is arranged on the surface of the epitaxial layer in the drain drift region, and the length of the drain field plate does not need to be long to have a good electric field suppression effect, and the increase of a source-drain parasitic capacitance is avoided.

The application relates to an AlGaN / GaN vertical high electron mobility transistor and a manufacturing method thereof; solves the problem that when the field plate technology is applied to a device with a vertical drift region, the vertical drift region is easily affected by charge imbalance, thereby affecting the on-current; comprises a substrate of a GaN material; an N-type drift region, a GaN channel layer and an AlGaN barrier layer are sequentially grown above the substrate; a source region is formed on the upper surface of the AlGaN barrier layer, and a source electrode is arranged in the source region; the same number of P-type floating buried layers are formed on the left and right sides of the N-type drift region, and a P-type blocking layer is formed on the upper portion of the N-type drift region; a multilayer stepped dielectric groove is formed by etching through the middle portions of the N-type drift region, the P-type blocking layer, the GaN channel layer and the AlGaN barrier layer; a multilayer stepped oxide layer is arranged on the inner wall of each side of the dielectric groove; an SIPOS field plate is deposited between the oxide layers on the two sides; polycrystalline silicon is deposited above the SIPOS field plate; a gate electrode and a passivation layer are arranged above the polycrystalline silicon; and the two source electrodes are connected in common.

This invention provides a method for manufacturing a semiconductor device. Before the active region manufacturing process, trench etching is performed on the substrate region to be fabricated as a high-voltage transistor to form at least a first depth adjustment trench located outside the gate oxide region of the high-voltage transistor. A first drift region is then formed by ion implantation. This solves the problem of incomplete corner implantation caused by the rounded exposure of photoresist corners in existing LDD processes. Furthermore, the depth of the first depth adjustment trench increases the bottom depth of the shallow trench isolation structure used to isolate the source / drain regions and channel regions of the high-voltage transistor, increasing the charge path of the high-voltage transistor and its breakdown voltage. Further, by simultaneously forming a gate oxide trench for fabricating a thick gate oxide layer with the first depth adjustment trench, the step height between the high-voltage transistor and other components is reduced, thereby reducing the load effect and defects in subsequent processes and improving the performance of the high-voltage transistor.

The application discloses a high-voltage MOS device, and relates to the technical field of semiconductors, comprising a substrate layer, a first epitaxial layer is stacked on the top of the substrate layer, a second epitaxial layer is stacked on the top of the first epitaxial layer, a gate metal is arranged on the second epitaxial layer, the gate metal is wrapped with a contact metal layer outside, the contact metal layer comprises a contact section in contact with the second epitaxial layer, a source metal is arranged on the top of the contact section, and a drain metal is arranged on the bottom of the substrate layer; wherein a first insulating silicon section is arranged between the first epitaxial layer and the substrate layer and located on the left side, a second insulating silicon section is arranged between the first epitaxial layer and the substrate layer and located on the right side, and a gap section is formed between the first insulating silicon section and the second insulating silicon section; a third insulating silicon section is arranged between the second epitaxial layer and the first epitaxial layer and opposite to the gap section; and a testing method of the high-voltage MOS device is also disclosed. The application has the advantages of safety and stability, high reliability and strong anti-single-particle radiation capacity.

The application discloses a kind of conformal heat-conducting insulating composite material and its preparation method and application method, it is related to semiconductor packaging and thermal management technical field.The composite material includes: organic polysilazane resin 40-60 parts, toughening agent 4-10 parts, crosslinking agent 0.1-3 parts, low dielectric heat-conducting filler 35-85 parts, heat-conducting filler dispersant 0.3-2 parts, low volume shrinkage modifier 5-10 parts, catalyst 0.1-1 part, polymerization inhibitor 0.01-0.06 parts, solvent 5-90 parts;Wherein low dielectric heat-conducting filler is hexagonal boron nitride nanosheet, spherical silicon powder and the complex of undefined aluminum nitride, low volume shrinkage modifier is cage-type silsesquioxane.The composite material of the application can perfectly fill micron chip gap, volume shrinkage rate is low after solidification, interface thermal resistance is small, has excellent temperature resistance and high insulation, can satisfy the requirement of high-end equipment manufacturing field such as aerospace, high-performance computing to thermal management material.