431results about How to "Improve breakdown voltage" patented technology

The invention discloses a cellular structure of a shield gate trench MOSFET and a manufacturing method thereof, the cellular structure of the shield gate trench MOSFET comprises a substrate, a drift region and an interlayer dielectric layer, the drift region is provided with a deep trench, and the deep trench is internally provided with a shield gate, an intermediate oxide layer and a control gate; a body region and a source region are formed at the upper part of the drift region through injection, the interlayer dielectric is provided with a source electrode contact hole which penetrates through the source region and extends into the body region, and highly doped contact regions are formed on the side wall and the bottom of the source electrode contact hole through injection; and a charge balance region is formed below the source electrode contact hole through high-energy ion implantation. According to the invention, by arranging the charge balance region, the lateral depletion of the shield gate to the adjacent drift region can be enhanced when the shield gate trench MOSFET device is in a reverse bias state, the specific on-resistance of the device is reduced, the depletion of the drift region of the epitaxial layer is accelerated, and the reliability and radiation resistance of the device are improved.

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the following steps: providing a substrate which comprises a base layer and a spacer layer located on the base layer, and is divided into a first region for forming a BCD device and a second region for forming an SGT device, a BCD structure is arranged in the substrate layer of the first area, and a first SGT structure and a second SGT structure which are spaced from each other are arranged in the substrate layer of the second area; forming a patterned photoresist layer on the first SGT structure in the second region and the spacer layer above the BCD structure in the first region, and etching the spacer layer to expose a part of the substrate layer and the second SGT structure; and forming a control gate on the spacer layer above a part of the BCD structure and extending to a part of the exposed substrate layer, wherein the control gate is also formed on the exposed second SGT structure. On the basis of not increasing a photomask and a process, the breakdown voltage can be increased, and the electrical performance of the device is improved.

The invention discloses a silicon carbide step groove MOSFET and a manufacturing method thereof. The MOSFET comprises a semiconductor drain region, a semiconductor drift region, a second conductive type semiconductor well region, a first conductive type semiconductor source region, a second conductive type semiconductor contact region, a first groove, a first conductive type carrier diffusion layer, a second groove, a second conductive type semiconductor shielding region, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a contact hole. And a source end metal electrode and a drain end metal electrode. A first conductive type semiconductor carrier diffusion layer (CSL) is prepared in a local region of the bottom and the side wall of a first groove, so that the specific on-resistance (Ron, sp) of the device is reduced; second conductive type semiconductor shielding regions short-circuited with the source end metal electrode are prepared in all regions of the bottom and the side wall of the second groove, so that the gate-oxide electric field can be remarkably reduced compared with a shielding region introduced only at the bottom of the groove, and the reliability of the device is improved.

The invention provides an electric field enhancement type shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises a substrate, an epitaxial layer formed on the substrate, a gate trench formed on a cellular region on the epitaxial layer, and a first gate dielectric layer formed at the bottom of the gate trench and a first polycrystalline silicon layer located in the first gate dielectric layer, a P-type epitaxial layer is formed on the first gate dielectric layer and the first polycrystalline silicon layer, and an isolation dielectric layer is formed on the P-type epitaxial layer; a second gate dielectric layer is formed on the side wall of the residual gate trench, and a second polycrystalline silicon layer is formed in the residual gate trench; a well region and a source region of a cellular region are formed on the epitaxial layer, and a contact hole dielectric layer is formed on the epitaxial layer; and contact holes communicated with the well region are formed on the contact hole dielectric layer and the epitaxial layer below the contact hole dielectric layer. By adding the shield grid P-type epitaxial layer, the electric field intensity in the middle of the drift region is effectively improved, the breakdown voltage is improved, and meanwhile, the conduction loss can be further reduced by adjusting epitaxy.

The invention discloses a homogeneous pn junction terminal gallium oxide Schottky barrier diode and a preparation method thereof. The problems that gallium oxide p-type doping is difficult, and heterojunction electric leakage is high and voltage resistance is low are solved. The semiconductor device comprises a cathode, an n-Ga2O3 substrate and an n-Ga2O3 epitaxial layer from bottom to top, ion implantation regions are arranged at the left end and the right end of the upper surface of the n-Ga2O3 epitaxial layer, and the upper surface of the n-Ga2O3 epitaxial layer is covered with an anode; the ion implantation region is subjected to annealing treatment to form a p-type Ga2O3 region, and the p-type Ga2O3 region and the n-Ga2O3 epitaxial layer form a homogeneous pn junction terminal, so that the gallium oxide Schottky barrier diode with high voltage resistance and low electric leakage is realized. The preparation method comprises the steps of cleaning an epitaxial wafer, photoetching to form a region to be implanted with ions, carrying out ion implantation, cleaning, carrying out rapid thermal annealing to form p-Ga2O3, and preparing a cathode and an anode. According to the invention, N / P ions are injected, annealing treatment is carried out, a gallium-oxygen-nitrogen-phosphorus compound with a p-type characteristic is generated in the n-Ga2O3 epitaxial layer, and the homogeneous pn junction terminal gallium oxide Schottky barrier diode is realized. The method can be used in high-voltage and high-power fields such as power grids and high-speed rails

The invention discloses a gallium oxide-based MOSFET device and a preparation method thereof, and relates to the field of semiconductor devices. The device has the characteristics of high voltage resistance and low electric leakage, and comprises a conductive region and an edge terminal region connected with the conductive region, the conductive region comprises a first drain metal layer, a first gallium oxide substrate, a first gallium oxide epitaxial layer, a gallium oxide current barrier layer and a highly-doped gallium oxide N + region which are sequentially stacked from bottom to top, and a groove which is positioned on the surface of the highly-doped gallium oxide N + region and of which the bottom is propped against the first gallium oxide epitaxial layer; the conductive region further comprises a first p-type semiconductor buried layer located at the bottom and on the side wall of the groove, a gate dielectric layer located on the surface of the first p-type semiconductor buried layer, the side wall of the groove and the surface of the highly-doped gallium oxide N + region, and a gate metal layer located on the surface of the gate dielectric layer. The first interlayer dielectric layer covers the surface and the side face of the gate metal layer and the side face of the gate dielectric layer, and the source metal layer is located on the surface of the first interlayer dielectric layer and the surface of the highly-doped gallium oxide N + region.

The invention relates to a semiconductor device and a preparation method thereof. The semiconductor device comprises a semiconductor material layer; the first groove is located in the semiconductor material layer, the side wall and the bottom wall of the first groove are connected through an arc angle, and the included angle between the plane where the side wall is located and the plane where the bottom wall is located is an obtuse angle; the drain region is located in the semiconductor material layer on the periphery of the first groove, and the depth of the drain region is smaller than that of the first groove; the well region is located in the semiconductor material layer below the bottom wall; the field oxide layer extends on the part, between the well region and the drain region, of the bottom wall and the side wall; the gate dielectric layer is connected with the field oxide layer and covers part of the well region; the field plate is located on the field oxide layer; the grid electrode is located on the grid electrode dielectric layer; the source region is positioned on the surface layer of the well region; a current conduction path of the semiconductor device comprises a first current conduction path which is located in the semiconductor material layer and extends close to the bottom wall and a second current conduction path which extends close to the side wall. Therefore, the on-resistance of the device is reduced, and the voltage-resistant performance of the device is ensured at the same time.

The invention provides a high-voltage NLDMOS (N-type laterally diffused metal oxide semiconductor) structure which comprises a P-type substrate, and an N-type injection region is formed in a region, close to a drain end, of the substrate; an N-type epitaxial layer is formed on the substrate, and a field oxide layer is formed on a field oxide region of the epitaxial layer; a P well is formed on the epitaxial layer, and a P-type doped layer close to the upper surface of the epitaxial layer is formed on the epitaxial layer below the source end and the field oxide layer; the gate structure comprises a gate dielectric layer and a gate polycrystalline silicon layer, one end of the gate polycrystalline silicon layer extends to the P well, the other end of the gate polycrystalline silicon layer extends to the adjacent field oxide layer, and the drain polycrystalline silicon field plate is located on the field oxide layer close to the drain end; an N-type source end heavily doped region, an N-type drain end heavily doped region and a P-type heavily doped P well lead-out region; the interlayer dielectric layer is located between the source end and the drain end, and a contact piece used for leading out the drain end polycrystalline silicon field plate is formed on the interlayer dielectric layer. The breakdown voltage of the device is improved.

The invention discloses a gallium oxide Schottky diode with a passivated two-dimensional semimetal insertion layer and a preparation method thereof, and the gallium oxide Schottky diode comprises a substrate which is made of N-type heavily doped beta-Ga2O3 with different crystal orientations; the epitaxial layer is located on the substrate; wherein the material of the epitaxial layer is N-type unintentionally doped beta-Ga2O3; the two-dimensional semimetal growth insertion layer is located on the epitaxial layer; the protection layer is located on the two-dimensional semimetal growth insertion layer, and the orthographic projection of the protection layer and the orthographic projection of the two-dimensional semimetal growth insertion layer are overlapped in the direction perpendicular to the substrate; the terminal structure is located on the epitaxial layer, the terminal structure is of an annular structure, and the terminal structure is arranged around the two-dimensional semimetal growth insertion layer and the protection layer; the anode covers the protective layer and a part of the terminal structure; and the cathode is positioned on one side, deviating from the epitaxial layer, of the substrate. According to the beta-Ga2O3-based SBD device provided by the invention, the two-dimensional material can adjust the energy band of the Ga2O3 surface by virtue of the inherent Van der Waals surface, and endow the Schottky barrier with extremely strong flexibility.

The invention belongs to the technical field of insulation heat dissipation coatings, and particularly relates to a magnesium alloy high-pressure-resistance surface treatment liquid and a preparation method thereof. The coating comprises the following raw materials in parts by weight: 30-40 parts of organic silicon modified waterborne epoxy resin, 9-12 parts of modified hexagonal boron nitride, 10-15 parts of modified graphene, 2-4 parts of a curing agent, 0.5-2 parts of a flatting agent, 1-2 parts of a defoaming agent and 25-50 parts of acetone. A coating formed on the surface of a magnesium alloy base material through the magnesium alloy high-pressure-resistance surface treatment liquid has high volume resistance, high breakdown voltage resistance, high corrosion resistance and high heat conductivity coefficient, and the magnesium alloy high-pressure-resistance surface treatment liquid can be applied to the field of new energy and can also be applied to the fields of aerospace, 3C electronics and the like. And the market prospect is wide.

The invention belongs to the technical field of semiconductors, and particularly relates to an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a method for manufacturing the MOSFET structure. The structure comprises a substrate; the drift region is positioned on the upper surface of the substrate and consists of a single-layer or multi-layer epitaxial layer; the drift region is provided with a plurality of first groove structures located in the active region and a plurality of second groove structures located in the terminal region, and the side walls of the second groove structures are zigzag; the first bottom oxidation layer is located in the first groove structure, and the second bottom oxidation layer is located in the second groove structure; the first bottom oxide layer and the second bottom oxide layer are of groove structures, and the thickness of the first bottom oxide layer is smaller than that of the second bottom oxide layer. The zigzag side wall is formed when the second groove structure is etched, so that the thickness of the second bottom oxide layer can be increased while the first bottom oxide layer is not increased, the withstand voltage of the terminal structure is ensured, the very small primitive cell unit size and the lower on-resistance are obtained, and the source-drain breakdown voltage is improved.

The invention discloses a deep trench isolation structure and a manufacturing process method thereof, an injection layer of a second conduction type is arranged on a substrate of a first conduction type, and a deep trap of the second conduction type is arranged on the injection layer; the surface layer of the deep well is provided with a shallow trench isolation structure, and the outer side of the shallow trench isolation structure is provided with a well region of a second conductive type; a deep trench is formed in the shallow trench isolation structure through etching; filling materials which are filled in sections are arranged in the deep grooves; wherein the lower part in the deep trench is filled with a silicon oxide material, and the upper part in the deep trench is filled with a polycrystalline silicon material; filling in the deep trench is divided into two sections of composite filling made of different materials, the portion located on the lower portion of the deep trench is made of silicon oxide, the portion located on the upper middle portion of the deep trench is made of polycrystalline silicon, the structure is further optimized, the bottom of DTI polycrystalline silicon is shortened to the position below an injection layer, the bottom of the DTI polycrystalline silicon can pull up a high peak electric field in a depletion region, and therefore the reliability of the deep trench is improved. And the breakdown voltage of the device is improved.

The invention discloses a manufacturing method of a stator bar of a main insulation structure with a circular inner part and a square outer part, and is suitable for the field of large-scale generator manufacturing. The stator bar is composed of a circular lead formed by twisting and transposing circular strands and a main insulator with a circular inner part and a square outer part, and a more-glue mould pressing or less-glue VPI manufacturing process is adopted. The stator bar with the main insulation structure with the round inside and the square outside has the advantages of clear principle, novel structure, convenient process and easiness in design and manufacture. The lead wire adopts a circular structure, so that the main insulation internal electric field of the stator bar can be greatly reduced, and the electrical performance and the breakdown voltage level of the stator bar are improved. The exterior of the main insulator adopts a square structure, so that the design consistency of the generator and the convenience of process wire embedding can be ensured. The stator bar with the round outside and the square inside can remarkably improve the rated voltage level of a large generator, and has great application prospects and remarkable economic and social benefits.

The invention discloses a room-temperature curing water-based ultrahigh-pressure insulating coating for electronics. The coating is formed by curing a water-based ultrahigh-pressure insulating paint at room temperature, the water-based ultrahigh-pressure insulating paint is prepared from a component A and a component B, wherein the component A comprises waterborne polyurethane resin, a curing agent, polyether-ether-ketone ultrafine powder, an insulating nano material and water; the component B comprises a dispersing agent, a foam inhibitor, a flatting agent, a wetting agent, a coalescing agent and a thickening agent. According to the invention, the added insulating nano material can improve the electrical insulation characteristic of the coating, so that the coating has a high insulating effect, is not easy to break down and has extremely high safety when being applied to electronic equipment, and the insulating nano material forms a network-shaped skeleton structure through mutual crosslinking in the coating, so that the structure of the coating can be supported and stabilized, and the service life of the coating is prolonged. The coating is not easy to damage, so that the stability of the coating is good, and the ultrahigh-voltage insulation effect can be kept for a long time.

The invention discloses a gallium nitride heterojunction material structure and a growth method thereof, and relates to the technical field of semiconductor single crystal films, the material structure comprises a SiC substrate, an AlN nucleating layer, an AlGaN buffer layer, a GaN channel layer, an AlN insertion layer, a gradient component AlGaN barrier layer and a GaN cap layer from bottom to top; the material is prepared on a substrate in an epitaxial mode through a metal organic matter chemical vapor deposition method. AlGaN with gradually-changed Al components is adopted as the barrier layer, so that the electric field intensity of the barrier is reduced, the voltage endurance capability of the device is improved, and the power density and the reliability of the device are improved.

The invention discloses a silicon carbide step groove MOSFET and a manufacturing method thereof. Comprising a semiconductor drain region, a semiconductor drift region, a second conductive type semiconductor well region, a first conductive type semiconductor source region, a second conductive type semiconductor body contact region, a first conductive type carrier diffusion layer, a first groove, a second conductive type semiconductor shielding region, a second groove, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a contact hole, a source end metal electrode and a drain end metal electrode; according to the invention, the first conductive type semiconductor carrier diffusion layer is prepared at the bottom of the semiconductor well region, so that the specific on-resistance of the device is reduced; second conductive type semiconductor shielding regions which are in short circuit connection with the source end metal electrode are prepared in all regions of the bottom and the side wall of the first groove, and the gate-oxide electric field can be remarkably reduced compared with a shielding region introduced only at the bottom of the groove, so that the reliability of the device is improved; according to the invention, the static and dynamic electrical performance parameters of the device are optimized, and the reliability of the device is also optimized.

The invention discloses a double-gate enhanced gallium nitride radio frequency power transistor, which relates to the field of transistors and comprises a substrate, a buffer layer, a GaN channel layer and an AlGaN barrier layer which are sequentially stacked, a p-GaN cap layer is arranged on the upper surface of the AlGaN barrier layer; a direct current grid electrode is arranged on the upper surface of the p-GaN cap layer; two ends of the upper surface of the AlGaN barrier layer are respectively provided with a source electrode and a drain electrode; a radio frequency grid electrode is arranged on the upper surface of the AlGaN barrier layer and located between the source electrode and the p-GaN cap layer. The transistor structure designed by the invention relates to the double-gate combination of the radio frequency gate and the direct current gate, so that the transistor device can simultaneously obtain a plurality of excellent electrical characteristics such as high cut-off frequency, positive threshold voltage, large breakdown voltage and low switch ratio.

The invention relates to the technical field of glass fiber sleeves, and discloses a preparation method of a high-temperature-resistant silicon resin glass fiber sleeve which comprises vinyl silicone oil, vinyl silicon-containing polyimide, hydrogen-containing silicone oil, a tackifier and a platinum water catalyst. The high-temperature-resistant silicon resin coating is formed on the surface of the glass fiber sleeve, the vinyl silicon-containing polyimide contains a siloxane structure and has good compatibility with a vinyl silicone oil matrix, the phase separation phenomenon between the vinyl silicon-containing polyimide and the vinyl silicone oil matrix is improved, and the coating does not crack after high-temperature heat treatment. In the vulcanization process, hydrogen-containing silicone oil can be subjected to a hydrosilylation reaction with vinyl silicone oil and alkenyl of vinyl silicon-containing polyimide, so that the heat resistance of a coating is improved, the crosslinking degree and molecular chain acting force of a silicon resin molecular chain are improved, the breakdown voltage is favorably improved, and better voltage resistance is shown.

The utility model provides a high-reliability SIC-MOSFET terminal structure, belonging to the technical field of semiconductor devices, the high-reliability SIC-MOSFET terminal structure comprises a source electrode and a drain electrode, the source electrode is the input end of an MOSFET and is used for current in a circuit to enter, and the drain electrode is the output end of the MOSFET and is used for exporting current; a groove and a grating are arranged between the source electrode and the drain electrode, the structure among the source electrode, the drain electrode, the groove and the grating is a FinFET structure, the source electrode and the drain electrode are fixedly connected through the middle groove and the grating, the groove is fixedly connected with the grating, the groove comprises a first groove and a second groove, and the first groove and the second groove are communicated with each other. The first groove is fixedly connected with the source electrode. The problem that an existing SIC-MOSFET0 is prone to being broken down under the conditions of high voltage and high current can be solved.

The invention discloses a side shield grid optimized vertical power field effect transistor with a super junction structure, which comprises an N + type substrate as a drain electrode, an N type epitaxial layer grown on the N + type substrate, and a drift region generated on the N type epitaxial layer. The top of the drift region is provided with a P-type channel region, an N + type doped source region and a P + region. And the grid is arranged between the P-type channel region and the N + type source region and is separated by a grid oxide layer. The super junction structure is embedded in the drift region below the gate. Shield gates are symmetrically arranged on two sides of the device and wrapped in shield gate oxide layers, and high-K dielectric cylinders are filled below the shield gates. Compared with a common shield grid vertical power device, the shield grid is separated into the shield grids on the two sides, the drift region is transversely assisted to be depleted, vertical depletion of the drift region is weakened, and therefore on resistance is optimized. The super junction structure is embedded in the drift region, the electric field distribution of the drift region is optimized, and the fixed relation between the on-resistance and the breakdown voltage is changed, so that the on-resistance and the breakdown voltage are better balanced.

The invention discloses a reflecting device, a reflecting device manufacturing method and a vehicle. The reflecting device comprises a first transparent substrate, a transparent conductive layer, a second transparent substrate, a reflecting layer, a sealant and a dimming composition, the reflecting layer faces the transparent conducting layer; the dimming composition is arranged between the reflecting layer and the transparent conductive layer, the sealant is connected between the first transparent substrate and the second transparent substrate, and a cavity is defined by the sealant, the transparent conductive layer and the reflecting layer; the dimming composition is arranged in the cavity, and the sealant comprises filling particles with the dielectric constant larger than or equal to 20. The breakdown voltage of an electric field formed by the reflecting layer and the transparent conducting layer can be improved, then the electrochemical stability of the filling particles under the action of the electric field can be improved, the reflecting reliability of the reflecting device can be further improved, and the service life of the reflecting device is prolonged.

The invention discloses an additive molecule screening design method for optimizing the performance of ester-based insulating oil, and relates to the technical field of electrical insulating materials. The invention provides an additive molecule design method combined with a deep molecule generation model, aiming at solving the problems that the breakdown voltage performance is insufficient due to the fact that ester-based insulating oil is easy to generate rapid streamer under high-strength lightning impulse, and time and labor are consumed when an appropriate additive is found through an experiment. The method comprises the following steps: acquiring molecular data with target electronic attributes; taking the fragment of the molecular structure as the input of the model, and designing a new additive molecular structure by utilizing the molecular generation model; performing molecular screening according to target characteristics; and the performance of the screened molecules is verified through streamer discharge simulation. According to the method, generative design of ester-based insulating oil additive molecules is realized by using the deep autoregressive neural network, the molecular screening efficiency is remarkably improved, and a new technical route is provided for improving the breakdown voltage performance of the ester-based insulating oil.

The invention relates to the technical field of semiconductor devices, and discloses a trench gate super junction metal oxide semiconductor field effect transistor, a manufacturing method thereof and a semiconductor device. The trench gate super junction metal oxide semiconductor field effect transistor comprises an epitaxial layer; the columnar doped regions are located in the epitaxial layer at intervals and downwards extend into the epitaxial layer from the upper surface of the epitaxial layer, and the conduction type of the columnar doped regions is different from that of the epitaxial layer; the groove layer is positioned above the epitaxial layer; the first groove is positioned in the groove layer and is positioned between two adjacent columnar doped regions; the second grooves are located in the groove layer and located between every two adjacent first grooves, and the width of the second grooves is larger than that of the first grooves; and the trench gates are respectively positioned in the first trench and the second trench and extend downwards from the openings of the trenches to the bottoms of the trenches. The compromise characteristic of the on resistance and the breakdown voltage of the trench gate super junction metal oxide semiconductor field effect transistor can be improved, and the reliability of the device is improved.

The invention relates to an LDMOS device and a preparation method thereof. The LDMOS device comprises a semiconductor substrate, a first drift region, a first well region, a first source-drain region, a second source-drain region and an embedded field plate unit. The first drift region and the first well region are formed in the semiconductor substrate and adjacent to each other. The first source-drain region is disposed in the first drift region. The second source-drain region is disposed in the first well region. The embedded field plate unit comprises a first shallow trench isolation structure and a conductive layer. The first shallow trench isolation structure is arranged in the first drift region and located between the first source-drain region and the second source-drain region. The conductive layer is embedded in the first shallow trench isolation structure.

The invention relates to a gallium nitride transistor based on a polycrystalline silicon field plate and a preparation method thereof, and belongs to the technical field of semiconductor devices. The transistor comprises a substrate, a GaN buffer layer, a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer which are sequentially arranged from bottom to top, a P-GaN cap layer and a first passivation layer are arranged on the upper side of the AlGaN barrier layer, a gate metal field plate is arranged on the upper side of the P-GaN cap layer, a second passivation layer is arranged on the upper sides of the gate metal field plate and the first passivation layer, and the second passivation layer is arranged on the upper side of the second passivation layer. Two sides of the GaN buffer layer are respectively provided with source electrode metal and drain electrode metal, the first passivation layer and the second passivation layer are provided with grooves, the bottoms of the grooves penetrate through the AlGaN barrier layer, and polycrystalline silicon field plates are arranged on the upper side of the source electrode metal, the upper side of the second passivation layer and in the grooves. By introducing the polycrystalline silicon field plate, interface charges are inhibited, and the electrical performance of the device is remarkably improved.

The invention relates to a Ga2O3 / MgO / Si avalanche heterostructure and preparation thereof, and belongs to the technical field of semiconductor devices. In order to improve the epitaxial quality of a Ga2O3 film on the Si substrate, guarantee good energy band arrangement and charge transmission and improve the avalanche gain of the Ga2O3 / Si heterojunction, the invention provides a Ga2O3 / MgO / Si avalanche heterojunction design which is focused on the fact that Si and Ga2O3 are combined to form the heterojunction, and the avalanche gain of the Ga2O3 / MgO / Si avalanche heterojunction is improved. The integration level and the universality of the Ga2O3-based solar-blind ultraviolet photoelectric detector are enhanced, and avalanche gain is provided for the detector by adding the MgO barrier layer. The preparation is simple, the optical gain and the sensitivity are ideal, and Si is used as a substrate, so that the integration and the processing of a subsequent CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process are facilitated.

The embodiment of the invention provides an enhanced GaN power device, and the device comprises a substrate which comprises a channel layer and a barrier layer which form an electron gas channel; the source electrode and the drain electrode are arranged at an interval along the first direction and are electrically connected through the electron gas channel; the first depletion layer is arranged on the barrier layer and located between the source electrode and the drain electrode, the first depletion layer comprises a first depletion body and a second depletion body, the second depletion body comprises a depletion monomer, and the depletion monomer comprises a first end connected with the first depletion body and a second end spaced from the drain electrode; a non-depletable region and a depletable region which are arranged along a second direction are defined by the depletion monomer in the electron gas channel, and the second direction is intersected with the first direction; and the first grid electrode is arranged on the first depletion body and is in ohmic contact with the first depletion body. According to the embodiment of the invention, the electric field distribution of the device in the off-state drain electrode high-pressure stress can be optimized so as to improve the breakdown voltage, and the trap effect in the device can be effectively inhibited so as to optimize the dynamic resistance degradation problem of the device.

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is internally provided with a drift region; forming a gate structure, wherein the gate structure covers a part of the drift region; a first body region is formed in the substrate, a first spacer region is arranged between the first body region and the drift region, and the doping type of the first spacer region is different from that of the drift region; a first inversion region is formed in the drift region, at least one part of the first inversion region is covered by the gate structure, and the doping type of the first inversion region is different from that of the drift region; the semiconductor structure is annealed, so that the first body region is diffused to the first interval region to obtain a second body region, the second body region is adjacent to the drift region, and the doping concentration of the second body region below the gate structure is gradually reduced in the direction adjacent to the drift region; a second inversion region is obtained based on the first inversion region, at least a part of the second inversion region is covered by the gate structure, and the doping type of the second inversion region is consistent with that of the first inversion region. By adopting the technical scheme, the breakdown voltage of the semiconductor structure can be improved.

The invention provides a high-voltage gallium oxide Schottky diode under a field limiting ring terminal structure. The high-voltage gallium oxide Schottky diode comprises a cathode metal layer (1), a highly-doped N-type gallium oxide substrate (2), a lowly-doped N-type gallium oxide epitaxial layer (3) and an anode metal layer (4) which are sequentially stacked from bottom to top, the anode metal layer is connected with a main junction (5) at the top of the low-doped N-type gallium oxide epitaxial layer; a plurality of field limiting rings (6) are also arranged at the top of the low-doped N-type gallium oxide epitaxial layer; according to the gallium oxide SBD device, the process steps are simplified, effective industrial production can be achieved, the electric field crowding phenomenon of the terminal area is relieved through the device design, electric field distribution is improved, and the voltage resistance and reliability of the gallium oxide SBD device are further improved. Under the structure, the breakdown voltage of the device is greatly improved, only the characteristic on-resistance is slightly improved, and finally a high PFOM value is achieved.

The invention discloses a p-Ga2O3 / n-Ga2O3pn junction diode and a preparation method thereof, and solves the problems that gallium oxide p-type doping is difficult, and a heterojunction diode is large in leakage current and low in withstand voltage. The gallium oxide homogeneous pn junction structure comprises cathode metal, a substrate and an n-type Ga2O3 epitaxial layer from bottom to top, a p-type NiO layer is arranged above the n-type Ga2O3 epitaxial layer, a p-type Ga2O3 material layer is arranged between the n-type Ga2O3 epitaxial layer and the p-type NiO layer, and a gallium oxide homogeneous pn junction is formed. The preparation method comprises the steps of epitaxial wafer cleaning, p-type Ga2O3 material layer preparation, cathode metal preparation, photoetching, p-type NiO film deposition, photoetching and anode metal preparation. N / P ion implantation is carried out on the upper portion of the gallium oxide epitaxial layer, Ga atoms in Ga2O3 are separated out and react again through high-temperature annealing to form the effective p-type characteristic, meanwhile, the effective p-type characteristic is combined with the p-type characteristic of p-type nickel oxide, p-type doping of gallium oxide is achieved through a simple process, the gallium oxide homogeneous pn junction is obtained, reliability is high, leakage current is small, and the gallium oxide homogeneous pn junction is suitable for large-scale production. The preparation method is used for preparing the p-Ga2O3 / n-Ga2O3pn junction diode with high voltage resistance.