37results about How to "High frequency performance" patented technology

A probe assembly that acts as a temporary interconnect between terminals on a circuit member and a test station. The probe assembly can include a base layer of a dielectric material printed onto a surface of a fixture. The surface of the fixture can have a plurality of cavities. A plurality of discrete contact members can be formed in the plurality of cavities in the fixture and coupled to the base layer. A plurality of conductive traces can be printed onto an exposed surface of the base layer and electrically coupled with proximal ends of one or more of the discrete contact members. A compliant layer can be deposited over the conductive traces and the proximal ends of the contact members. A protective layer can be deposited on the compliant layer such that when the probe assembly is removed from the fixture the distal ends of the contact members contact terminals on the circuit member and the conductive traces electrically couple the circuit member to a test station. Electrical devices on the probe assembly can communicate with the test station to provide adaptive testing.

A probe assembly that acts as a temporary interconnect between terminals on an IC device and a test station. The probe assembly includes a plurality of stud bumps arranged on a first surface of a substrate in a configuration corresponding to the terminal on the IC device. The stud bumps include a shape adapted to temporarily couple with the terminals on the IC device. A plurality of conductive traces on the substrate electrically couple the stud bumps with the test station.

An integrated circuit (IC) package for an IC device, and a method of making the same. The IC package includes an interconnect assembly with at least one printed compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members. The compliant layer is positioned to bias at least the first contact members against terminals on the IC device. Packaging substantially surrounds the IC device and the interconnect assembly. The second contact members are accessible from outside the packaging.

Provided is a piezoelectric oscillator to attain high-frequency performance and frequency stabilization with the use of reflection characteristics of a reflective element. A piezoelectric oscillator is configured such that: a resonant circuit is connected to a gate of a field effect transistor; an output terminal is connected to a drain and a power supply voltage V is applied to the drain; a piezoelectric resonator is connected to a source, as a reflective element; and a resonance frequency of the resonant circuit and an oscillation frequency of the piezoelectric resonator as a reflective element are set to substantially the same frequency, and further, the piezoelectric oscillator may be configured such that a first matching circuit is provided between the resonant circuit and the gate, a second matching circuit is provided between the drain and the output terminal, and a third matching circuit is provided between the source and the reflective element.

An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.

An area array integrated circuit (IC) package for an IC device. The IC package includes a first substrate with conductive traces electrically coupled to the IC device. An interconnect assembly having a first surface is mechanically coupled to the first substrate. The interconnect assembly includes a plurality of contact members electrically coupled to the conductive traces on the first substrate. A second substrate is mechanically coupled to a second surface of the interconnect assembly so that the first substrate, the interconnect assembly, and the second substrate substantially surround the IC device. The second substrate includes conductive traces that are electrically coupled to the contact members in the interconnect assembly.

The invention relates to a deposit amount estimation device for estimating a deposit amount by calculating an amount of a deposit on an injection hole wall face of a fuel injector (22). An increment judgment of whether an actual fuel injection amount is larger than the required fuel injection amount corresponding thereto when a fuel injection command value corresponding to a required fuel injection amount smaller than a predetermined amount is given to the fuel injector, is performed, and when it is judged that the actual fuel injection amount is larger than the required fuel injection amount corresponding thereto by the increment judgment, the deposit amount is estimated on the basis of the difference between the actual fuel injection amount and the required fuel injection amount corresponding thereto.