2301 results about "Line structure" patented technology

A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer.

Combination of nanolithography and wet chemical etching including the fabrication of nanoarrays of sub-50 nm gold dots and line structures with deliberately designed approximately 12-100 nm gaps. These structures were made by initially using direct write nanolithography to pattern the etch resist, 16-mercaptohexadecanoic acid (MHA), on Au / Ti / SiOx / Si substrates and then wet chemical etching to remove the exposed gold. These are the smallest Au structures prepared by a wet chemical etching strategy. Also, Dip-Pen Nanolithography (DPN) has been used to generate resist layers on Au, Ag, and Pd that when combined with wet chemical etching can lead to nanostructures with deliberately designed shapes and sizes. Monolayers of mercaptohexadecanoic acid (MHA) or octadecanethiol (ODT), patterned by DPN, were explored as etch resists. They work comparably well on Au and Ag, but ODT is the superior material for Pd. MHA seems to attract the FeCl3 etchant and results in nonuniform etching of the underlying Pd substrate. Dots, lines, triangles and circles, ranging in size from sub-100 to several hundred nm have been fabricated on these substrates. These results show how one can use DPN as an alternative to more complex and costly procedures like electron beam lithography to generate nanostructures from inorganic materials.

A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

Provided are a three-dimensional semiconductor device and a method of operating the same. The three-dimensional semiconductor device includes: a plurality of word line structures on a substrate; active semiconductor patterns between the plurality of word line structures; and information storage elements between the plurality of word line structures and the active semiconductor patterns. Each of the plurality of word line structures includes a plurality of word lines spaced apart from each other and stacked, and the active semiconductor patterns include electrode regions and channel regions, the electrode regions and the channel regions having different conductive types and being alternately arranged.

A ferromagnetic thin-film based digital memory having a substrate supporting bit structures that are electrically interconnected with information storage and retrieval circuitry and having magnetic material films in which a characteristic magnetic property is substantially maintained below an associated critical temperature above which such magnetic property is not maintained separated by at least one layer of a nonmagnetic material with each bit structure having an interconnection structure providing electrical contact thereto at a contact surface thereof substantially parallel to the intermediate layer positioned between the first contact surface and the substrate. A plurality of word line structures located across from a corresponding one of the bit structures on an opposite side of the intermediate layer of a corresponding one of said bit structures from its interconnection structure provides electrical contact thereto. Sufficient electrical current selectively drawn through each of these bit structures and its interconnection structure can cause substantial heating of that bit structure to raise temperatures thereof to have at least one of the magnetic material films therein at least approach its corresponding associated critical temperature while being substantially above temperatures of at least an adjacent said bit structure because of sufficient thermal isolation.

The invention provides a liquid crystal display panel and a driving method thereof. The 4j grid scanning line and the (4j-3) grid scanning line are set to be odd-number frame grid scanning lines, the (4j-1) grid scanning line and the (4j-2) grid scanning line are set to be even-number frame grid scanning lines, first red subpixels (R1), first green subpixels (G1) and first blue subpixels (B1) are electrically connected to the odd-number frame grid scanning lines, second red subpixels (R2), second green subpixels (G2) and second blue subpixels (B2) are electrically connected to the even-number frame grid scanning lines, odd-number frame scanning and even-number frame scanning are conducted by the odd-number frame grid scanning lines and the even-number frame grid scanning lines respectively, data signal delay can be effectively weakened, the charging effect of all the subpixels is ensured, light fringes of the liquid crystal display panel of the double grid line structure in the display process are eliminated, signal inversion frequency and the driving power consumption of the liquid crystal display panel are reduced.