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648results about "Delay lines" patented technology

Tunable microwave devices with auto-adjusting matching circuit

An impedance matching circuit includes a conductor line having an input port and an output port, a ground conductor, a tunable dielectric material positioned between a first section of the conductor line and the ground conductor, a non-tunable dielectric material positioned between a second section of the conductor line and the ground conductor, and means for applying a DC voltage between the conductor line and the ground conductor. The impedance matching circuit may alternatively include a first planar ground conductor, a second planar ground conductor, a strip conductor having an input port and an output port, and positioned between the first and second planar ground conductors to define first and second gaps, the first gap being positioned between the strip conductor and the first planar ground conductor and the second gap being positioned between the strip conductor and the second planar ground conductor. A non-tunable dielectric material supports the first and second planar ground conductors and the strip conductor in the same plane. A connection is provided for applying a DC voltage between the strip conductor and the first and second planar ground conductors. A plurality of tunable dielectric layer sections are positioned between the strip conductor and the first and second planar ground conductors so as to bridge the gaps between the said first and second planar ground conductors and the strip conductor at a plurality of locations, leaving non-bridged sections in between, defining a plurality of alternating bridged and non-bridged co-planar waveguide sections.
Owner:NXP USA INC

Phased array antenna interconnect having substrate slat structures

A phased array antenna is provided having a plurality of phase shifter devices for phase shifting and beam steering a radiated beam of the phased array antenna. The plurality of phase shifter devices are interconnected with an interconnect structure comprising a plurality of linear array substrate slats. Each linear array substrate slat includes a plurality of radiating elements formed using first and second metal layers of the substrate slat, a plurality of phase shifter devices and a common RF feed conductor for the plurality of radiating elements. The common RF feed conductor is formed on a third metal layer of the substrate slat that is disposed between the first and second metal layers. The common RF feed conductor is configured to include a single location for electrical connections to receive RF signals for the plurality of radiating elements. The phased array antenna also includes bias / control conductors applied to selected areas of the third metal layer, a fourth metal layer applied over the second metal layer and a shielding metal layer applied on the fourth metal layer. The bias / control conductors are configured to include a single location for electrical connections to receive bias voltages and control signals. The fourth metal layer includes circuit connections from the bias / control circuitry to the plurality of phase shifter devices. Each phase shifter device is attached to a radiating element via a mounting location on the shielding metal layer. Accordingly, a phased array antenna interconnect structure is provided that reduces the number of electrical connections required to provide RF signals and bias / control signals to multiple radiating elements and phase shifters, respectively, of the phased array antenna and provides a cost effective phased array antenna architecture that has a single locus of electrical connection for RF and bias control signals embedded in a multi-layer linear array or slat substrate of the phased array antenna.
Owner:ADVANCED HEALTH MEDIA +1

Adaptive equalizers and methods for carrying out equalization with a precoded transmitter

Adaptive equalization methods and adaptive equalizers used with precoded systems dominated by intersymbol interference (ISI) monitor the output of a DFE and compare it to a reference for updating a precoder in response to the comparison. To accomplish this, an adaptive equalizer includes a feed forward equalizer receiving a signal from a communication channel, the feed forward equalizer equalizing variations in pre-cursor intersymbol interference resulting from changes in characteristics of the channel and providing an output signal to an error correction decoder, a decision circuit, coupled to the feed forward equalizer, for generating error vectors in response to the output signal of the feed forward equalizer and a decision feedback equalizer, coupled to the decision circuit, the decision feedback equalizer monitoring the pre-cursor intersymbol interference of the channel, determining when the transmitter coefficients to the precoder warrant updating, and generating a signal indicating that an update to the transmitter coefficients to the precoder is warranted. The adaptive equalizer farther includes a comparison circuit, the comparison circuit receiving an output from the decision feedback equalizer and comparing the output from the decision feedback equalizer to a reference, the comparison circuit generating the signal indicating that an update to the transmitter coefficients to the precoder is warranted in response to the comparison.
Owner:LEVEL ONE COMM

High power, high linearity and low insertion loss single pole double throw transmitter/receiver switch

A high performance single-pole-double-throw (SPDT) Transmitter / Receiver (T / R) FET switch utilizes a plurality of multi-gate FETs in series to realize low insertion loss, low harmonic distortion and high power handling capabilities. The SPDT switch consists of an antenna port, a transmitter branch coupled to a transmitter port through a plurality of multi-gate FETs in series and a receiver branch coupled to a receiver port through a plurality of multi-gate FETs in series. When a high power signal passes from the transmitter port to the antenna port through the transmitter branch, the receiver branch is required to be shut off electrically to prevent the high power signal from leaking to receiver port. This leakage can degrade the isolation of the switch and cause harmonic distortion. Furthermore, the transmitter branch is required to provide a resistance as small as possible to reduce the power loss when it passes through the transmitter branch to the antenna port. In the receiver branch, two of the gate metals in the multi-gate FETs are fabricated with gate sizes several times larger than the others. Furthermore, a heavily doped cap layer is utilized between the gate fingers in a multi-gate FET to reduce the channel resistance of FET, thereby lowering the insertion loss.
Owner:ANALOG DEVICES INC
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