101results about How to "Reduce signal reflection" patented technology

An impedance matching circuit includes a conductor line having an input port and an output port, a ground conductor, a tunable dielectric material positioned between a first section of the conductor line and the ground conductor, a non-tunable dielectric material positioned between a second section of the conductor line and the ground conductor, and means for applying a DC voltage between the conductor line and the ground conductor. The impedance matching circuit may alternatively include a first planar ground conductor, a second planar ground conductor, a strip conductor having an input port and an output port, and positioned between the first and second planar ground conductors to define first and second gaps, the first gap being positioned between the strip conductor and the first planar ground conductor and the second gap being positioned between the strip conductor and the second planar ground conductor. A non-tunable dielectric material supports the first and second planar ground conductors and the strip conductor in the same plane. A connection is provided for applying a DC voltage between the strip conductor and the first and second planar ground conductors. A plurality of tunable dielectric layer sections are positioned between the strip conductor and the first and second planar ground conductors so as to bridge the gaps between the said first and second planar ground conductors and the strip conductor at a plurality of locations, leaving non-bridged sections in between, defining a plurality of alternating bridged and non-bridged co-planar waveguide sections.

A low voltage differential signal driver includes first and second current sources, a first branch and a second branch. The first branch includes at least two transistors and at least two resistors between them that are all connected in series between the first and second current sources, to define a first node between adjacent resistors that is configured to transmit and receive differential signals. The second branch also includes at least two transistors and at least two resistors between them that also are all connected in series between the first and second current sources, to define a second node between adjacent resistors that is also configured to transmit and receive differential signals.

A system and method is presented for reducing skew between the positive and negative components of a differential signal in a high speed communications link. The communications link includes a signal generator producing and transmitting complementary positive and negative signals over separate transmission lines and a receiver receiving the complementary signals. The communication link further includes a skew compensation circuit having a skew detector, a controller, and separate delay and buffer elements for both the positive and negative component of the differential signal. The controller separately controls each of the delay or buffer elements in response to the detected skew between differential signal components.

A digital visual interface dual-stack connector includes a holder base and a first connector and a second connector mounted in the holder base at different elevations, the second connector having multiple second terminal pins arranged in three sets and mounted in a slotted mating body portion of a housing thereof, each second terminal pin defining a vertical rear bonding portion, a horizontal front contact portion, an oblique support arm portion and two curved portions respectively connected between the vertical rear bonding portion and horizontal front contact portion and the two ends of the support arm portion. By means of controlling the bending angles of the two curved portions of the second terminal pins and the pitch between each two adjacent second terminal pins, the invention accurately achieves impedance matching to reduce high frequency signal reflection, enhancing signal transmission stability and reliability.