914results about "High frequency circuit adaptations" patented technology

The invention provides a circuit board processing method and a circuit board, and the method comprises the steps: carrying out the first drilling of the circuit board, so as to form a plurality of through holes; acquiring horizontal position information of a target through hole in the plurality of through holes; according to the horizontal position information of the target through hole, the position of a target signal layer corresponding to the target through hole in the vertical direction is measured, the vertical position information of the target signal layer is obtained, and the target signal layer is exposed on the hole wall of the through hole; and according to the vertical position information of the target signal layer, performing second drilling at the target through hole position of the circuit board to form a back drilling hole, and enabling the stub length after the second drilling to be within a preset range. According to the method, the problems of line damage, excessive stub length and the like caused by position deviation can be effectively avoided, the stub length after back drilling can be strictly controlled within a preset range, and interference of the stub on high-frequency signals is remarkably reduced.

A component carrier including: i) a stack with at least one electrically insulating layer structure and at least one electrically conductive layer structure; ii) a first metal trace comprising a rough surface; and iii) a second metal trace arranged adjacent to the first metal trace, comprising a smooth surface. The component carrier is configured to guide high-frequency and or high-speed signals through the second metal trace.

The invention discloses an optimized high-speed differential via hole structure, which is characterized in that high-speed differential via holes are arranged in each wiring layer, each wiring layer is provided with a corresponding anti-pad, and corresponding wires are laid in the high-speed differential via holes; marking the part of the wire in each suspension area outside the corresponding anti-bonding pad close to the wiring layer as a suspension wire, marking the part of the wire in the high-speed differential via hole as a via hole wire, thickening the suspension wire, and controlling the suspension wire to be thicker than the via hole wire; and reducing the size of the anti-bonding pad in each non-adjacent wiring layer, and controlling the size of the anti-bonding pad in each non-adjacent wiring layer to be smaller than the size of the anti-bonding pad in each adjacent wiring layer. According to the invention, through combined use of the thickened suspension line, reduction of the non-adjacent wiring layer anti-bonding pad and increase of the adjacent wiring layer anti-bonding pad, the impedance of each part is effectively adjusted, and the impedance requirement of high-speed signal transmission is met; and the optimized mode is high in universality, simple and efficient.

The embodiment of the invention provides a circuit board, communication equipment and a chip, the circuit board is used for connecting an electronic device, the circuit board is used for inhibiting thermal expansion coefficient mismatch between the circuit board and the electronic device, and the insertion loss of the circuit board can be effectively reduced. Along the direction perpendicular to the surface of the circuit board, the circuit board comprises M sub-boards arranged in sequence, M is any integer not less than 2, and the M sub-boards comprise a first sub-board and a second sub-board. The thermal expansion coefficient of the first daughter board is smaller than that of the second daughter board, and the dielectric loss factor of the second daughter board is smaller than that of the first daughter board.

The embodiment of the invention provides a circuit board and electronic equipment, relates to the technical field of signal transmission, and is used for solving the problem of signal crosstalk between different channels in the circuit board. A signal layer of the circuit board can comprise a first dielectric layer, a first grounding part and a second grounding part of two adjacent signal channels. The signal channel can comprise a transmission line arranged on the first dielectric layer, and a first grounding part and a second grounding part of the transmission line are located on the same side surface of the first dielectric layer to form a coplanar waveguide. The first grounding part and the second grounding part are located between the two adjacent signal channels and are arranged at intervals. The first grounding part and the second grounding part are used for providing different backflow paths to flow backflow signals of two adjacent signal channels, so that crosstalk between different backflow signals is reduced.

RADAR sensor assemblies / modules, particularly those for vehicles. In some embodiments, the assembly may comprise a waveguide comprising a waveguide groove defined by opposing waveguide groove structures. An antenna structure may be operably coupled with the waveguide. A printed circuit board may be operably coupled with the waveguide and may comprise an electrically conductive top layer, an electrically conductive bottom layer, and a substrate positioned in between the electrically conductive top layer and the electrically conductive bottom layer. The electrically conductive top layer may comprise an opening exposing the substrate, which opening may extend along the waveguide groove in between the opposing waveguide groove structures. This configuration may allow for various parameters of the printed circuit board to be modified to tune a performance of a sensor / antenna.

The invention discloses a multi-layer high-frequency PCB board and a preparation method thereof, belonging to the technical field of PCB board preparation. The multi-layer high-frequency PCB board is composed of an inner layer board, a heat dissipation layer and an outer layer board, and the inner layer board, the heat dissipation layer and the outer layer board are arranged in sequence from the inside to the outside, the surface of the inner layer board is covered with a layer of composite film, the heat dissipation layer is composed of a composite aerogel material, and the layers are fixed by hot pressing technology. The multi-layer high-frequency PCB board prepared by the method has excellent high frequency and heat dissipation.

A flexible circuit board and a foldable electronic device includes a first multi-layer region, a second multi-layer region and a highly bendable region disposed between the first multi-layer region and the second multi-layer region. The first multi-layer region and the second multi-layer region include a structure in which a plurality of copper clad laminates (CCLs) are stacked. The highly bendable region includes a structure in which a single CCL extending from one CCL among the plurality of CCLs in the first multi-layer region and the second multi-layer region is stacked. The single CCL may be configured such that a first ground wire, a second ground wire, and a plurality of sub wires disposed to be spaced apart between the first ground wire and the second ground wire transmit a single RF signal.

A high-frequency signal transmission line (102) is provided with: a resin laminate part in which first resin layers (11, 12, 13) and second resin layers (21, 22) are laminated; a signal conductor pattern (4) formed on the first resin layer (11); and ground conductor layers (51, 52) that face the signal conductor pattern across the resin laminate part. Opening portions are formed in the first resin layers (11, 12) at a position along the signal conductor pattern (4) in the resin laminate part so that a hollow portion (HP) is provided in the resin laminate part at the opening portions. The second resin layers (22) in contact with the first resin layers (11, 12) having the opening portions are provided with a maximum thickness and a minimum thickness that are different in the opening portions formed in the first resin layers so that the second resin layers in contact with the first resin layers are adhered to a part of end surfaces of the first resin layers (11, 12) at the opening portions.

To increase the resonance frequency of resonance occurring upon input of a signal of a specific frequency to a chip when the chip is mounted in a sample holder.SOLUTION: A sample holder includes a pedestal and a PCB (Printed Circuit Board) 3 in contact with the pedestal. The PCB 3 has a through-hole 4. The PCB 3 has a cavity 5 at least at a part of the pedestal below the through-hole 4. The cavity 5 has a support structure which supports the surface of the chip and is in communication with the pedestal. At least a part of the portion of the support structure which supports the chip 7 is not parallel to the back surface of the chip. The support structure includes conductor posts 6 located at the four corners of the cavity 5. At least a part of the upper surface of the post 6 is not parallel to the upper surface of the pedestal.SELECTED DRAWING: Figure 10A

A layout of signal traces includes a first set of signal traces and a second set of signal traces that are used for transmitting a first differential signal and a second differential signal respectively. Each set of signal traces includes a first part, a second part, and a third part along the direction of signal transmission. Different parts of the same signal trace as a whole is not straight. All the first parts are in a first signal layer and parallel. The second parts of the two sets of signal traces are in a second signal layer and the first signal layer, respectively, and are across each other. The second part of the first / second set of signal traces is coupled with the first and third parts of the first / second set of signal traces. All the third parts are in the first signal layer and parallel.

The present disclosure relates to flexible printed circuit boards (FPCBs) for augmented reality (AR) eyewear. Disclosed examples provide an FPCB with air gaps for enhanced bending flexibility and an Electromagnetic Interference (EMI) film for consistent ground reference, enabling high-speed signal transmission with controlled impedance. The FPCB may include asymmetrical dielectric thicknesses and a crosshatch pattern in the ground reference layer to further support signal integrity and mechanical durability.

The disclosure relates to a circuit board. A circuit board according to an embodiment of the disclosure may comprise a base layer positioned in a first portion of the circuit board and a second portion of the circuit board different from the first portion of the circuit board, a power line positioned in the first portion of the circuit board, a signal line positioned in the second portion of the circuit board, a shielding layer spaced apart from the power line and the signal line, and a cover layer disposed between the base layer and the shielding layer. The cover layer may include a cover base layer positioned in the first portion and the second portion of the circuit board, a conductive layer positioned in the first portion of the circuit board to correspond to the power line, and disposed between the cover base layer and the shielding layer, and an insulating layer positioned in the second portion of the circuit board to correspond to the signal line, and disposed between the cover base layer and the shielding layer.

An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.

The invention relates to the technical field of semiconductors, in particular to a precise circuit board with an ultrahigh-frequency multilayer memory bank, which comprises a functional circuit surface layer, a high-speed signal layer, an upper grounding layer, an upper waveguide insulating layer, a power supply layer, a lower waveguide insulating layer, a lower grounding layer and a functional circuit bottom layer, the functional circuit surface layer, the high-speed signal layer, the upper grounding layer, the upper waveguide insulating layer, the power supply layer, the lower waveguide insulating layer, the lower grounding layer and the functional circuit bottom layer are sequentially stacked from top to bottom, a conductive groove is formed in the high-speed signal layer in a penetrating mode, a conductive column is arranged in the conductive groove in a matched mode, and waveguide grooves are formed in the tops of the upper waveguide insulating layer and the lower waveguide insulating layer. And a waveguide tube is arranged in the waveguide groove. According to the scheme provided by the invention, by arranging the trapezoidal conductive columns and utilizing the function of dispersing high-frequency current distribution by the asymmetric cross sections of the conductive columns, the skin effect is reduced, the signal integrity is improved, and the effect of optimizing the high-speed signal transmission time sequence consistency is achieved through the obliquely arranged waveguide tubes.

There is provided a printed wiring board including an outermost conductive layer that includes a plurality of conductive pads, a first conductive layer that includes a first inner-layer wiring and is stacked on the conductive layer, a second conductive layer that includes a second inner-layer wiring and is stacked on the conductive layer and the first conductive layer, a first signal via that connects one of the conductive pads and the first inner-layer wiring with each other, a second signal via connecting another one of the conductive pads and the second inner-layer wiring with each other, and a stitching via that is connected to a ground. The first inner-layer wiring and the second inner-layer wiring form a common wiring route in which the first inner-layer wiring and the second inner-layer wiring are stacked and disposed in a connection area in which the conductive pads are arranged.

A PCB bridge, used to interconnect two or more semiconductor chips for data communication, comprises: a plurality of metal strips; and a dielectric material disposed between the plurality of metal strips. The PCB bridge is used in a vertical direction within a semiconductor module to interconnect two or more semiconductor chips. By adjusting the dielectric material and trace width of the PCB bridge, the vertical direction of the PCB bridge provides flexible impedance matching. By matching the impedance to the source, the vertical direction of the PCB bridge prevents signal reflections. The trace length of the PCB bridge is limited by the spacing between the two semiconductor chips, which further limits the inductance of the PCB bridge traces.

Provided are: a fluororesin sheet having both a low linear expansion coefficient (CTE) and improved adhesion to a copper foil having a smooth surface; and a copper-clad laminate using the fluororesin sheet. A fluororesin sheet containing a fluororesin and silica particles, the fluororesin sheet having an oxygen element ratio of 3.0 at% or more and a linear expansion coefficient (CTE) of 100 ppm / DEG C or less when measured by X-ray photoelectron spectroscopy (XPS) on one or both surfaces thereof.

The invention relates to a printed circuit board, electronic equipment and a vehicle. The printed circuit board comprises a multi-layer circuit substrate, a first impedance line, a second impedance line and a reference layer. The first impedance line and the second impedance line are respectively positioned on the circuit substrates of different layers and are electrically connected through via holes; the reference layer is located in a via hole avoiding area and is arranged between a layer where the first impedance line is located and a layer where the second impedance line is located, the reference layer is overlapped with the first impedance line and / or the second impedance line in the stacking direction of the circuit substrate, the reference layer is connected with a reference potential, and the reference layer is connected with the second impedance line. And the via hole avoiding area is arranged around the via hole. According to the technical scheme, the problem that the impedance line is inductively suddenly changed at the via hole position can be solved.

The invention provides a waveguide device. The waveguide device comprises a waveguide structure, an electronic component and a driving circuit, the waveguide structure comprises a first conductor layer, a second conductor layer, an insulating layer and a through hole array. The second conductor layer is disposed over the first conductor layer. The insulating layer is disposed between the first conductor layer and the second conductor layer. The through hole array is arranged in the insulating layer and comprises a plurality of first through holes and at least one second through hole. The plurality of first through-holes are arranged in a first direction and disposed on opposite sides of the insulating layer in a second direction, wherein the first direction intersects the second direction and each first through-hole includes a hollow portion and a conductor portion surrounding the hollow portion. The at least one second through hole is arranged between two adjacent first through holes in the first direction and penetrates through the first conductor layer and the second conductor layer. The electronic component is arranged on the waveguide structure and is electrically connected with the second conductor layer. The driving circuit is arranged below the waveguide structure and is electrically connected with the electronic component through at least one second through hole.

In an embodiment of the present disclosure, a wiring board includes a first insulating layer, a second insulating layer, a signal line, and a first ground conductor line. The first insulating layer includes a first upper surface and a first lower surface. The second insulating layer is positioned on the first insulating layer and includes a second upper surface, a second lower surface, and one or more first opening parts each including an opening at the second upper surface. The signal line is positioned on the second upper surface. The first ground conductor line is positioned on the second upper surface and extends along the signal line with a first gap between the signal line and first ground conductor line. In plan view, at least one first opening part is positioned between the signal line and first ground conductor line and is in contact with the first ground conductor line.

A method for controlled filling of a backdrill cavity in an unused portion of a via to a desired penetration depth of the backdrill cavity can begin with setting a starting gas pressure in the backdrill cavity to a back-filling fixture chamber pressure in a filling pressure chamber. The back-filling fixture chamber pressure is selected based on a desired penetration depth h of a non-conductive filling material within the backdrill cavity, given a fill application pressure to be applied to the backdrill cavity. Then, the non-conductive filling material is applied with the fill application pressure to the backdrill cavity until a final gas pressure in the backdrill cavity equals to the fill application pressure and the backdrill cavity has a final gas volume of π / 4d2(H−h), where H represents a backdrill depth and d represents a backdrill diameter of the backdrill cavity.

The invention discloses a circuit board and a preparation method thereof, and an electronic device, the disclosed circuit board comprises a circuit board main body (100) and a via hole structure (200), the circuit board main body (100) is provided with a hole segment (101) and a back drilling hole (102) which are communicated with each other, an orifice of the hole segment (101) is located in a first surface of the circuit board main body (100), and the hole segment (101) is located in a second surface of the circuit board main body (100). The circuit board comprises a circuit board body (100) and a hole section (101), the hole section (101) is provided with a back drilling hole (102), the hole opening of the back drilling hole (102) is located in the second surface of the circuit board body (100), the first surface and the second surface are opposite to each other, the inner wall of the hole section (101) is provided with a metal layer to form the via hole structure (200), the via hole structure (200) is filled with a first filler (300), the back drilling hole (102) is filled with a second filler (400), and the first filler (300) and the second filler (400) are arranged in the via hole structure (200). And the dielectric constant of the second filler (400) is smaller than that of the circuit board main body (100). According to the scheme, the impedance of the via hole structure can be improved.

The present invention relates to a metal foil having a rough surface, a carrier-attached metal foil including the metal foil, and a printed circuit board manufactured using the metal foil. The rough surface is naturally formed during formation of the metal foil. The formation of the rough surface allows the metal foil to have a high adhesive strength to an insulating resin substrate and enables the manufacture of a printed circuit board with improved efficiency.

The embodiment of the invention provides a printed circuit board and an intelligent robot brain with a body, and relates to the technical field of printed circuits. The printed circuit board is applied to the domain brain of the intelligent robot with the body, the printed circuit board comprises two independent printed circuit boards, namely a brain board and a cerebellum board, the brain board is used for bearing a graphics processing unit (GPU), the cerebellum board is used for bearing a central processing unit (CPU), and the brain board and the cerebellum board are electrically connected through a board-to-board connector in a plug-in mode. The printed circuit board has relatively high signal integrity, and can meet the requirements of a brain of an intelligent robot with a body.

This disclosure provides a circuit board and an electronic device. In addition to a PCB, the circuit board may further include an FPC assembled on the PCB. In addition, a line between different components assembled on the PCB includes a line in the PCB, and further includes a line in the FPC. Because a quantity of core boards in the FPC is generally far less than a quantity of core boards in the PCB, selecting a core board with a dielectric loss less than that of the core board in the PCB for the FPC helps reduce a transmission loss of a high-speed signal in the circuit board, and helps reduce costs of the circuit board. This disclosure further provides an electronic device. Selecting, for the electronic device, the circuit board provided in this disclosure helps improve cost competitiveness of the electronic device in a high-speed high-density scenario.

The invention relates to an amplifier circuit (1) for broadband and low-noise amplification of a capacitive current source, preferably a thermoelectric sensor, comprising: a signal input (3) which can be connected to the capacitive current source in a node K1; the invention relates to an amplifier (1) for amplifying an input voltage, comprising an input stage (A1), which is connected to a node K1 at an input (7) of the input stage (A1) and has a node K2 at an output (9) of the input stage (A1), the input stage (A1) being designed to amplify the input voltage by at least three times, the input stage (A1) being designed to provide a high-ohm input resistance at the input of the input stage (A1), the input stage (A1) is designed to provide a stable and load-independent voltage at the output of the input stage (A1); the invention relates to a power amplifier comprising a first amplifier (A1) and a second amplifier (A3), an amplifier cascade (11) having at least a first amplifier and a second amplifier (A2, A3), each having an input (13, 17) and an output (15, 19), the output (15) of the first amplifier (A2) being connected in a node K3 to the input (17) of the second amplifier (A3), the input (13) of the first amplifier (A2) being connected to a node K2, the output (15, 19) being connected in a node K3 to the input (17) of the second amplifier (A3). An output (19) of the second amplifier (A3) is connected to a node K4, the amplifier cascade (11) being arranged to produce a high signal gain with a low phase shift over a wide frequency range; a feedback network (F1), which is connected to the input (7) of the input stage (A1) in a node K1 and to the output (19) of the second amplifier (A3) in a node K4, said feedback network (F1) being designed to provide a high-ohm feedback resistance with a parasitic capacitance of less than 0.5 pF, the feedback network (F1) is arranged to provide a negative feedback to a structure comprising the input stage (A1) and the amplifier cascade (11), and a signal output (21) connected to a node K5, which is connected to or corresponds to a node K4. The invention also relates to a sensor system.

A substrate comprises a monolithic structure formed from a dielectric material, with a first side, a second side, and an intermediate region between the first and second sides. The intermediate region has a lattice structure of the dielectric material with a plurality of interstitial spaces between the dielectric material of the lattice structure. The lattice structure extends between the first and second sides and monolithically joins them. At least one of the first and second sides has a substantially solid surface that is suitably designed to support one or more of the following functions: mapping of electronic circuits, electroplating, metal deposition, or vias between the first and second sides.

[Problem] To provide a copper-clad laminate capable of simultaneously achieving good volume resistivity in an electroless copper plating layer of a low dielectric resin film and suppression of transmission loss when applied to a flexible circuit board, and a manufacturing method thereof. [Solution] This copper-clad laminate is characterized by including a low dielectric resin film which has a relative dielectric constant of 3.5 or lower and a dielectric loss tangent of 0.008 or lower at a frequency of 10 GHz and an electroless copper plating layer which is laminated on at least one surface of the low dielectric resin film, wherein the electroless copper plating layer has a Ni-content of 0.01 to 1.2 wt%, and the electroless copper plating layer has a volume resistivity of 6.0 µΩ·cm or lower.

An element, a method of forming an element, and a method of assembling an element on an electronic device are provided. For example, a method of forming an element includes providing a first substrate having a first surface, a second surface opposite the first surface in a height direction, and an initial thickness from the first surface to the second surface in the height direction; forming one or more vias in the first substrate, each via extending from the first surface of the first substrate to the second surface of the first substrate; depositing one or more conductive vias on the first surface of the first substrate; plating the one or more vias; disposing a second substrate on the first surface of the first substrate to form a device laminated structure; processing the second surface of the first substrate to reduce the thickness of the device laminated structure; and forming one or more contact pads on the first substrate.