719results about "High frequency circuit adaptations" patented technology

The invention provides a circuit board processing method and a circuit board, and the method comprises the steps: carrying out the first drilling of the circuit board, so as to form a plurality of through holes; acquiring horizontal position information of a target through hole in the plurality of through holes; according to the horizontal position information of the target through hole, the position of a target signal layer corresponding to the target through hole in the vertical direction is measured, the vertical position information of the target signal layer is obtained, and the target signal layer is exposed on the hole wall of the through hole; and according to the vertical position information of the target signal layer, performing second drilling at the target through hole position of the circuit board to form a back drilling hole, and enabling the stub length after the second drilling to be within a preset range. According to the method, the problems of line damage, excessive stub length and the like caused by position deviation can be effectively avoided, the stub length after back drilling can be strictly controlled within a preset range, and interference of the stub on high-frequency signals is remarkably reduced.

The invention discloses an optimized high-speed differential via hole structure, which is characterized in that high-speed differential via holes are arranged in each wiring layer, each wiring layer is provided with a corresponding anti-pad, and corresponding wires are laid in the high-speed differential via holes; marking the part of the wire in each suspension area outside the corresponding anti-bonding pad close to the wiring layer as a suspension wire, marking the part of the wire in the high-speed differential via hole as a via hole wire, thickening the suspension wire, and controlling the suspension wire to be thicker than the via hole wire; and reducing the size of the anti-bonding pad in each non-adjacent wiring layer, and controlling the size of the anti-bonding pad in each non-adjacent wiring layer to be smaller than the size of the anti-bonding pad in each adjacent wiring layer. According to the invention, through combined use of the thickened suspension line, reduction of the non-adjacent wiring layer anti-bonding pad and increase of the adjacent wiring layer anti-bonding pad, the impedance of each part is effectively adjusted, and the impedance requirement of high-speed signal transmission is met; and the optimized mode is high in universality, simple and efficient.

A flexible circuit board and a foldable electronic device includes a first multi-layer region, a second multi-layer region and a highly bendable region disposed between the first multi-layer region and the second multi-layer region. The first multi-layer region and the second multi-layer region include a structure in which a plurality of copper clad laminates (CCLs) are stacked. The highly bendable region includes a structure in which a single CCL extending from one CCL among the plurality of CCLs in the first multi-layer region and the second multi-layer region is stacked. The single CCL may be configured such that a first ground wire, a second ground wire, and a plurality of sub wires disposed to be spaced apart between the first ground wire and the second ground wire transmit a single RF signal.

A high-frequency signal transmission line (102) is provided with: a resin laminate part in which first resin layers (11, 12, 13) and second resin layers (21, 22) are laminated; a signal conductor pattern (4) formed on the first resin layer (11); and ground conductor layers (51, 52) that face the signal conductor pattern across the resin laminate part. Opening portions are formed in the first resin layers (11, 12) at a position along the signal conductor pattern (4) in the resin laminate part so that a hollow portion (HP) is provided in the resin laminate part at the opening portions. The second resin layers (22) in contact with the first resin layers (11, 12) having the opening portions are provided with a maximum thickness and a minimum thickness that are different in the opening portions formed in the first resin layers so that the second resin layers in contact with the first resin layers are adhered to a part of end surfaces of the first resin layers (11, 12) at the opening portions.

A layout of signal traces includes a first set of signal traces and a second set of signal traces that are used for transmitting a first differential signal and a second differential signal respectively. Each set of signal traces includes a first part, a second part, and a third part along the direction of signal transmission. Different parts of the same signal trace as a whole is not straight. All the first parts are in a first signal layer and parallel. The second parts of the two sets of signal traces are in a second signal layer and the first signal layer, respectively, and are across each other. The second part of the first / second set of signal traces is coupled with the first and third parts of the first / second set of signal traces. All the third parts are in the first signal layer and parallel.

The present disclosure relates to flexible printed circuit boards (FPCBs) for augmented reality (AR) eyewear. Disclosed examples provide an FPCB with air gaps for enhanced bending flexibility and an Electromagnetic Interference (EMI) film for consistent ground reference, enabling high-speed signal transmission with controlled impedance. The FPCB may include asymmetrical dielectric thicknesses and a crosshatch pattern in the ground reference layer to further support signal integrity and mechanical durability.

The disclosure relates to a circuit board. A circuit board according to an embodiment of the disclosure may comprise a base layer positioned in a first portion of the circuit board and a second portion of the circuit board different from the first portion of the circuit board, a power line positioned in the first portion of the circuit board, a signal line positioned in the second portion of the circuit board, a shielding layer spaced apart from the power line and the signal line, and a cover layer disposed between the base layer and the shielding layer. The cover layer may include a cover base layer positioned in the first portion and the second portion of the circuit board, a conductive layer positioned in the first portion of the circuit board to correspond to the power line, and disposed between the cover base layer and the shielding layer, and an insulating layer positioned in the second portion of the circuit board to correspond to the signal line, and disposed between the cover base layer and the shielding layer.

The invention relates to the technical field of semiconductors, in particular to a precise circuit board with an ultrahigh-frequency multilayer memory bank, which comprises a functional circuit surface layer, a high-speed signal layer, an upper grounding layer, an upper waveguide insulating layer, a power supply layer, a lower waveguide insulating layer, a lower grounding layer and a functional circuit bottom layer, the functional circuit surface layer, the high-speed signal layer, the upper grounding layer, the upper waveguide insulating layer, the power supply layer, the lower waveguide insulating layer, the lower grounding layer and the functional circuit bottom layer are sequentially stacked from top to bottom, a conductive groove is formed in the high-speed signal layer in a penetrating mode, a conductive column is arranged in the conductive groove in a matched mode, and waveguide grooves are formed in the tops of the upper waveguide insulating layer and the lower waveguide insulating layer. And a waveguide tube is arranged in the waveguide groove. According to the scheme provided by the invention, by arranging the trapezoidal conductive columns and utilizing the function of dispersing high-frequency current distribution by the asymmetric cross sections of the conductive columns, the skin effect is reduced, the signal integrity is improved, and the effect of optimizing the high-speed signal transmission time sequence consistency is achieved through the obliquely arranged waveguide tubes.

There is provided a printed wiring board including an outermost conductive layer that includes a plurality of conductive pads, a first conductive layer that includes a first inner-layer wiring and is stacked on the conductive layer, a second conductive layer that includes a second inner-layer wiring and is stacked on the conductive layer and the first conductive layer, a first signal via that connects one of the conductive pads and the first inner-layer wiring with each other, a second signal via connecting another one of the conductive pads and the second inner-layer wiring with each other, and a stitching via that is connected to a ground. The first inner-layer wiring and the second inner-layer wiring form a common wiring route in which the first inner-layer wiring and the second inner-layer wiring are stacked and disposed in a connection area in which the conductive pads are arranged.

A PCB bridge, used to interconnect two or more semiconductor chips for data communication, comprises: a plurality of metal strips; and a dielectric material disposed between the plurality of metal strips. The PCB bridge is used in a vertical direction within a semiconductor module to interconnect two or more semiconductor chips. By adjusting the dielectric material and trace width of the PCB bridge, the vertical direction of the PCB bridge provides flexible impedance matching. By matching the impedance to the source, the vertical direction of the PCB bridge prevents signal reflections. The trace length of the PCB bridge is limited by the spacing between the two semiconductor chips, which further limits the inductance of the PCB bridge traces.

Provided are: a fluororesin sheet having both a low linear expansion coefficient (CTE) and improved adhesion to a copper foil having a smooth surface; and a copper-clad laminate using the fluororesin sheet. A fluororesin sheet containing a fluororesin and silica particles, the fluororesin sheet having an oxygen element ratio of 3.0 at% or more and a linear expansion coefficient (CTE) of 100 ppm / DEG C or less when measured by X-ray photoelectron spectroscopy (XPS) on one or both surfaces thereof.

The present invention relates to a metal foil having a rough surface, a carrier-attached metal foil including the metal foil, and a printed circuit board manufactured using the metal foil. The rough surface is naturally formed during formation of the metal foil. The formation of the rough surface allows the metal foil to have a high adhesive strength to an insulating resin substrate and enables the manufacture of a printed circuit board with improved efficiency.

The embodiment of the invention provides a printed circuit board and an intelligent robot brain with a body, and relates to the technical field of printed circuits. The printed circuit board is applied to the domain brain of the intelligent robot with the body, the printed circuit board comprises two independent printed circuit boards, namely a brain board and a cerebellum board, the brain board is used for bearing a graphics processing unit (GPU), the cerebellum board is used for bearing a central processing unit (CPU), and the brain board and the cerebellum board are electrically connected through a board-to-board connector in a plug-in mode. The printed circuit board has relatively high signal integrity, and can meet the requirements of a brain of an intelligent robot with a body.

This disclosure provides a circuit board and an electronic device. In addition to a PCB, the circuit board may further include an FPC assembled on the PCB. In addition, a line between different components assembled on the PCB includes a line in the PCB, and further includes a line in the FPC. Because a quantity of core boards in the FPC is generally far less than a quantity of core boards in the PCB, selecting a core board with a dielectric loss less than that of the core board in the PCB for the FPC helps reduce a transmission loss of a high-speed signal in the circuit board, and helps reduce costs of the circuit board. This disclosure further provides an electronic device. Selecting, for the electronic device, the circuit board provided in this disclosure helps improve cost competitiveness of the electronic device in a high-speed high-density scenario.

[Problem] To provide a copper-clad laminate capable of simultaneously achieving good volume resistivity in an electroless copper plating layer of a low dielectric resin film and suppression of transmission loss when applied to a flexible circuit board, and a manufacturing method thereof. [Solution] This copper-clad laminate is characterized by including a low dielectric resin film which has a relative dielectric constant of 3.5 or lower and a dielectric loss tangent of 0.008 or lower at a frequency of 10 GHz and an electroless copper plating layer which is laminated on at least one surface of the low dielectric resin film, wherein the electroless copper plating layer has a Ni-content of 0.01 to 1.2 wt%, and the electroless copper plating layer has a volume resistivity of 6.0 µΩ·cm or lower.

An element, a method of forming an element, and a method of assembling an element on an electronic device are provided. For example, a method of forming an element includes providing a first substrate having a first surface, a second surface opposite the first surface in a height direction, and an initial thickness from the first surface to the second surface in the height direction; forming one or more vias in the first substrate, each via extending from the first surface of the first substrate to the second surface of the first substrate; depositing one or more conductive vias on the first surface of the first substrate; plating the one or more vias; disposing a second substrate on the first surface of the first substrate to form a device laminated structure; processing the second surface of the first substrate to reduce the thickness of the device laminated structure; and forming one or more contact pads on the first substrate.

A solder connection (1) between a coaxial cable (2) and a printed circuit board arrangement (3). The coaxial cable (2) comprises an inner conductor (4), an outer conductor (6) and a dielectric (5) arranged in between. The printed circuit board arrangement (3) comprises an outer conductor contact area (8) and an inner conductor contact area (9). The outer conductor contact area (8) comprises an outer conductor receiving opening (12). The coaxial cable (2) runs at an angle to the printed circuit board arrangement (3), wherein a part of the outer conductor (6) is arranged in the outer conductor receiving opening (12) and wherein the inner conductor (4) is arranged at the inner conductor contact area (9). A first solder joint (10) connects the outer conductor (6) to the outer conductor contact area (8). A second solder joint (11) connects the inner conductor (4) to the inner conductor contact area (9).

A wiring board includes a base body, a signal line located at the base body, and a waveguide of a waveguide-type located at the base body. The signal line includes a first end part that is one end of the signal line in a signal transmission direction. The waveguide includes a second end part that is one end of the waveguide in the signal transmission direction, a center part in the signal transmission direction, and an intermediate part on a side of the second end part closer to the center part. The first end part and the second end part are coupled to one another. A width of the waveguide at the second end part is wider than a width of the waveguide at the intermediate part.

This high-frequency substrate is provided with: a first laminate in which a first conductive layer and a first resin layer are laminated; a second laminate in which a second conductive layer and a second resin layer are laminated, the second laminate being disposed so as to face the first laminate; a first via hole; the first laminated body is provided with a conductive pattern, the conductive pattern is provided with a signal line and a grounding layer, the bottom surface of the first via hole is in contact with the grounding layer, the first conductive layer is conducted with the grounding layer through the first via hole, the bottom surface of the second via hole is in contact with the grounding layer, and the second conductive layer is conducted with the grounding layer through the second via hole; the first resin layer and the second resin layer are mainly composed of a resin having a linear expansion coefficient of 20 ppm / K or more at 20-120 DEG C. The first conductive layer has a first opening portion in a peripheral region of an opening of the first via hole, and the second conductive layer has a second opening portion in a peripheral region of an opening of the second via hole.

The antenna substrate of the embodiment includes a substrate, an antenna pattern layer on the substrate, a first insulating layer containing a resin and an inorganic filler on the substrate and the antenna pattern layer, and a second insulating layer containing a resin and an inorganic filler on the first insulating layer, wherein the second insulating layer has a greater dielectric constant and thickness than the first insulating layer.

Provided is an electronic device having an antenna. The electronic device comprises: a radiator configured by stacking metal patterns on different layers of a multi-layer structure; and an antenna module including a feeding unit disposed on a specific layer of the radiator and having a feeding line configured to be connected to the radiator, wherein the radiator includes a first pad connected to the feeding line and a second pad disposed on the first pad, and the first pad and the second pad are connected to each other by a first connection line and a second connection line.

A differential transmission board set includes a mounting board on which a compression connector is mounted and a contact board configured to come into contact with the compression connector. In the contact board, a second conductor layer is a ground layer and has a penetrating hole. The penetrating hole is formed in such a way that a first signal pad and a second signal pad are both located inside an inner edge of the penetrating hole. In the contact board, the penetrating hole is formed to overlap an outer region of the first ground pad and an outer region of the second ground pad.

A directional coupler according to various embodiment and an electronic device having the same are provided. The directional coupler includes a first layer having at least one conductive portion, a second layer disposed adjacent to the first layer in a first direction and having at least one conductive plate corresponding to the conductive portion of the first layer, a third layer disposed adjacent to the second layer in the first direction and including an RF signal transmission line, a fourth layer disposed adjacent to the third layer in the first direction and having a conductive line wound with at least one turn, and at least one conductive via electrically connecting the at least one conductive plate of the second layer and the conductive line of the fourth layer which is wound with at least one turn.

A wiring board includes a wiring layer, a shield layer, and an insulating layer. The wiring layer includes at least one signal line and at least one ground line. The shield layer overlaps the wiring layer in plan view. The insulating layer is provided between the wiring layer and the shield layer. The insulating layer includes at least one end portion surrounded by the insulating layer. The at least one end portion is located on at least the at least one ground line. A connection conductor line electrically connecting the shield layer to the at least one ground line is provided on part of the at least one end portion.

The present disclosure relates to a dielectric substrate that may include a first fluoropolymer based adhesive layer, a polyimide layer overlying the fluoropolymer based adhesive layer, and a first filled polymer layer overlying the polyimide layer. The first filled polymer layer may include a resin matrix component, and a first ceramic filler component. The first ceramic filler component may include a first filler material. The first filler material may further have a mean particle size of at not greater than about 10 microns.

A multilayer substrate includes a stacked body and a first conductor layer. The stacked body includes insulator layers stacked in a stacking direction. The first conductor layer is provided in the stacked body. In the stacked body, interior spaces that are not connected to a space outside the stacked body are provided. The first conductor layer includes a first principal surface and a second principal surface including an exposed portion exposed to the interior spaces. A surface roughness of the exposed portion is greater than a surface roughness of the first principal surface.

A circuit board according to an embodiment of the disclosure can include a substrate layer on a first portion of the circuit board and a second portion of the circuit board different from the first portion, a power line on the first portion of the circuit board, a signal line on the second portion of the circuit board, a shield layer spaced apart from the power line and the signal line, and a cover layer between the substrate layer and the shield layer, wherein the cover layer includes a cover substrate layer on the first portion and the second portion of the circuit board, a conductive layer on the first portion of the circuit board corresponding to the power line and between the cover substrate layer and the shield layer, and an insulating layer on the second portion of the circuit board corresponding to the signal line and disposed between the cover substrate layer and the shield layer.

Disclosed is an electronic device including a housing including a first plate, a second plate facing away from the first plate, and a side member surrounding a space between the first plate and the second plate, a metal structure of which a part is connected to the side member; and a printed circuit board positioned between the metal structure and the second plate. The side member includes a first conductive portion, a second conductive portion extending from one end of the first conductive portion, a third conductive portion extending from the other end of the first conductive portion, a first segment formed between the first conductive portion and the second conductive portion, and a second segment formed between the first conductive portion and the third conductive portion. The first conductive portion is connected to a first ground part disposed on the printed circuit board through a first path, and is connected to a second ground part disposed on the metal structure through a second path spaced from the first path by a specific distance. In addition, various embodiments as understood from the specification may be also possible.

The abstract describes an integrated circuit package comprising a first package layer having a first package layer plane, at least one transmission line aligned with the first package layer plane and connected to at least one package terminal, an integrated circuit having at least one integrated circuit terminal, and an electrical connection aligned with the first package layer plane and configured to electrically connect the package terminals and the integrated circuit terminal.

Back drilling vias of a PCB, including: identifying a particular diameter of a particular via of multiple vias of the PCB; back drilling of the particular via with a first drill bit having a first diameter, the first diameter a first percentage greater than the particular diameter of the particular via; determining whether the first diameter of the first drill bit is a threshold percentage greater than the particular diameter of the particular via; determining that the first diameter of the first drill bit is less than the threshold percentage greater than the particular diameter of the particular via, and in response: back drilling of the particular via with a second drill bit having a second diameter, the second diameter a second percentage greater than the particular diameter of the particular via, the second diameter greater than the first diameter.