165 results about "Fan-out" patented technology

The invention relates to an optical engine and a forming method thereof, the optical engine comprises an adapter plate, an electric chip, an optical chip and a packaging substrate, the adapter plate comprises a first surface, a second surface opposite to the first surface, and a first through hole penetrating through the first surface and the second surface, the first surface of the adapter plate and the front surface of the electric chip are mounted on the optical chip and are electrically connected with the optical chip, and the second surface of the adapter plate is mounted on the packaging substrate and is electrically connected with the packaging substrate. According to the 3D fan-out type packaging optical engine integrated with the TSV adapter plate, the problems that an existing 3D fan-out type packaging optical engine is large in module size and cannot support the extremely high number of channels can be solved at the same time, and the problems that an existing 3D integrated optical engine with the TSV is high in cost and chip incoming materials are fixed can be solved at the same time.

According to the wiring substrate, the manufacturing method thereof and the electronic device, the wiring substrate comprises a substrate body, the substrate body comprises a first surface and a second surface which are oppositely arranged, the second surface comprises a binding area extending in the first direction and fan-out areas located on the two sides of the binding area in the second direction, and a plurality of via holes are formed in the fan-out areas; the first direction intersects with the second direction; the multiple signal lines are located on the side where the first surface is located, and orthographic projections of the multiple signal lines on the substrate penetrate through the binding area and the fan-out area in the second direction; the connecting lines are located on the side where the second surface is located, the connecting lines extend from the fan-out area to the binding area, and the connecting lines are coupled with the signal lines through the via holes.

The embodiment of the present invention provides a wafer-level fan-out packaging method and a wafer-level fan-out packaging structure, which relate to the field of chip packaging technology. The method prepares a carrier with a relief protrusion and directly forms a plastic package body on the carrier. After removing the carrier, a plastic package body with a relief groove is obtained. The relief groove is directly obtained by plastic packaging with a plastic packaging material, and then the chip is embedded in the relief groove, and a passivation layer covering the relief groove is formed on the surface of the plastic package body, and finally the wafer-level processes such as wiring layer and solder ball are completed. The advantages of easy plasticity and low cost of the plastic package material are fully utilized, and the mature plastic packaging shaping process is used. In combination with the relief protrusion of the carrier, the relief groove and other structures can be accurately shaped, and the process is simple and the process difficulty is low. In addition, by embedding the chip in the relief groove, the front side is rewired to fan out each signal contact outside the plastic package, thereby improving the reliability of the plastic package.

The invention relates to the field of packaged antenna arrays, and particularly discloses a fan-out type dual-polarization packaged antenna array integrated with a heterogeneous chipset. The packaging antenna array comprises three packaging bodies which are arranged from top to bottom, and a dual-polarized antenna array, a feed network and a heterogeneous chipset embedded in the packaging bodies are integrated in the packaging antenna array, so that high-density fan-out integration of the dual-polarized antenna array and the heterogeneous radio frequency front-end chipset is realized; the phased array module has lower transmission loss and higher integration level, not only can effectively reduce the size and cost of the system, but also has the characteristics of simple assembly process, high consistency, easy realization of random expansion of the array scale and the like, and can be applied to a large-scale phased array system as a standard module.

The present disclosure provides a wiring substrate and a manufacturing method therefor, and an electronic device. The wiring substrate comprises: a base substrate, comprising a first surface and a second surface arranged opposite to each other, wherein the second surface comprises a binding area extending along a first direction and fan-out areas located on two sides of the binding area in a second direction, a plurality of via holes are formed in the fan-out areas, and the first direction intersects with the second direction; a plurality of signal lines located on the side where the first surface is located, wherein the orthographic projections of the plurality of signal lines on the base substrate penetrate through the binding area and the fan-out areas along the second direction; and a plurality of connecting lines located on the side where the second surface is located, wherein the plurality of connecting lines extend from the fan-out areas to the binding area, and the plurality of connecting lines and the plurality of signal lines are coupled by means of the plurality of via holes.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

An electronic assembly component may comprise at least one fan-out device comprising a first encapsulant disposed around a memory device or function and a processor device or function, and a fan-out interconnect structure disposed over the first encapsulant and the at least one fan-out device. Input output pads may be disposed over the fan-out interconnect structure. A structural support may comprise electrical routing and structural support pads, the structural support further comprising at least one mounting site to which the at least one fan-out device is coupled. An electrical connector may be configured to electrically couple the input output pads of the at least one fan-out device to the structural support pads. A second encapsulant may be disposed over at least a portion of the at least one fan-out device and the structural support.

The invention provides a manufacturing method of a fan-out type packaging structure and the fan-out type packaging structure, the fan-out type packaging structure comprises a rewiring layer, at least one plastic packaging layer, at least one first shielding layer, at least one chip and at least one electric connecting piece, the rewiring layer comprises a grounding circuit layer, the chip and the electric connecting piece are arranged on the first surface of the rewiring layer, and the grounding circuit layer is arranged on the second surface of the rewiring layer. The electric connecting piece is positioned on the outer side of the chip and is electrically connected to the grounding circuit layer; the plastic packaging layer is arranged on the first surface of the rewiring layer and packages the electric connecting piece and the chip; the first shielding layer at least partially covers the side surface of the plastic package layer; at least part of the electric connecting piece is exposed out of the side face of the plastic packaging layer and is electrically connected to the first shielding layer, and the first shielding layer and the grounding circuit layer are electrically conducted through the electric connecting piece. The first shielding layer is connected to the grounding line layer through the electric connecting piece, so that the electric connecting piece can be utilized to realize relatively large-area surface contact with the first shielding layer and the grounding line layer respectively, the resistance among the three layers is reduced, and the shielding effect is improved.

The invention discloses a fan-out packaging integrated heat dissipation structure, and relates to the technical field of semiconductor packaging. The structure comprises at least one chip which is arranged in a mold; the rewiring layer is arranged below the chip and the molding; the solder ball is arranged below the rewiring layer; a first thermal interface layer disposed on the top of the mold; and the integrated radiator is arranged on the first thermal interface layer. According to the fan-out type package integrated heat dissipation structure provided by the invention, the integrated radiator is directly attached to the fan-out type package to enhance heat dissipation of the top passage, so that the requirements of increased power density and heat flux density on heat dissipation performance are met. Molding of the structure can protect the chip, control warping and play a role in supporting the integrated radiator.

The invention provides a circuit board assembly and an electronic device, the circuit board assembly comprises a board main body and at least one chip, the board main body comprises a first surface and a second surface which are opposite, the first surface comprises at least one chip area, each chip is arranged on the corresponding chip area, and a power pin of a core area of the chip is fanned out through a via hole in the corresponding chip area. A plurality of liquid cooling channels corresponding to the chips are arranged in the plate body, and heat generated by the chips is rapidly absorbed by cooling media filled in the liquid cooling channels. The problem that the high integration level and the heat dissipation design of the circuit board assembly related to the high-power chip and the electronic equipment are difficult to be compatible is solved, the integration level and the miniaturization of the circuit board assembly and the electronic equipment are improved, and the production cost is further reduced.

The invention belongs to the technical field of chip packaging, and particularly relates to a high-reliability and high-heat-dissipation hard fully-encapsulated fan-out packaging method. Comprising the following steps: providing a hard substrate, and etching a plurality of concave grooves in the front surface of the hard substrate; providing a plurality of functional chips; wherein the plurality of functional chips are the same chip or a plurality of different chips; correspondingly mounting the plurality of functional chips in the plurality of concave grooves through a wafer reconstruction technology to form a reconstructed wafer, and exposing the front surfaces of the plurality of functional chips; preparing a rewiring layer on the front surface of the reconstructed wafer; preparing a conductive bump on the front surface of the rewiring layer; cutting the reconstructed wafer to form a plurality of chip packaging structures; preparing packaging layers on the front surfaces and the side surfaces of the plurality of chip packaging structures so as to form a plurality of hard fully-packaged fan-out packaging structures; the reliability and the heat dissipation capability of the fan-out type packaging structure are improved.

The application belongs to the technical field of circuit board manufacturing, and particularly relates to an embedded circuit board and a preparation method thereof. The preparation method of the embedded circuit board comprises the following steps: obtaining an embedded module, manufacturing a first bonding layer on at least part of the surface of the embedded module; placing the embedded module in a containing groove formed by communication of the grooves, and pressing the laminated plate structure to embed the embedded module in the containing groove; pressing a second build-up layer to fan out signals of the embedded module to the first build-up layer; forming an insulating layer and a connecting layer on the second build-up layer to obtain the embedded circuit board. The first bonding layer on the surface of the embedded module has high bonding force and stress buffering effect with the embedded module, an SIC chip and resin, and can be used as an intermediate buffering layer to connect the embedded module and a PP layer, thereby effectively reducing the problem of delamination due to insufficient bonding force.

The present invention relates to the field of packaged antenna arrays, and specifically discloses a fan-out type dual-polarized packaged antenna array integrating a heterogeneous chipset. The packaged antenna array includes three packages arranged from top to bottom, internally integrating a dual-polarized antenna array, a feeding network, and a heterogeneous chipset embedded inside the packages. The present invention realizes the high-density fan-out integration of the dual-polarized antenna array and the heterogeneous radio frequency front-end chipset, has lower transmission loss and higher integration, can not only effectively reduce the system volume and cost, but also has the characteristics of simple assembly process, high consistency, and easy realization of arbitrary expansion of the array scale, and can be applied as a standard module to large-scale phased array systems.

Systems and techniques that facilitate signal-delivery systems for cryogenic refrigerators are provided. In an embodiment, a structure can comprise a plurality of cables between a lower interconnect assembly and a fanout assembly, wherein the fanout assembly is structured such that each cable of the plurality of cables fans out radially from an inlet to an edge of a vacuum tight casing.

A vertical line card (VLC) system is disclosed. In one aspect, a VLC system includes a vertically-oriented printed circuit board (PCB), a vertically-oriented integrated circuit (IC) mounted to the PCB, and a cage assembly having cages arranged in a splayed layout so that the cages angularly fan out with respect to the IC.

The utility model discloses a fan-out type wafer level packaging unit. The fan-out type wafer level packaging unit comprises a carrier plate, at least one bare chip, a first dielectric layer, at least one conductive column, a second dielectric layer, a plurality of first conductive connection lines, a first outer protective layer, a third dielectric layer, a plurality of second conductive connection lines and a second outer protective layer, wherein the die can be electrically connected to the outside by at least one first bonding pad around a chip region on the second side of the die; wherein the die can be electrically connected to the outside through a second bonding pad in at least one opening of the second outer protective layer; wherein each first conductive connection line and each second conductive connection line are manufactured by a technology of filling metal paste into the grooves and then grinding and forming the conductive connection lines, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when each conductive connection line is manufactured by the existing fan-out packaging technology are solved.

Embodiments of the present invention provide a fan-out package structure and a preparation method thereof, relating to the technical field of semiconductor packaging. A main chip is disposed in a first plastic package body. Meanwhile, a first groove is formed on a first surface of the first plastic package body, a first mounted chip is mounted in the first groove, and a first conductive pillar is disposed in the first plastic package body to achieve electrical connection of the main chip. Compared with the conventional technology, in the present invention, the main chip and the first mounted chip are stacked and embedded in the first plastic package body, and the first mounted chip is stacked above the main chip in space, so that the package size can be greatly reduced compared with the flat fan-out structure, the package area is reduced, which is beneficial to the miniaturization of products. At the same time, the main chip is connected to the first wiring combination layer through the first conductive pillar, which can greatly reduce the transmission rate and make the stacking performance of its fan-out products more excellent.

The utility model discloses a module for bonding a fan-out type wafer level packaging unit on an electronic component through wire bonding. The module comprises a carrier plate, a first bare chip, a first dielectric layer, a plurality of first conducting circuits, a second dielectric layer, a plurality of second conducting circuits, a second bare chip, an electronic component, at least one first bonding wire, at least two second bonding wires and at least one third bonding wire, wherein each second conducting circuit is formed by grinding metal paste filled in each second groove of the second dielectric layer, and each second conducting circuit forms a welding pad in each second groove; wherein the first bare crystal can be electrically connected with the outside through the welding pads around the chip area on the second surface of the first bare crystal, so that the problems that the fan-out packaging technology in the existing module is easy to generate higher manufacturing cost and is not beneficial to environmental protection when manufacturing the conducting circuits are effectively solved.

The utility model discloses a fan-out type wafer level packaging unit, which comprises a carrier plate, a bare crystal, a first dielectric layer, a second dielectric layer, a plurality of conducting lines and an outer protective layer, the bare crystal is provided with a first surface and a second surface opposite to the first surface, the first surface is fixedly arranged on the carrier plate, the second surface is provided with a plurality of crystal pads, a vertical chip area of the second surface is defined as a chip area, and the chip area is provided with a plurality of chip pads. Each conductive connection line is composed of metal paste filled in a plurality of first grooves of the first dielectric layer and a plurality of second grooves of the second dielectric layer, one end of each conductive connection line is electrically connected with a plurality of crystal pads of a bare crystal, and the other end of each conductive connection line forms a welding pad in a plurality of openings of the outer protective layer and is exposed. Wherein at least one bonding pad is located around the chip area of the second surface of the die; wherein the bare crystal is electrically connected with the outside through the crystal pads, the conducting circuits and the welding pads, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when the conducting circuits are manufactured by the existing fan-out packaging technology are effectively solved.

The present invention relates to a fan-out system package and method for integrated MIM capacitors. It includes a base chip, a functional chipset, and a lead-out connection unit. The functional chips in the functional chipset are interconnected with the base chip and are plastic-sealed on the base chip through a plastic sealing layer. A MIM capacitor group is arranged in the plastic sealing layer, and the MIM capacitor group includes a plurality of MIM capacitors. The MIM capacitor includes a first capacitor plate and a second capacitor plate corresponding to the first capacitor plate. The first capacitor plate and the second capacitor plate are both buried in the plastic sealing layer. The first capacitor plate and the second capacitor plate are spaced by the plastic sealing layer, and the first capacitor plate and the second capacitor plate are electrically connected to the corresponding substrate capacitor connection pad unit on the base chip. The lead-out connection unit is used to lead out the package formed by the base chip, the functional chipset, and the MIM capacitor group. The present invention effectively realizes the integration of a large capacitor system, is compatible with existing processes, reduces packaging costs, and is safe and reliable.

A semiconductor device has a semiconductor assembly and an antenna substrate formed separate from the semiconductor assembly and mounted to the semiconductor assembly. A bonding material is disposed between the antenna substrate and semiconductor assembly. An encapsulant is deposited over the antenna substate. The encapsulant may be planar or have encapsulant bumps. The bonding material extends over a side surface of the antenna substrate. The antenna substrate has a first antenna substrate and a second antenna substrate disposed over the semiconductor assembly. The first antenna substrate is offset with respect to the second antenna substrate in the horizontal and / or vertical directions. The antenna substrate can fan out from the semiconductor assembly. The semiconductor assembly can have multiple layers of core material with different coefficient of thermal expansions. A heat sink or shielding layer can be formed over the antenna substrate and semiconductor assembly.

A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

The embodiment of the invention discloses a chip interposer wiring method and device based on integer linear programming. A specific embodiment of the method comprises the steps that a real coordinate set of salient points of a current chip is determined according to physical information of the current chip, and the physical information of the current chip comprises center coordinate information of the current chip, current rotation angle information and current rotation center coordinate information; according to the current chip salient point real coordinate set, target salient point determination is carried out on each key salient point in the key salient point set to generate a target salient point, and a target salient point set is obtained; according to the target salient point set, generating a fan-out edge set corresponding to the physical information of the current chip and a candidate edge set of the target salient point; generating a fan-out edge distribution salient point set according to the candidate edge set and the fan-out edge set; and performing inter-chip wiring path distribution on the fan-out edge wiring to generate an inter-chip fan-out edge wiring distribution path. According to the embodiment of the invention, the time required for completing the wiring of the interposer is reduced, and the wiring quality of multi-chip interconnection is improved.

The application provides a chip and an electronic device, the chip comprises a Die, a substrate structure and a Ball from top to bottom, the substrate structure comprises a top layer substrate, a middle layer substrate and a bottom layer substrate which are stacked with each other, the top layer substrate is connected with the Die, and the bottom layer substrate is connected with the Ball; a communication signal of the chip is fanned out from the middle layer substrate and connected to the bottom layer substrate through a via hole downwardly. By adopting the scheme, the wiring space can be increased without increasing the substrate area and the number of layers, the wiring space of a single layer substrate is improved, the number of layers of the substrate is reduced, and the substrate cost and the chip cost are significantly saved.

The invention discloses a fan-out type wafer level packaging unit which comprises a carrier plate, at least one bare chip, a first dielectric layer, at least one conductive column, a second dielectric layer, a plurality of first conductive connection lines, a first outer protection layer, a third dielectric layer, a plurality of second conductive connection lines and a second outer protection layer. Wherein the die can be electrically connected to the outside by at least one first bonding pad around a chip region on the second side of the die; wherein the die can be electrically connected to the outside through a second bonding pad in at least one opening of the second outer protective layer; wherein each first conductive connection line and each second conductive connection line are manufactured by a technology of filling metal paste into the grooves and then grinding and forming the conductive connection lines, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when each conductive connection line is manufactured by the existing fan-out packaging technology are solved.

The present invention relates to the fields of computer application technology and network coding, and more particularly to an IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array. The architecture comprises a PE module, a Weight FIFO module, an encoding and decoding module, and a driver module. L PE modules are arranged horizontally to form a one-dimensional systolic array. The one-dimensional systolic array outputs R redundant packets at intervals of K*L cycles. The PE modules include registers, accumulators, and XOR units. The calculation results and valid signals of the previous PE module are transmitted to the next PE module for calculation after passing through the registers. The Weight FIFO module is used to temporarily store coefficient matrix information and periodically fan out the input ports of all PE modules corresponding to the one-dimensional systolic array. The present invention implements cyclic shift matrix multiplication operations through the systolic array, reducing computational complexity while ensuring a fixed encoding and decoding delay, and improving hardware scalability, throughput, and energy efficiency.

The application discloses a fan-out packaging structure and method of multi-component devices, which comprises at least two components with different thicknesses. The component with smaller thickness is firstarily molded, then the metal bumps are made on the surface of each component, and then each component is attached to the substrate in an upward manner and secondarily molded. The re-routed layer electrically connected with the metal bumps is made. The method can not only be compatible with the thickness difference of the two components, but also effectively overcome the difficulty caused by the uneven wafer surface due to the component bump in the subsequent photoetching step and chemical mechanical polishing process.

Provided are a fan-out package structure and a manufacturing method thereof. The fan-out package structure provided in the embodiments of the present disclosure, and the fan-out package structure obtained by the manufacturing method provided in the embodiments of the present disclosure have an inter-chip fine interconnection line between functional surfaces of chips, so that fine interconnection pin pads of adjacent chips form electrical interconnection.

A system includes a transmitter and a processor. The processor is configured to receive true time at a terminal; acquire a first communication link with a satellite using a first protocol; determine a second communication link with the satellite using a second protocol; and provide the true time to the satellite in a constellation using the transmitter.

The present application provides a display substrate, a display device, and a method for manufacturing a display substrate. The display substrate includes a display area and a non-display area located around the display area, and the display area includes a fan-out area; the display substrate includes a data line arranged in the display area and a fan-out line arranged in the fan-out area; the fan-out line is electrically connected to the data line, and the fan-out line and the data line are located in different layers. The display device shown includes the display substrate. The preparation method shown includes forming a data line in the display area; forming a fan-out line in a layer different from the data line, and the fan-out line is located in the fan-out area; and electrically connecting the fan-out line to the data line.