92 results about "Fan-out" patented technology

An electronic assembly component may comprise at least one fan-out device comprising a first encapsulant disposed around a memory device or function and a processor device or function, and a fan-out interconnect structure disposed over the first encapsulant and the at least one fan-out device. Input output pads may be disposed over the fan-out interconnect structure. A structural support may comprise electrical routing and structural support pads, the structural support further comprising at least one mounting site to which the at least one fan-out device is coupled. An electrical connector may be configured to electrically couple the input output pads of the at least one fan-out device to the structural support pads. A second encapsulant may be disposed over at least a portion of the at least one fan-out device and the structural support.

The application belongs to the technical field of circuit board manufacturing, and particularly relates to an embedded circuit board and a preparation method thereof. The preparation method of the embedded circuit board comprises the following steps: obtaining an embedded module, manufacturing a first bonding layer on at least part of the surface of the embedded module; placing the embedded module in a containing groove formed by communication of the grooves, and pressing the laminated plate structure to embed the embedded module in the containing groove; pressing a second build-up layer to fan out signals of the embedded module to the first build-up layer; forming an insulating layer and a connecting layer on the second build-up layer to obtain the embedded circuit board. The first bonding layer on the surface of the embedded module has high bonding force and stress buffering effect with the embedded module, an SIC chip and resin, and can be used as an intermediate buffering layer to connect the embedded module and a PP layer, thereby effectively reducing the problem of delamination due to insufficient bonding force.

Systems and techniques that facilitate signal-delivery systems for cryogenic refrigerators are provided. In an embodiment, a structure can comprise a plurality of cables between a lower interconnect assembly and a fanout assembly, wherein the fanout assembly is structured such that each cable of the plurality of cables fans out radially from an inlet to an edge of a vacuum tight casing.

A vertical line card (VLC) system is disclosed. In one aspect, a VLC system includes a vertically-oriented printed circuit board (PCB), a vertically-oriented integrated circuit (IC) mounted to the PCB, and a cage assembly having cages arranged in a splayed layout so that the cages angularly fan out with respect to the IC.

The utility model discloses a fan-out type wafer level packaging unit. The fan-out type wafer level packaging unit comprises a carrier plate, at least one bare chip, a first dielectric layer, at least one conductive column, a second dielectric layer, a plurality of first conductive connection lines, a first outer protective layer, a third dielectric layer, a plurality of second conductive connection lines and a second outer protective layer, wherein the die can be electrically connected to the outside by at least one first bonding pad around a chip region on the second side of the die; wherein the die can be electrically connected to the outside through a second bonding pad in at least one opening of the second outer protective layer; wherein each first conductive connection line and each second conductive connection line are manufactured by a technology of filling metal paste into the grooves and then grinding and forming the conductive connection lines, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when each conductive connection line is manufactured by the existing fan-out packaging technology are solved.

A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

The application provides a chip and an electronic device, the chip comprises a Die, a substrate structure and a Ball from top to bottom, the substrate structure comprises a top layer substrate, a middle layer substrate and a bottom layer substrate which are stacked with each other, the top layer substrate is connected with the Die, and the bottom layer substrate is connected with the Ball; a communication signal of the chip is fanned out from the middle layer substrate and connected to the bottom layer substrate through a via hole downwardly. By adopting the scheme, the wiring space can be increased without increasing the substrate area and the number of layers, the wiring space of a single layer substrate is improved, the number of layers of the substrate is reduced, and the substrate cost and the chip cost are significantly saved.

The invention discloses a fan-out type wafer level packaging unit which comprises a carrier plate, at least one bare chip, a first dielectric layer, at least one conductive column, a second dielectric layer, a plurality of first conductive connection lines, a first outer protection layer, a third dielectric layer, a plurality of second conductive connection lines and a second outer protection layer. Wherein the die can be electrically connected to the outside by at least one first bonding pad around a chip region on the second side of the die; wherein the die can be electrically connected to the outside through a second bonding pad in at least one opening of the second outer protective layer; wherein each first conductive connection line and each second conductive connection line are manufactured by a technology of filling metal paste into the grooves and then grinding and forming the conductive connection lines, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when each conductive connection line is manufactured by the existing fan-out packaging technology are solved.

The present invention relates to the fields of computer application technology and network coding, and more particularly to an IP core architecture for implementing triple-redundant MDS array encoding and decoding based on a systolic array. The architecture comprises a PE module, a Weight FIFO module, an encoding and decoding module, and a driver module. L PE modules are arranged horizontally to form a one-dimensional systolic array. The one-dimensional systolic array outputs R redundant packets at intervals of K*L cycles. The PE modules include registers, accumulators, and XOR units. The calculation results and valid signals of the previous PE module are transmitted to the next PE module for calculation after passing through the registers. The Weight FIFO module is used to temporarily store coefficient matrix information and periodically fan out the input ports of all PE modules corresponding to the one-dimensional systolic array. The present invention implements cyclic shift matrix multiplication operations through the systolic array, reducing computational complexity while ensuring a fixed encoding and decoding delay, and improving hardware scalability, throughput, and energy efficiency.

The application discloses a fan-out packaging structure and method of multi-component devices, which comprises at least two components with different thicknesses. The component with smaller thickness is firstarily molded, then the metal bumps are made on the surface of each component, and then each component is attached to the substrate in an upward manner and secondarily molded. The re-routed layer electrically connected with the metal bumps is made. The method can not only be compatible with the thickness difference of the two components, but also effectively overcome the difficulty caused by the uneven wafer surface due to the component bump in the subsequent photoetching step and chemical mechanical polishing process.

A system includes a transmitter and a processor. The processor is configured to receive true time at a terminal; acquire a first communication link with a satellite using a first protocol; determine a second communication link with the satellite using a second protocol; and provide the true time to the satellite in a constellation using the transmitter.

The invention discloses a fan-out type wafer level packaging unit which comprises a carrier plate, a first dielectric layer, at least one antenna, at least one bare chip, a second dielectric layer, at least one conductive column, a plurality of first conductive connection lines, a third dielectric layer, a plurality of second conductive connection lines and an outer protection layer. Wherein each first conductive connection line and each second conductive connection line are formed by a technology of filling metal paste into the groove and then grinding and forming the conductive connection lines; wherein each die is electrically connected with each antenna; wherein the bare crystal can be electrically connected with the outside through each welding pad around the chip area on the second surface of the bare crystal, so that the fan-out type wafer level packaging unit is formed, and the problems that high manufacturing cost is easily generated and environmental protection is not facilitated when each conducting circuit is manufactured by the existing fan-out type packaging technology are solved.

The embodiment of the invention provides a circuit board and a manufacturing method thereof, and the circuit board comprises a first core board, a second core board and a third core board which are sequentially stacked, the second core board is provided with an installation groove which penetrates in the thickness direction, and one side, facing the second core board, of the third core board is provided with a first positioning hole; the embedded device is arranged in the mounting groove, the embedded device comprises a positioning protrusion, and at least part of the positioning protrusion is located in the first positioning hole so as to limit movement of the embedded device. According to the circuit board provided by the embodiment of the invention, through the cooperation of the first positioning hole and the positioning bulge, the slippage of the embedded device in the circuit board pressing process is reduced, so that the position deviation of the embedded device and the embedded device before pressing is reduced, the position deviation between the connecting channel and the chip is favorably controlled within an allowable range during the subsequent processing of the connecting channel, and the reliability of the circuit board is improved. Therefore, the precision and stability of connection with the via hole during subsequent chip signal fan-out are improved.

This invention discloses a deterministic delay and arbitrary range delay compensation adjustment architecture between multiple DA channels. In this architecture, each DAC consists of a set of ADC_CLK and SYSREF, and each FPGA consists of a set of REF_CLK and SYSREF. This architecture is used to design the clock block diagram and the deterministic delay synchronization output rate of multiple DACs. The frequency multiplier multiplies the reference input to output DAC_CLK and REF_CLK. DAC_CLK is set according to the DAC operating frequency, and REF_CLK is determined according to the operating range of the frequency divider. In this system, REF_CLK = DAC_CLK / N (N<=40). The frequency divider receives REF_CLK1 and divides it to output the required SYSREF. The clock fan-out fans out DAC_CLK into N DAC_CLKs according to the number of DACs. Through reasonable clock arrangement, only the clock fan-out chip can be used when the number of DACs is increased, ensuring that the output time remains stable after multiple power-on cycles while reducing hardware costs.

The invention discloses a fan-out type packaging structure and a manufacturing method, and the method comprises the steps: 1, preparing a carrier plate (1), planting copper needles (4) at the two ends of the upper part of the carrier plate (1), pasting a first wafer (2) in the middle of the carrier plate (1), and carrying out the pre-grooving of the upper part of the first wafer (2) before pasting; and 2, mounting a second wafer (3) in a groove above the first wafer (2). The invention belongs to the field of semiconductor packaging, and particularly relates to a fan-out type packaging structure and a manufacturing method. According to the invention, another one or more crystal grains are embedded in the back surface of the wafer, and a fan-out structure of circuit layer wiring is remade, so that high-density and wafer-embedded setting is realized.

A system to integrate a fan-out package including a first semiconductor die (120) with a second semiconductor die (110). In some embodiments, the fan-out package includes a first semiconductor die (120), a molding compound (305) covering the first semiconductor die on at least two sides, and electrical contacts on a lower surface of the first semiconductor die. The fan-out package can have a notch (315) along a portion of a lower edge of the fan-out package.

The application discloses a fan-out packaging structure for inhibiting chip offset and a preparation method thereof, and belongs to the technical field of semiconductor packaging. The packaging structure comprises a rewiring dielectric layer, a chip and a molding sealing layer. An array limiting groove is arranged on the surface of the dielectric layer. The active surface of the chip is downwardly embedded in the groove and is coplanar with the bottom surface of the dielectric layer. The preparation method comprises the following steps: preparing the rewiring dielectric layer on a temporary carrier, forming the limiting groove through photolithography, pre-baking the dielectric layer after attaching the chip, molding the sealing layer, and directly completing rewiring, ball planting and cutting after stripping the temporary carrier. The application does not need to sacrifice the cofferdam and does not have interface residual glue. The chip offset can be controlled within ±2μm. The limiting process and the passivation process are combined, the process is simplified, the cost is reduced, and the packaging yield and reliability are effectively improved.

An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies.

The application provides a heat sink and a server, the heat sink comprises: a copper sheet, the copper sheet is arranged on the upper part of a CPU and closely adheres to the CPU; a first temperature sensor, the first temperature sensor is arranged on the upper part of the copper sheet and is configured to measure the temperature of the CPU; heat dissipation fins, the heat dissipation fins are vertically arranged on the upper part of the copper sheet, the bottom of the heat dissipation fins closely adheres to the copper sheet, and the heat dissipation fins are arranged at intervals; a copper pipe, the copper pipe is configured in a U shape, the bottom of the copper pipe is in contact with the copper sheet, the copper pipe is arranged perpendicularly to the surface of the heat dissipation fins and passes through the heat dissipation fins through a preset hole on the heat dissipation fins; and a heat dissipation part, the heat dissipation part comprises a fan, the fan is arranged on the upper part of the heat dissipation fins, the fan comprises a transmission structure, the transmission structure is fixedly connected with the copper pipe, and the heat dissipation part is configured to slide the fan out and start the fan to cool the server based on the temperature measured by the first temperature sensor. Through the use of the scheme of the application, the heat dissipation efficiency of the server can be improved, the power consumption of the system can be reduced, the service life of the CPU can be improved, and the working efficiency of the CPU can be ensured.

The invention provides a packaging structure and a manufacturing method thereof. Specifically, on the basis of a substrate on which a first chip is packaged, an uncured viscous dielectric layer is adopted to bond a second chip and stack the chips layer by layer, and the stacked chips are fanned out and conducted to the substrate in the stacking process, so that an ultrathin chip substrate is replaced and solder ball welding is avoided in such a manner, and the cost is reduced. The manufacturing difficulty and the thickness of the whole product are reduced, and the electrical performance is improved.

The embodiment of the invention discloses a PCB differential line wiring method, a design method and a PCB, and relates to the technical field of PCBs, through different-layer wiring of differential lines, the wiring space is saved, the wiring pressure of a BGA area is reduced, rapid coupling of the differential lines is carried out in a vertical coupling mode, and the coupling effect of the differential lines is higher. The embodiment of the invention provides a PCB differential line wiring method, a PCB at least comprises a first differential line, and the method comprises the steps: carrying out the fan-out wiring of the first differential line in a middle layer of the PCB, and carrying out the fan-out curved wiring of the first differential line around a wiring bonding pad in a spherical grid array region based on a principle that the first differential line does not enter a bonding pad distribution forbidding region.

The invention relates to the technical field of chip packaging, in particular to a fan-out semiconductor packaging structure with an electromagnetic shielding layer. Comprising a chip, the surface of one end of the chip is connected with a rewiring layer, the other surfaces of the chip are all covered with electromagnetic shielding layers, plastic packaging layers are arranged on the outer sides of the electromagnetic shielding layers, and the other side of the rewiring layer is connected with salient points through UBM layers. Compared with the prior art, electromagnetic mutual interference among the chips is realized by introducing a sputtering electromagnetic shielding layer in the fan-out packaging process, the structure is simple, the process cost is low, the electromagnetic shielding layer is formed on the surface of the chip, and the packaging thickness is reduced.

A method of making a semiconductor assembly may include mounting a plurality of components to one or more intermediate carriers and disposing the one or more intermediate carriers over a temporary carrier. The intermediate carriers may comprise one or more conductive features and coupling the components to the conductive features. The method may further include disposing an encapsulant over the one or more intermediate carriers and over the plurality of components mounted to the temporary carrier to form a reconstituted panel. The encapsulant may be disposed around four side surfaces and over a front surface of each of the plurality of components and removing a portion of the encapsulant to form a planar surface above the front surface of the plurality of components and removing the temporary carrier.

A fan-out package on package (PoP) assembly in which a second chip is adhered to an inactive side of a first chip. The active side of the first chip embedded in the first package material may be electrically coupled through one or more redistribution layers that fan out to package interconnects on the first side of the PoP. A second chip may be adhered to the non-active side of the first chip with a second encapsulation material. The active side of the second chip may be electrically coupled to the package interconnect through a via structure extending through the first package material. A second interconnect between the second chip or a package thereof may contact the via structure. Using the second packaging material as an adhesive may improve positional stability of the second chip to facilitate wafer level assembly techniques.

The present application discloses a method for manufacturing a printed circuit board, a slot and a connector, and relates to the field of electronic technology. The printed circuit board comprises: a first solder pad, a second solder pad, a first layer board, a signal layer board group and a second layer board stacked in sequence from bottom to top; the side of the first layer board is flush with the side of the second layer board; the signal layer board group comprises two adjacent layers of signal layer boards, the signal layer board has an extension portion, the extension portion protrudes from the side of the first layer board, and the extension portion is provided with a first solder pad; the surface of the first layer board and / or the surface of the second layer board is provided with a second solder pad, the first solder pad and the second solder pad form an electrical connection, and the first solder pad provided on a group of signal layer board groups is used to transmit a pair of differential signals. The implementation of the embodiment of the present application can transfer high-speed differential signals from the surface layer of the printed circuit board to the signal layer board on the inner layer of the printed circuit board, and then fan out to the gold finger, thereby improving the signal transmission quality and reducing the board area.

The present disclosure relates to a silicon-based fan out package structure including embedded manifold type microchannels, which includes: a chip, which includes a substrate and embedded microchannels located on a back of the substrate; a silicon-based adapter plate, which includes a groove for burying the chip, a manifold channel located below the groove and communicated with the groove, a liquid inlet and a liquid outlet; a low temperature sealing layer for sealing the embedded microchannels with the manifold channel, the low temperature sealing layer being located between the chip and the silicon-based adapter plate; and a rewiring layer at a top of the chip. The present disclosure also relates to a preparation method for a silicon-based fan out package structure including embedded manifold type microchannels.

This invention discloses a fan-out package with a three-dimensional electromagnetic shielding structure and its fabrication method. The fan-out package includes a molding compound covering a central metal sheet; a first chip and a second chip are respectively disposed above and below the central metal sheet; at least two rows of inner copper pillars and at least two rows of outer copper pillars penetrate the molding compound; a first superwiring layer is disposed on the metal bumps of the first chip and the outer copper pillars, and a first insulating layer is coated on the first superwiring layer, forming a first continuous shielding layer on the surface of the first insulating layer; a second superwiring layer is disposed on the metal bumps of the second chip and the outer copper pillars, forming a back pad; the bottom of the inner copper pillars is led out to the surface through the second superwiring layer, forming an independent ground pad; solder balls are disposed on the back pad and the ground pad; this invention can simultaneously construct a three-dimensional, continuous electromagnetic shielding structure in the fan-out packaging process, achieving all-round shielding of stacked chips, while maintaining the miniaturization and high integration of the package.

The invention discloses a preparation method of a fan-out type packaging structure, and belongs to the technical field of semiconductor packaging. After the release layer is formed on the substrate, the multi-layer structure comprising at least three insulating layers and the rewiring layer is constructed, and the first insulating layer in contact with the release layer adopts silicon dioxide and / or silicon nitride as a non-photosensitive dielectric material. The non-photosensitive dielectric material has high rigidity and low thermal expansion coefficient, provides rigid support for the whole panel, effectively inhibits process warping, and ensures the upper layer patterning precision; meanwhile, an interface formed by the carrier plate and the release layer is easy to separate completely, so that the structural damage risk during release of the carrier plate is reduced; and in combination with a rigid-flexible structure formed by the photosensitive polyimide on the upper layer, the thermal stress can be effectively managed, the reliability of interlayer combination is enhanced, and the service life of the product is prolonged. The fan-out type packaging structure with high yield and high reliability is manufactured through the steps of chip mounting, panel-level plastic packaging, substrate removal, external terminal formation and the like.

A fan-out electronic package and packaging method thereof include a wire redistribution unit, an isolation structure, at least one functional chip, a mask, a first pattern structure, a sealing structure, and a second pattern structure. The isolation structure is disposed within the wire redistribution unit, the functional chip is disposed within the isolation structure, the mask is disposed within the isolation structure and covers the functional chip, the first pattern structure is formed within the isolation structure, the sealing structure cooperates with the wire redistribution unit to encapsulate the isolation structure, the at least one functional chip, the mask, and the first pattern structure, and the second pattern structure is formed within the sealing structure and, together with the first pattern structure, forms an antenna. The isolation structure and mask provide shielding, while the application of the first pattern structure simplifies the manufacturing process. The wire redistribution unit serves as an electrical connection interface with external circuits, achieving circuit packaging and fan-out integrated layout.

A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.