51 results about "Fan-out" patented technology

The application belongs to the technical field of circuit board manufacturing, and particularly relates to an embedded circuit board and a preparation method thereof. The preparation method of the embedded circuit board comprises the following steps: obtaining an embedded module, manufacturing a first bonding layer on at least part of the surface of the embedded module; placing the embedded module in a containing groove formed by communication of the grooves, and pressing the laminated plate structure to embed the embedded module in the containing groove; pressing a second build-up layer to fan out signals of the embedded module to the first build-up layer; forming an insulating layer and a connecting layer on the second build-up layer to obtain the embedded circuit board. The first bonding layer on the surface of the embedded module has high bonding force and stress buffering effect with the embedded module, an SIC chip and resin, and can be used as an intermediate buffering layer to connect the embedded module and a PP layer, thereby effectively reducing the problem of delamination due to insufficient bonding force.

Systems and techniques that facilitate signal-delivery systems for cryogenic refrigerators are provided. In an embodiment, a structure can comprise a plurality of cables between a lower interconnect assembly and a fanout assembly, wherein the fanout assembly is structured such that each cable of the plurality of cables fans out radially from an inlet to an edge of a vacuum tight casing.

A vertical line card (VLC) system is disclosed. In one aspect, a VLC system includes a vertically-oriented printed circuit board (PCB), a vertically-oriented integrated circuit (IC) mounted to the PCB, and a cage assembly having cages arranged in a splayed layout so that the cages angularly fan out with respect to the IC.

A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

The invention discloses a fan-out type wafer level packaging unit which comprises a carrier plate, at least one bare chip, a first dielectric layer, at least one conductive column, a second dielectric layer, a plurality of first conductive connection lines, a first outer protection layer, a third dielectric layer, a plurality of second conductive connection lines and a second outer protection layer. Wherein the die can be electrically connected to the outside by at least one first bonding pad around a chip region on the second side of the die; wherein the die can be electrically connected to the outside through a second bonding pad in at least one opening of the second outer protective layer; wherein each first conductive connection line and each second conductive connection line are manufactured by a technology of filling metal paste into the grooves and then grinding and forming the conductive connection lines, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when each conductive connection line is manufactured by the existing fan-out packaging technology are solved.

A system includes a transmitter and a processor. The processor is configured to receive true time at a terminal; acquire a first communication link with a satellite using a first protocol; determine a second communication link with the satellite using a second protocol; and provide the true time to the satellite in a constellation using the transmitter.

The invention discloses a fan-out type wafer level packaging unit which comprises a carrier plate, a first dielectric layer, at least one antenna, at least one bare chip, a second dielectric layer, at least one conductive column, a plurality of first conductive connection lines, a third dielectric layer, a plurality of second conductive connection lines and an outer protection layer. Wherein each first conductive connection line and each second conductive connection line are formed by a technology of filling metal paste into the groove and then grinding and forming the conductive connection lines; wherein each die is electrically connected with each antenna; wherein the bare crystal can be electrically connected with the outside through each welding pad around the chip area on the second surface of the bare crystal, so that the fan-out type wafer level packaging unit is formed, and the problems that high manufacturing cost is easily generated and environmental protection is not facilitated when each conducting circuit is manufactured by the existing fan-out type packaging technology are solved.

The invention discloses a fan-out type packaging structure and a manufacturing method, and the method comprises the steps: 1, preparing a carrier plate (1), planting copper needles (4) at the two ends of the upper part of the carrier plate (1), pasting a first wafer (2) in the middle of the carrier plate (1), and carrying out the pre-grooving of the upper part of the first wafer (2) before pasting; and 2, mounting a second wafer (3) in a groove above the first wafer (2). The invention belongs to the field of semiconductor packaging, and particularly relates to a fan-out type packaging structure and a manufacturing method. According to the invention, another one or more crystal grains are embedded in the back surface of the wafer, and a fan-out structure of circuit layer wiring is remade, so that high-density and wafer-embedded setting is realized.

A system to integrate a fan-out package including a first semiconductor die (120) with a second semiconductor die (110). In some embodiments, the fan-out package includes a first semiconductor die (120), a molding compound (305) covering the first semiconductor die on at least two sides, and electrical contacts on a lower surface of the first semiconductor die. The fan-out package can have a notch (315) along a portion of a lower edge of the fan-out package.

The application discloses a fan-out packaging structure for inhibiting chip offset and a preparation method thereof, and belongs to the technical field of semiconductor packaging. The packaging structure comprises a rewiring dielectric layer, a chip and a molding sealing layer. An array limiting groove is arranged on the surface of the dielectric layer. The active surface of the chip is downwardly embedded in the groove and is coplanar with the bottom surface of the dielectric layer. The preparation method comprises the following steps: preparing the rewiring dielectric layer on a temporary carrier, forming the limiting groove through photolithography, pre-baking the dielectric layer after attaching the chip, molding the sealing layer, and directly completing rewiring, ball planting and cutting after stripping the temporary carrier. The application does not need to sacrifice the cofferdam and does not have interface residual glue. The chip offset can be controlled within ±2μm. The limiting process and the passivation process are combined, the process is simplified, the cost is reduced, and the packaging yield and reliability are effectively improved.

The application provides a heat sink and a server, the heat sink comprises: a copper sheet, the copper sheet is arranged on the upper part of a CPU and closely adheres to the CPU; a first temperature sensor, the first temperature sensor is arranged on the upper part of the copper sheet and is configured to measure the temperature of the CPU; heat dissipation fins, the heat dissipation fins are vertically arranged on the upper part of the copper sheet, the bottom of the heat dissipation fins closely adheres to the copper sheet, and the heat dissipation fins are arranged at intervals; a copper pipe, the copper pipe is configured in a U shape, the bottom of the copper pipe is in contact with the copper sheet, the copper pipe is arranged perpendicularly to the surface of the heat dissipation fins and passes through the heat dissipation fins through a preset hole on the heat dissipation fins; and a heat dissipation part, the heat dissipation part comprises a fan, the fan is arranged on the upper part of the heat dissipation fins, the fan comprises a transmission structure, the transmission structure is fixedly connected with the copper pipe, and the heat dissipation part is configured to slide the fan out and start the fan to cool the server based on the temperature measured by the first temperature sensor. Through the use of the scheme of the application, the heat dissipation efficiency of the server can be improved, the power consumption of the system can be reduced, the service life of the CPU can be improved, and the working efficiency of the CPU can be ensured.

The invention provides a packaging structure and a manufacturing method thereof. Specifically, on the basis of a substrate on which a first chip is packaged, an uncured viscous dielectric layer is adopted to bond a second chip and stack the chips layer by layer, and the stacked chips are fanned out and conducted to the substrate in the stacking process, so that an ultrathin chip substrate is replaced and solder ball welding is avoided in such a manner, and the cost is reduced. The manufacturing difficulty and the thickness of the whole product are reduced, and the electrical performance is improved.

The embodiment of the invention discloses a PCB differential line wiring method, a design method and a PCB, and relates to the technical field of PCBs, through different-layer wiring of differential lines, the wiring space is saved, the wiring pressure of a BGA area is reduced, rapid coupling of the differential lines is carried out in a vertical coupling mode, and the coupling effect of the differential lines is higher. The embodiment of the invention provides a PCB differential line wiring method, a PCB at least comprises a first differential line, and the method comprises the steps: carrying out the fan-out wiring of the first differential line in a middle layer of the PCB, and carrying out the fan-out curved wiring of the first differential line around a wiring bonding pad in a spherical grid array region based on a principle that the first differential line does not enter a bonding pad distribution forbidding region.

A method of making a semiconductor assembly may include mounting a plurality of components to one or more intermediate carriers and disposing the one or more intermediate carriers over a temporary carrier. The intermediate carriers may comprise one or more conductive features and coupling the components to the conductive features. The method may further include disposing an encapsulant over the one or more intermediate carriers and over the plurality of components mounted to the temporary carrier to form a reconstituted panel. The encapsulant may be disposed around four side surfaces and over a front surface of each of the plurality of components and removing a portion of the encapsulant to form a planar surface above the front surface of the plurality of components and removing the temporary carrier.

A fan-out package on package (PoP) assembly in which a second chip is adhered to an inactive side of a first chip. The active side of the first chip embedded in the first package material may be electrically coupled through one or more redistribution layers that fan out to package interconnects on the first side of the PoP. A second chip may be adhered to the non-active side of the first chip with a second encapsulation material. The active side of the second chip may be electrically coupled to the package interconnect through a via structure extending through the first package material. A second interconnect between the second chip or a package thereof may contact the via structure. Using the second packaging material as an adhesive may improve positional stability of the second chip to facilitate wafer level assembly techniques.

This invention discloses a fan-out package with a three-dimensional electromagnetic shielding structure and its fabrication method. The fan-out package includes a molding compound covering a central metal sheet; a first chip and a second chip are respectively disposed above and below the central metal sheet; at least two rows of inner copper pillars and at least two rows of outer copper pillars penetrate the molding compound; a first superwiring layer is disposed on the metal bumps of the first chip and the outer copper pillars, and a first insulating layer is coated on the first superwiring layer, forming a first continuous shielding layer on the surface of the first insulating layer; a second superwiring layer is disposed on the metal bumps of the second chip and the outer copper pillars, forming a back pad; the bottom of the inner copper pillars is led out to the surface through the second superwiring layer, forming an independent ground pad; solder balls are disposed on the back pad and the ground pad; this invention can simultaneously construct a three-dimensional, continuous electromagnetic shielding structure in the fan-out packaging process, achieving all-round shielding of stacked chips, while maintaining the miniaturization and high integration of the package.

The invention discloses a preparation method of a fan-out type packaging structure, and belongs to the technical field of semiconductor packaging. After the release layer is formed on the substrate, the multi-layer structure comprising at least three insulating layers and the rewiring layer is constructed, and the first insulating layer in contact with the release layer adopts silicon dioxide and / or silicon nitride as a non-photosensitive dielectric material. The non-photosensitive dielectric material has high rigidity and low thermal expansion coefficient, provides rigid support for the whole panel, effectively inhibits process warping, and ensures the upper layer patterning precision; meanwhile, an interface formed by the carrier plate and the release layer is easy to separate completely, so that the structural damage risk during release of the carrier plate is reduced; and in combination with a rigid-flexible structure formed by the photosensitive polyimide on the upper layer, the thermal stress can be effectively managed, the reliability of interlayer combination is enhanced, and the service life of the product is prolonged. The fan-out type packaging structure with high yield and high reliability is manufactured through the steps of chip mounting, panel-level plastic packaging, substrate removal, external terminal formation and the like.

The invention provides a fan-out type packaging integrated heat dissipation structure and a preparation method thereof. The fan-out type packaging integrated heat dissipation structure comprises a fan-out type packaging structure, a first medium-thermal interface material layer is arranged on the fan-out type packaging structure, and a radiator and / or a soaking piece are / is arranged on the first medium-thermal interface material layer; wherein the fan-out type packaging structure comprises a chip which is in contact with the first medium-thermal interface material layer, and the thickness of the first medium-thermal interface material layer is less than 100 microns. According to the fan-out type packaging integrated heat dissipation structure and the preparation method thereof provided by the embodiment of the invention, the heat dissipation effect of the fan-out type packaging structure is improved.

The application discloses a fan-out packaging substrate structure based on a thin film capacitor and a preparation method thereof, and belongs to the technical field of integrated circuits. The preparation method of the fan-out packaging substrate structure based on the thin film capacitor comprises the following steps: S10, providing a thin film capacitor, wherein the thin film capacitor is composed of a capacitor layer and first and second copper foil layers located on two sides of the capacitor layer; S20, manufacturing a first circuit structure on one side of the capacitor layer and attaching an ASIC chip and a resistor; S30, manufacturing a second circuit structure on the side of the capacitor layer away from the first circuit layer, and electrically connecting the first circuit structure and the second circuit structure, so as to obtain a substrate; and S40, performing a sound hole processing on the substrate, so as to obtain the fan-out packaging substrate structure based on the thin film capacitor. The ASIC chip is packaged into the substrate by the fan-out technology and the thin film capacitor is used to replace a traditional PCB, so that the buried resistor, the bearing of the MEMS chip and the sound transmission are realized, the product yield and the product service life are improved, the process is simplified, and the production cost is reduced.

According to some embodiments, a device is provided that includes a pre-package and an interconnect package. The pre-package has a semiconductor die having a first contact pad, a molding layer over the semiconductor die, and a first contact comprising a first base portion embedded in the molding layer and contacting the first contact pad, and a first fan out portion over a portion of the molding layer and extending from the first base portion. The interconnect package has a first interconnect structure embedded in a dielectric material and contacting the first contact, wherein the pre-package is embedded in the dielectric material.

The invention discloses a fan-out type wafer level packaging unit and a package formed by stacking the same. The fan-out type wafer level packaging unit comprises a carrier plate, at least one bare chip, a first dielectric layer, at least one second conductive column, a second dielectric layer, a plurality of first conductive connection lines, a third dielectric layer and a plurality of metal protection layers, wherein each first conducting circuit is manufactured and formed on the second surface of each bare chip by utilizing a technology of filling metal paste into a groove and then grinding and forming the conducting circuit, so that the problems that the manufacturing cost is high and the environment is not facilitated when each conducting circuit is manufactured by the existing fan-out packaging technology are solved; wherein the layout of each second welding pad on the first surface of the fan-out type wafer level packaging unit is the same as that of each first welding pad on the second surface of the fan-out type wafer level packaging unit, so that the fan-out type wafer level packaging unit can be manufactured in mass production.

The invention discloses a fan-out type wafer level packaging unit, which comprises a carrier plate, a first dielectric layer, a plurality of first conductive connection lines, at least one first die, a second dielectric layer, at least one conductive column, a plurality of second conductive connection lines, a third dielectric layer, a plurality of third conductive connection lines and at least one second die, wherein each first die and each second die can be electrically connected with each other through each first welding pad around the wafer area on the second surface of each first die; wherein each first conductive connection line, each second conductive connection line and each third conductive connection line are manufactured by using a technology of filling metal paste into the grooves and then grinding and forming the conductive connection lines, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when each conductive connection line is manufactured by using the existing fan-out packaging technology are solved.

The invention discloses a circuit board and electronic equipment, and relates to the technical field of servers, and the circuit board comprises a first pin group and a second pin group which are arranged on a first surface of the circuit board in parallel and at intervals, and a plurality of welded junctions which are arranged on a second surface of the circuit board in a centralized manner, the wiring of the high-speed differential signal transmitted by the connector on the circuit board and the wiring of the low-speed signal transmitted by the electronic device are physically isolated, electromagnetic coupling of the high-speed signal and the low-speed signal on the same layer is avoided, and electromagnetic isolation of the high-speed signal and the low-speed signal is achieved. A first surface of a circuit board is divided into three areas through a first pin group and a second pin group, a high-speed differential signal line connected with the first pin group is fanned out of the first area, a differential clock signal line connected with the first pin group is fanned out of the second area, and a high-speed differential signal line connected with the second pin group is fanned out of the third area. Therefore, the differential clock signal does not occupy the wiring space of the high-speed differential signal, and the interference of adjacent high-speed differential signal lines can be reduced.

Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a controller, a first mold compound surrounding the controller, a plurality of semiconductor dies, a second mold compound surrounding the plurality of semiconductor dies, and one or more through-mold interconnects electrically coupling the controller to the plurality of semiconductor dies.

Semiconductor devices and methods of forming the semiconductor devices are described herein that are directed towards the formation of a system on integrated substrate (SoIS) package. The SoIS package includes an integrated fan out structure and a device redistribution structure for external connection to a plurality of semiconductor devices. The integrated fan out structure includes a plurality of local interconnect devices that electrically couple two of the semiconductor devices together. In some cases, the local interconnect device may be a silicon bus, a local silicon interconnect, an integrated passive device, an integrated voltage regulator, or the like. The integrated fan out structure may be fabricated in wafer or panel form and then singulated into multiple integrated fan out structures. The SoIS package may also include an interposer connected to the integrated fan out structure for external connection to the SoIS package.

The invention discloses an aEASI function optimized fan-out type packaging technology and structure, and relates to the technical field of semiconductor packaging, and the technology comprises the steps: preparing an ASIC control module comprising a vertical interconnection channel; glass is used as a temporary substrate, and the 3P2M configuration fan-out type conductive structure A is fixed through pyrolysis glue; after the ASIC module is inversely installed, the ASIC module is coated with an epoxy molding compound and ground to be thinned; a 3P2M-configuration fan-out conductive structure B (provided with an LED), a low-refractive-index light-transmitting material layer and a 3P2M-configuration fan-out conductive structure C with a notch right above the LED are sequentially arranged, a temporary substrate is removed after ball mounting, and a heat dissipation assembly containing fin type heat dissipation pieces is arranged on the back face of the fan-out conductive structure A. According to the scheme, the signal loss is reduced by more than 20%, the thermal resistance is reduced from 1.5 DEG C / W to 1.0 DEG C / W, the LED luminous efficiency is improved, the high integration level is realized, and the method is suitable for electronic equipment with high requirements on the performance and the integration level.

The invention provides a fan-out type packaging structure integrated with a voltage regulation module and a preparation method thereof, the fan-out type packaging structure comprises a rewiring layer, the voltage regulation module, an electric connection part, a load chip, a solder connection structure and a first filling layer, and the rewiring layer comprises a metal wire exposed on a first main surface of the rewiring layer; the voltage regulation module comprises a VR chip and an integrated inductor. The VR chip is electrically led out to the surface away from the rewiring layer through a TSV column penetrating through the VR chip. The electric connection part and the voltage regulation module are arranged at intervals; the load chips are arranged between the voltage adjusting modules and the electric connecting parts in a crossing mode, the load chips are electrically connected to the corresponding voltage adjusting modules so as to receive the converted electric signals from the voltage adjusting modules, and the load chips are electrically connected with the electric connecting parts so as to achieve electric connection between the load chips and the metal wires. According to the invention, the power is supplied to the load chip through the transmission path as short as possible, the RC delay is obviously reduced, the insertion loss is reduced, and the packaging area can also be reduced.

A vertical line card (VLC) system is disclosed. In one aspect, a VLC system includes a vertically-oriented printed circuit board (RGB), a vertically-oriented integrated circuit (IC) mounted to the RGB, and a cage assembly having cages arranged in a splayed layout so that the cages angularly fan out with respect to the IC.

The present application relates to the field of chips, and provides a chip packaging unit, a package-on-package, and an electronic device. The chip packaging unit comprises a first chip and a second chip that are stacked, a redistribution layer, and a vertical interconnection structure. The vertical interconnection structure is arranged on side surfaces of the first chip and the second chip. The redistribution layer is arranged on the side of one chip where an active surface is located, and is connected to the active surface. Alternatively, the redistribution layer is arranged between active surfaces of the two chips, and is connected to the two active surfaces. Moreover, the redistribution layer is connected to the vertical interconnection structure. The active surfaces of the chips are fanned out using the redistribution layer, and longitudinal interconnection is achieved by means of the vertical interconnection structure located on the side surfaces of the chips; thus, the need for through silicon vias passing through the chips is eliminated, and the manufacturing process complexity can be reduced, thereby lowering manufacturing costs.

The application discloses a circuit board and an electronic device, relates to the technical field of servers, and discloses the circuit board, which comprises a first pin group and a second pin group arranged in parallel and at intervals on a first surface of the circuit board, and a plurality of solder joints arranged in a concentrated manner on a second surface of the circuit board. The wires of high-speed differential signals transmitted by a connector on the circuit board and low-speed signals transmitted by electronic devices are physically isolated, electromagnetic coupling of the high-speed and low-speed signals in the same layer is avoided, and electromagnetic isolation of the high-speed and low-speed signals is achieved. The first surface of the circuit board is divided into three regions by the first pin group and the second pin group, high-speed differential signal lines connected with the first pin group are fanned out from a first region, differential clock signal lines connected with the first pin group are fanned out from a second region, and high-speed differential signal lines connected with the second pin group are fanned out from a third region, so that the differential clock signal lines do not occupy the wire space of the high-speed differential signal lines, and interference between adjacent high-speed differential signal lines is reduced.