83 results about "NOR gate" patented technology

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention relates to an anti-single event transient and anti-single event upset setting latch, which is characterized in that a setting signal end circuit is re-reinforced and designed, and a setting signal access terminal structure of the setting signal end circuit, which is accessed to a setting latch main body circuit, is correspondingly improved; by means of delay and judgment processing provided by a delay chain A, a delay chain B, an XNOR gate and a three-state phase inverter of a setting signal end circuit, it is ensured that a setting signal can be normally transmitted to a setting redundant circuit formed by a first phase inverter and a second phase inverter when no external transient pulse is input to a setting signal end; two paths of setting signals generated by the setting redundant circuit are respectively accessed to the setting latch main body circuit; when external transient pulse input exists at the setting signal end, the setting signal which is influenced by the transient state and causes an error cannot generate effective output through the three-state inverter, so that the error is filtered out, and the purpose of effectively realizing reinforcing design aiming at the external input transient state of the setting signal end is achieved.

The invention relates to the technical field of memristors, and provides a chitosan-based memristor which comprises a substrate, a buffer layer, a composite dielectric layer and a top electrode which are sequentially stacked from bottom to top, the buffer layer is formed by spin-coating a PEDOT: PSS aqueous solution on the substrate and then carrying out heat treatment; the composite dielectric layer is formed by spin-coating the buffer layer with an ultrasonic composite solution formed by a graphene oxide aqueous dispersion and a chitosan acetic acid solution and then carrying out heat treatment. By adopting a collaborative architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT: PSS buffer layer, the prepared bio-based memristor has the effects of relatively high switching ratio, relatively low operating voltage and good performance stability. Meanwhile, based on stable high and low resistance states of the device, all seven basic logic operations including a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate and an XNOR gate are completely realized on a single bio-based platform, the function accuracy can reach 100%, and an unexpected effect is achieved.

In one aspect, a network comprises a plurality of computation nodes, each comprising an input, an output, connections to first and second voltage rails, a capacitor electrically connected to the input configured to store state information as a state voltage, a comparator electrically connected to the capacitor and the output, configured to connect the output to the first voltage rail when the state voltage exceeds the threshold, and the second voltage rail when the state voltage is below the threshold, a plurality of programming units, a plurality of outputs, a network of NOR gates connected to the plurality of inputs and the plurality of outputs, each comprising an input electrically connected to the output of at least one of the plurality of clause formation units, an output connected to an input of at least one computation node, and a current conversion circuit.

A compare circuitry that can be implemented in a memory circuit includes: selection logic coupled to a sense amplifier of the memory circuit, the selection logic structured to receive a sense amplifier enable signal, a column output from the sense amplifier, and a column output bar from the sense amplifier, wherein the selection logic is structured to pass through the column output and the column output bar when the sense amplifier enable signal is active and hold the column output and the column output bar at a same value when the sense amplifier enable signal is inactive; and an XNOR gate structured to receive the column output and the column output bar passed through the selection logic, a data input, and a data input bar and output a bit compare output.

The invention discloses a single-layer crossed two-dimensional channel logic device, belongs to the technical field of information engineering, and is suitable for a phase inverter Inverter, an OR gate or a NOR gate. Comprising a device back gate, a bottom dielectric layer covering the device back gate and a crisscross channel covering the bottom dielectric layer, the crisscross channel is formed by an N-type channel and a P-type channel which are located on the same channel plane, and the middle crossing part is a common region; the two ends of the N-type channel are in contact with the N-type metal, the two ends of the P-type channel are in contact with the P-type metal, the two ends of the N-type metal are connected with the VOUT and the GND respectively, and the two ends of the P-type metal are connected with the VOUT and the VDD respectively. According to the invention, a corresponding logic function can be directly realized at a single device level, a transistor cascade normal form is broken through, and the bottleneck of integration level, power consumption and speed caused by multi-transistor cascade is eliminated. According to the invention, the single-layer crisscross two-dimensional channel is used for replacing multi-tube cascade connection, so that the logic functions of the phase inverter, the OR gate and the NOR gate are realized.

This invention discloses a 4-2 approximation compressor based on memristors, a control method, an apparatus, and applications. It approximates and compresses four 1-bit numbers X1, X2, X3, and X4 using two identical memristor-based majority gate circuits. The two majority gate circuits respectively implement traditional majority gate logic and a novel majority gate logic including inversion logic. The first majority gate circuit implements the traditional majority gate logic M(X1, X3, X4) to obtain the carry result of the 4-2 approximation compressor. The second majority gate circuit implements the novel majority gate logic including inversion logic to obtain the pseudo-sum result of the 4-2 approximation compressor. This invention does not rely on the cascading of a large number of basic logic units such as NAND gates and NOR gates, has a shallow logic depth, and can achieve a 4-2 compressor with good error performance with low circuit complexity, high operation speed, and low power consumption.

A non-overlapping clock generator based on exclusive-NOR gates. The non-overlapping clock generator generates a non-overlapping in-phase output clock signal and an inverting output clock signal from an input clock signal. The non-overlapping clock generator includes first and second exclusive-NOR gates, first and second load transistors cross-coupled to each other, and first and second delay circuits coupled between the in-phase output clock signal and the control terminal of the first load transistor and between the inverting output clock signal and the control terminal of the second load transistor, respectively. Each exclusive-NOR gate includes at least one pass transistor logic to implement exclusive-NOR logic, the at least one pass transistor logic being coupled to the first control voltage. A non-overlapping period between the in-phase output clock signal and the inverting output clock signal is determined based on the first control voltage and / or the delay periods of the first and second delay circuits.

The invention discloses an OR gate, a NOR gate and a maximum gate circuit realized based on a three-valued memristor, and belongs to the technical field of digital logic circuit design, the three-valued memristor is used in a three-valued digital logic circuit, and the OR gate, the NOR gate and the maximum gate circuit are realized. The multi-valued digital logic circuit carries more information, the complexity degree between circuit connecting lines is lower, the area and power consumption of the logic circuit are effectively reduced, the operational capability of the circuit is higher, the structure is clear and simple, implementation is easy, and the multi-valued digital logic circuit can be used for application research in many fields such as multi-valued digital logic operation.

Disclosed are a pulse generator and a pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate. The pulse generator based on a multi-phase delay-locked loop and a high-precision NOR gate according to the present invention comprises: a delay-locked loop module that generates and outputs a phase of an input clock as a plurality of half-phase delay signals; a NOR edge-combining module including a plurality of NOR gates which generate, through pulse-edge combining using the plurality of half-phase delay signals, a specific pulse that satisfies a predetermined condition; a multiplexer that receives, from the NOR edge-combining module, specific pulses classified according to respective conditions, and selects and outputs a specific pulse corresponding to a pulse-selection signal received from a digital block among the received specific pulses; and a pulse-repetition-interval gating module that generates an output pulse by combining the specific pulse outputted from the multiplexer with a pulse-repetition-interval signal.

Embodiments of the present disclosure provide a monostable circuit, wherein the monostable circuit comprises: a monostable main circuit, a shielding time window circuit; wherein the monostable main circuit is configured to receive an input signal of the monostable circuit, a feedback of an output signal of the monostable circuit, a time window signal output by the shielding time window circuit through an AND gate, and then obtain the output signal after passing through a first RC delay circuit and a logic gate, the time window signal being a signal resisting interference of the output signal by abnormal pulses of the input signal; the shielding time window circuit is configured to receive the feedback of the output signal, and then obtain the time window signal after passing through a second RC delay circuit and a logic gate. The problem that the existing monostable circuit may be mis-triggered due to abnormal pulses of an input signal is solved.

The present invention provides an SRAM word line voltage regulation circuit, comprising: a first n-input NAND gate, whose input receives a row decoding signal from a word line decoding circuit; a first PMOS transistor, whose source is connected to a power supply voltage, and whose output signal from the first n-input NAND gate passes through two stages of inverters and is then input into the gate of the first PMOS transistor; a second n-input NAND gate, whose input receives the row decoding signal; a NOR gate, whose input receives the output signal of the second n-input NAND gate and a read / write control signal; and a second PMOS transistor, whose source and drain are short-circuited and connected to the drain of the first PMOS transistor, and which outputs the regulation signal from the word line decoding circuit. The output signal from the NOR gate passes through a single stage of inverters and is then input into the gate of the second PMOS transistor. The present invention can control the SRAM word line voltage without requiring an external control signal, reducing the circuit's control difficulty. Furthermore, by using the second PMOS transistor for charging, capacitors can be eliminated, thereby reducing occupied area.

The invention discloses a PTL-based processor calculation unit design method, which comprises the following steps: multiplexing a processor dual-port register, and obtaining the input of a PTL basic gate circuit from the output of the dual-port register, so as to form a PTL gate circuit as the design basis of a processor calculation unit. The PTL basic gate circuit comprises a NOT gate, an AND gate, an OR gate, an NAND gate, a NOR gate, an XOR gate, an XNOR gate or a transmission gate. And the processor calculation unit comprises an adder, a multiplier or a logical operation unit. And the dual-port register outputs complementary signal pair input of the PTL basic gate circuit.

The present invention discloses a high-precision voltage-mode relaxation oscillator, comprising: a reference current source; a bandgap reference voltage source; a three-terminal input and dual-output comparator, wherein the three-terminal input includes a positive terminal input connected to a reference voltage V REF and two negative terminal inputs respectively connected to the positive terminals of capacitors C1 and C2. The comparison results of the two negative terminal inputs with the positive terminal input are respectively the two output signals of the comparator. Two capacitors C1 and C2, whose negative terminals are both grounded, and whose positive terminals are respectively connected to the two negative terminal inputs of the comparator; a digital control circuit, which consists of a latch formed by two NOR gates and two inverters. The comparator adopted by the voltage-mode relaxation oscillator has a dual-output structure, and there is no need to additionally adopt a D flip-flop for sampling and frequency division. The control logic only adopts a latch formed by two NOR gates and two inverters, which improves the output frequency of the voltage-mode relaxation oscillator, reduces the power consumption and layout area of the circuit.

The application discloses an optimization method, a verification method and a storage medium of a circuit containing uncertain signals. The optimization method of the circuit containing uncertain signals includes at least one of tieX and tieZ, and the optimization method includes: mapping a circuit to be subjected to equivalence verification into a simple circuit structure in which only AND gates and NOT gates exist; and performing traversal on the simple structure circuit, and optimizing the AND gate and / or the NOT gate with an input signal being an uncertain signal, so that the input signal of the AND gate and / or the NOT gate is converted from the uncertain signal into a determined signal. The uncertain signals are subjected to normalization processing, and the uncertainty during verification is avoided.

The utility model relates to a kind of optical fiber receiving circuit module for one turns many under magnetic field environment, including two-way optical fiber plug input to output end, filter capacitor C1, filter capacitor C2, pull-up resistor R1, pull-up resistor R2, signal reverser, multi-or non gate output circuit and TTL level output circuit;The utility model relates to the technical field of optical fiber receiving circuit, the optical fiber receiving circuit module for one turns many under magnetic field environment, realizes two-way optical fiber signal result logic truth table to determine output, is converted into serial communication, with scalability simultaneously, after accumulation can realize one-to-many optical fiber communication, ensure normal communication under magnetic field environment, reduce cost, without separate optical fiber converter, scalable one-to-many, realize the design of multiple optical fiber module conversion serial port, can be realized stable in high magnetic field environment, communication without influence, for receiving instruction reduces the circuit design of redundancy, maximum degree improves stability and reduces cost.

The present invention relates to the technical field of clock control, and discloses a clock control circuit, a power supply control circuit and an integrated circuit with high anti-interference performance. The clock control circuit includes a voltage detection unit, a NOR gate, an AND gate, a plurality of serially connected TFF flip-flops, a latch LAT and an OR gate; in actual use, the present invention detects the fluctuation of the power supply voltage through the voltage detection unit. When the power supply voltage changes upward or downward, the changed high-voltage detection signal or low-voltage detection signal will cause the latch LAT to stop outputting the clock signal through the serially connected TFF flip-flops. After the power supply voltage returns to normal, the serially connected TFF flip-flops will cause the latch LAT to continue outputting the clock signal after timing, so as to avoid generating abnormal clock signals by stopping the clock signal when the power supply voltage is abnormal, thereby improving the anti-interference performance of the clock control circuit.

The invention provides a circuit structure for solving single-particle inversion and a method for solving single-particle inversion. The circuit structure comprises three groups of two-input NAND gates and a three-input NOR gate, wherein the three groups of two-input NAND gates are formed by transforming a first six-transistor static memory unit, and the three-input NOR gate is formed by transforming at least one second six-transistor static memory unit. And the outputs of the three groups of NAND gates are connected to the input of the NOR gate so as to realize a majority voting function on the three paths of redundant input signals. According to the embedded majority voter, the circuit connection of the standard static memory unit is reconstructed, and the embedded majority voter is realized by multiplexing the existing resources on the premise of not changing the layout of a bottom transistor. Compared with the prior art, the scheme effectively solves the problems of extra signal propagation delay and chip area overhead caused by the adoption of an external voter, improves the integration level and time sequence performance of the circuit, and is highly compatible with a standard process.

The invention relates to a self-adaptive dead time generation circuit based on a current mirror load and a generation method thereof, and the circuit comprises a first signal path A which is used for processing a PWMH signal and outputting a signal OUTA with dead time; the second signal path B is used for processing the PWML signal and outputting a signal OUTB with dead time; the biasing circuit comprises a PMOS (P-channel Metal Oxide Semiconductor) tube MP5, a PMOS tube MP7, an NMOS (N-channel Metal Oxide Semiconductor) tube MN7 and a temperature coefficient compensation resistor R1, and is used for generating a reference current IREF with stable temperature; the dynamic feedback module comprises NOR gates NOR1 and NOR2, a Schmitt trigger SMIT, a PMOS transistor MP6 and a resistor R2, and the dead time is prolonged by detecting the current state; the first signal path A is connected with the second signal path B, the first signal path A and the second signal path B adopt mirror image design, each path is composed of two stages of delay units, and the biasing circuit and the dynamic feedback module are connected with the first signal path A and the second signal path B respectively. The system reliability is remarkably improved.

The invention provides a circuit for computing in a memory. The in-memory computing circuit includes a plurality of latches and a plurality of NOR gates. Each latch has a word line, a bit line, a complementary bit line, a first output terminal and a second output terminal. The bit line is coupled to a local bit line of one of a plurality of memory strings in the memory array. The complementary bit line is coupled to a local complementary bit line of a memory string in the memory array. The memory string includes a plurality of storage units. Each storage unit is composed of a storage unit pair. The second output provides a weight signal sensed by the latch from the pair of memory cells. Each NOR gate is provided with a first input end, a second input end and an output end. The first input is coupled to the second output of the latch. The second input end receives an input signal from the outside. The output end outputs the product of the weight signal and the input signal.

The present invention relates to provide limited granting module for computing chips A Granting module is provided as a main module for limiting the computational operations of the computing chips. The Granting module through enable signal grants the operations of an actual design in a computing device, such as CPU, GPU, Artificial Intelligence based Neural Network models, any primitive logic gates such as AND, OR, NOT, XOR, XNOR, NAND, NOR and the like. An encrypted enable logic may be provided for non-System on Chip. A replaceable and / or reconfigurable measuring unit is provided to measure one or more parameters, wherein the measuring unit is adapted to reconfigure for a System on Chip if the Limited grantor is meant for repetitive operations. Different kind of the secured mode settings are implemented which triggers to reset in case of re-configurable measuring unit. Limited grantor Design logic is operative when measuring unit is not reached to measuring limit. The measuring unit provides enable logic triggering that further provide the actual design to operate, whereas if the measuring unit reaches to a measuring limit, the measuring unit triggers enable logic which makes the actual design non operative.

The invention provides a segmented timing circuit and a low-dropout voltage stabilizing circuit, and the segmented timing circuit comprises a timing module and a control module. The timing module comprises a first timing unit and a second timing unit; the first timing unit comprises a first current source, a first capacitor and a first single-pole single-throw switch; the second timing unit comprises a second current source, a second capacitor and a second single-pole single-throw switch; the control module comprises a first comparator, a second comparator, a plurality of first AND gates, a plurality of second AND gates, a plurality of first triggers, a plurality of second triggers, a power-on detection unit, a signal generation unit, a first NOR gate and a second NOR gate; the signal generation unit comprises a plurality of first signal generation circuits and a plurality of second signal generation circuits. The segmented timing circuit provided by the invention not only can reduce the consumption of the digital unit, but also does not need the cooperation of an external digital clock and a digital-to-analog converter, thereby greatly reducing the resource consumption of the digital-to-analog converter.

A latch circuit includes a NOR gate including a first input terminal to receive a scan input signal and a second input terminal to receive a control signal. The latch circuit further includes a first transmission gate including a first input terminal coupled to an output terminal of the NOR gate, and a second input terminal and a third input terminal to receive at least one non-pulsed clock signal. The latch circuit further includes a first inverter including an input terminal to receive a data input signal. The latch circuit further includes a second transmission gate including a first input terminal coupled to an output terminal of the first inverter, and a second input terminal and a third input terminal to receive at least one pulsed clock signal.

The application discloses an instrument forced shutdown circuit and an instrument, and relates to the field of circuit protection. Wherein, the first and second input pins of an OR gate chip U1 are connected with first and second buttons KEY1 and KEY2 respectively; the first and second input pins of an NOR gate chip U2 are connected with the output pin of the OR gate chip U1 and a third button KEY3 respectively; KEY1, KEY2 and KEY3 are three different buttons on the instrument; the output pin of the NOR gate chip U2 is connected with the base of a transistor Q1 through a resistor R1; the collector of the transistor Q1 is connected with the base of a transistor Q2; the collector of the transistor Q2 is connected with the gate of a PMOS tube U3 through a resistor R5; the source of the PMOS tube U3 is connected with the positive pole of a battery, and the drain thereof is connected with the power supply circuit of a microcontroller. The application can realize the function of power-off after pressing the button without changing the appearance structure of the instrument, and there is no risk of false touch.

The utility model provides a motor fault detection system, and belongs to the technical field of motors. The motor fault detection system comprises a U-phase detection module, a V-phase detection module, a W-phase detection module, an AND gate, a NOR gate, an OR gate and a main control module. The first input end of the AND gate is connected with the U-phase detection module, the second input end of the AND gate is connected with the V-phase detection module, and the third input end of the AND gate is connected with the W-phase detection module; the first input end of the NOR gate is connected with the U-phase detection module, the second input end of the NOR gate is connected with the V-phase detection module, and the third input end of the NOR gate is connected with the W-phase detection module; the output end of the AND gate is connected with the first input end of the OR gate, the output end of the NOR gate is connected with the second input end of the OR gate, and the output end of the operational amplifier U1 is connected with the first input end of the AND gate and the first input end of the NOR gate. According to the invention, the problem that a traditional motor fault detection means is difficult to find out an open-phase fault accurately in real time can be solved.

The present invention discloses a data eye width extended decision feedback equalizer and a data eye width extension method, which relate to the technical field of digital signal processing. The decision feedback equalizer includes: a first numerically controlled delay unit, a second numerically controlled delay unit, an OR gate logic circuit, a NOR gate logic circuit, a data sampler, and a decision feedback circuit; the first numerically controlled delay unit is used for delaying the positive-phase signal and outputting and sending it to the OR gate logic circuit; the second numerically controlled delay unit is used for delaying the negative-phase signal and outputting and sending it to the NOR gate logic circuit; the data sampler is used for outputting 4 sampled data; the decision feedback circuit is used for taking the odd-bit signal as the first output signal and taking the even-bit signal as the second output signal. The present invention realizes the extension of the data eye width, thereby effectively improving the jitter tolerance of the deserializer and reducing the bit error rate of the deserializer.

The invention discloses a bit stream random number generator, a random multiplication circuit and a calculation method, and belongs to the technical field of integrated circuits. A reverse signal end of a highest-bit D trigger Ln of a linear feedback shift register is respectively connected with a NOR gate and a NAND gate, and output signal ends of n-1 low-bit triggers in the linear feedback shift register are respectively connected with a comparator; a sign bit xn of an n-bit binary number corresponding to the target numerical value is input into the NOR gate and the NAND gate respectively; bits corresponding to the amplitude bits of the n-bit binary number are input to the comparator; the comparator and the NOR gate are connected with the OR gate; the OR gate and the NAND gate are connected with the AND gate. In the application, the two bit stream random number generators can generate two bit streams with low correlation, so that the numerical value shown by the bit stream obtained by carrying out multiplication (namely XNOR operation) on the two bit streams is closer to the product result of two target numerical values.

The application relates to the technical field of memristor, and provides a chitosan-based memristor, which comprises, from bottom to top, a substrate, a buffer layer, a composite dielectric layer and a top electrode; the buffer layer is formed by heat treatment after PEDOT:PSS aqueous solution is spin-coated on the substrate; and the composite dielectric layer is formed by heat treatment after an ultrasonic composite solution formed by graphene oxide aqueous dispersion and chitosan acetic acid solution is spin-coated on the buffer layer. Through the synergistic architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT:PSS buffer layer, the prepared bio-based memristor has the effects of high switching, low operating voltage and good performance stability. Meanwhile, based on the stable high and low resistance states of the device, all seven basic logic operations including the non-gate, the and gate, the or gate, the not-and gate, the not-or gate, the exclusive or gate and the same or gate are completely realized on a single bio-based platform, the function correctness rate can reach 100%, and unexpected effects are achieved.

The present disclosure provides a ripple carry full adder circuit including a sum generation circuit that includes a first bit generation circuit and a second bit generation circuit, where the first bit generation circuit is configured to generate a first output sum signal, and the second bit generation circuit is configured to generate a second output sum signal; and a carry bit generation circuit that is configured to generate an output carry signal, where the carry bit generation circuit comprises a compute logic circuit and a ripple carry generation circuit, the ripple carry generation circuit further including a plurality of carry bit generation NAND gates; the first bit generation circuit having a first NOR gate, a first logic circuit, a first inverter, and a second logic circuit, and the second bit generation circuit having a second NOR gate, a third logic circuit, a fourth inverter, and a fourth logic circuit.

The invention relates to the field of integrated circuit design, in particular to a positive and negative voltage input enabling circuit for a negative voltage LDO (Low Dropout Regulator), which is composed of four PMOS (P-channel Metal Oxide Semiconductor) tubes MP1-MP4, seven NMOS (N-channel Metal Oxide Semiconductor) tubes MN1-MN7, three NOT gates INV1-INV3, a NOR gate NAND1, a resistor R1, a capacitor C1 and a diode D1. According to the invention, the working characteristics of the complementary metal oxide semiconductor are utilized, a negative voltage signal can be used, a positive voltage signal can also be used as an enabling input control signal, and the circuit has the characteristics of clear logic function, simple circuit structure and easy realization.