36 results about "NOR gate" patented technology

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention relates to the technical field of memristors, and provides a chitosan-based memristor which comprises a substrate, a buffer layer, a composite dielectric layer and a top electrode which are sequentially stacked from bottom to top, the buffer layer is formed by spin-coating a PEDOT: PSS aqueous solution on the substrate and then carrying out heat treatment; the composite dielectric layer is formed by spin-coating the buffer layer with an ultrasonic composite solution formed by a graphene oxide aqueous dispersion and a chitosan acetic acid solution and then carrying out heat treatment. By adopting a collaborative architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT: PSS buffer layer, the prepared bio-based memristor has the effects of relatively high switching ratio, relatively low operating voltage and good performance stability. Meanwhile, based on stable high and low resistance states of the device, all seven basic logic operations including a NOT gate, an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate and an XNOR gate are completely realized on a single bio-based platform, the function accuracy can reach 100%, and an unexpected effect is achieved.

A compare circuitry that can be implemented in a memory circuit includes: selection logic coupled to a sense amplifier of the memory circuit, the selection logic structured to receive a sense amplifier enable signal, a column output from the sense amplifier, and a column output bar from the sense amplifier, wherein the selection logic is structured to pass through the column output and the column output bar when the sense amplifier enable signal is active and hold the column output and the column output bar at a same value when the sense amplifier enable signal is inactive; and an XNOR gate structured to receive the column output and the column output bar passed through the selection logic, a data input, and a data input bar and output a bit compare output.

This invention discloses a 4-2 approximation compressor based on memristors, a control method, an apparatus, and applications. It approximates and compresses four 1-bit numbers X1, X2, X3, and X4 using two identical memristor-based majority gate circuits. The two majority gate circuits respectively implement traditional majority gate logic and a novel majority gate logic including inversion logic. The first majority gate circuit implements the traditional majority gate logic M(X1, X3, X4) to obtain the carry result of the 4-2 approximation compressor. The second majority gate circuit implements the novel majority gate logic including inversion logic to obtain the pseudo-sum result of the 4-2 approximation compressor. This invention does not rely on the cascading of a large number of basic logic units such as NAND gates and NOR gates, has a shallow logic depth, and can achieve a 4-2 compressor with good error performance with low circuit complexity, high operation speed, and low power consumption.

Disclosed are a pulse generator and a pulse generation method based on a multi-phase delay-locked loop and a high-precision NOR gate. The pulse generator based on a multi-phase delay-locked loop and a high-precision NOR gate according to the present invention comprises: a delay-locked loop module that generates and outputs a phase of an input clock as a plurality of half-phase delay signals; a NOR edge-combining module including a plurality of NOR gates which generate, through pulse-edge combining using the plurality of half-phase delay signals, a specific pulse that satisfies a predetermined condition; a multiplexer that receives, from the NOR edge-combining module, specific pulses classified according to respective conditions, and selects and outputs a specific pulse corresponding to a pulse-selection signal received from a digital block among the received specific pulses; and a pulse-repetition-interval gating module that generates an output pulse by combining the specific pulse outputted from the multiplexer with a pulse-repetition-interval signal.

Embodiments of the present disclosure provide a monostable circuit, wherein the monostable circuit comprises: a monostable main circuit, a shielding time window circuit; wherein the monostable main circuit is configured to receive an input signal of the monostable circuit, a feedback of an output signal of the monostable circuit, a time window signal output by the shielding time window circuit through an AND gate, and then obtain the output signal after passing through a first RC delay circuit and a logic gate, the time window signal being a signal resisting interference of the output signal by abnormal pulses of the input signal; the shielding time window circuit is configured to receive the feedback of the output signal, and then obtain the time window signal after passing through a second RC delay circuit and a logic gate. The problem that the existing monostable circuit may be mis-triggered due to abnormal pulses of an input signal is solved.

The invention discloses a PTL-based processor calculation unit design method, which comprises the following steps: multiplexing a processor dual-port register, and obtaining the input of a PTL basic gate circuit from the output of the dual-port register, so as to form a PTL gate circuit as the design basis of a processor calculation unit. The PTL basic gate circuit comprises a NOT gate, an AND gate, an OR gate, an NAND gate, a NOR gate, an XOR gate, an XNOR gate or a transmission gate. And the processor calculation unit comprises an adder, a multiplier or a logical operation unit. And the dual-port register outputs complementary signal pair input of the PTL basic gate circuit.

The application discloses an optimization method, a verification method and a storage medium of a circuit containing uncertain signals. The optimization method of the circuit containing uncertain signals includes at least one of tieX and tieZ, and the optimization method includes: mapping a circuit to be subjected to equivalence verification into a simple circuit structure in which only AND gates and NOT gates exist; and performing traversal on the simple structure circuit, and optimizing the AND gate and / or the NOT gate with an input signal being an uncertain signal, so that the input signal of the AND gate and / or the NOT gate is converted from the uncertain signal into a determined signal. The uncertain signals are subjected to normalization processing, and the uncertainty during verification is avoided.

The utility model relates to a kind of optical fiber receiving circuit module for one turns many under magnetic field environment, including two-way optical fiber plug input to output end, filter capacitor C1, filter capacitor C2, pull-up resistor R1, pull-up resistor R2, signal reverser, multi-or non gate output circuit and TTL level output circuit;The utility model relates to the technical field of optical fiber receiving circuit, the optical fiber receiving circuit module for one turns many under magnetic field environment, realizes two-way optical fiber signal result logic truth table to determine output, is converted into serial communication, with scalability simultaneously, after accumulation can realize one-to-many optical fiber communication, ensure normal communication under magnetic field environment, reduce cost, without separate optical fiber converter, scalable one-to-many, realize the design of multiple optical fiber module conversion serial port, can be realized stable in high magnetic field environment, communication without influence, for receiving instruction reduces the circuit design of redundancy, maximum degree improves stability and reduces cost.

The invention provides a circuit for computing in a memory. The in-memory computing circuit includes a plurality of latches and a plurality of NOR gates. Each latch has a word line, a bit line, a complementary bit line, a first output terminal and a second output terminal. The bit line is coupled to a local bit line of one of a plurality of memory strings in the memory array. The complementary bit line is coupled to a local complementary bit line of a memory string in the memory array. The memory string includes a plurality of storage units. Each storage unit is composed of a storage unit pair. The second output provides a weight signal sensed by the latch from the pair of memory cells. Each NOR gate is provided with a first input end, a second input end and an output end. The first input is coupled to the second output of the latch. The second input end receives an input signal from the outside. The output end outputs the product of the weight signal and the input signal.

The application relates to the technical field of memristor, and provides a chitosan-based memristor, which comprises, from bottom to top, a substrate, a buffer layer, a composite dielectric layer and a top electrode; the buffer layer is formed by heat treatment after PEDOT:PSS aqueous solution is spin-coated on the substrate; and the composite dielectric layer is formed by heat treatment after an ultrasonic composite solution formed by graphene oxide aqueous dispersion and chitosan acetic acid solution is spin-coated on the buffer layer. Through the synergistic architecture of the chitosan-graphene oxide composite dielectric layer and the PEDOT:PSS buffer layer, the prepared bio-based memristor has the effects of high switching, low operating voltage and good performance stability. Meanwhile, based on the stable high and low resistance states of the device, all seven basic logic operations including the non-gate, the and gate, the or gate, the not-and gate, the not-or gate, the exclusive or gate and the same or gate are completely realized on a single bio-based platform, the function correctness rate can reach 100%, and unexpected effects are achieved.

The present disclosure provides a ripple carry full adder circuit including a sum generation circuit that includes a first bit generation circuit and a second bit generation circuit, where the first bit generation circuit is configured to generate a first output sum signal, and the second bit generation circuit is configured to generate a second output sum signal; and a carry bit generation circuit that is configured to generate an output carry signal, where the carry bit generation circuit comprises a compute logic circuit and a ripple carry generation circuit, the ripple carry generation circuit further including a plurality of carry bit generation NAND gates; the first bit generation circuit having a first NOR gate, a first logic circuit, a first inverter, and a second logic circuit, and the second bit generation circuit having a second NOR gate, a third logic circuit, a fourth inverter, and a fourth logic circuit.

The invention relates to the field of integrated circuit design, in particular to a positive and negative voltage input enabling circuit for a negative voltage LDO (Low Dropout Regulator), which is composed of four PMOS (P-channel Metal Oxide Semiconductor) tubes MP1-MP4, seven NMOS (N-channel Metal Oxide Semiconductor) tubes MN1-MN7, three NOT gates INV1-INV3, a NOR gate NAND1, a resistor R1, a capacitor C1 and a diode D1. According to the invention, the working characteristics of the complementary metal oxide semiconductor are utilized, a negative voltage signal can be used, a positive voltage signal can also be used as an enabling input control signal, and the circuit has the characteristics of clear logic function, simple circuit structure and easy realization.

A multiplexer and a serializer including the multiplexer are provided. The multiplexer selects one of first to fourth data signals in response to first to fourth pulses. The first to fourth pulses correspond to the first to fourth data signals, respectively, and are sequentially switched. The multiplexer includes: (1) a NAND gate that receives the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse, and outputs a first gate signal; and (2) a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse, and outputs a second gate signal. The first data signal corresponds to a rising edge of the first pulse, and the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

The utility model relates to the technical field of automatic control, and discloses a steam turbine emergency interruption protection tripping device which comprises a plurality of electric appliance protection screens which are connected with an output clamping piece used for transmitting fault tripping protection signals of a generator transformer set. The output cards are connected with AND gate circuits with the number corresponding to the number of the output cards, any AND gate circuit is connected with the two output cards, and the output end of any AND gate circuit is connected with shutdown output equipment through a NOR gate circuit; according to the utility model, shutdown operation can be realized only through triggering of at least two paths of fault signals, so that risks of operation refusal and maloperation of tripping protection are effectively avoided, and the stability and the reliability of the device are improved.

The invention discloses a back-to-back type folded and stacked high-integration-level OECT circuit. The circuit comprises an organic electrochemical transistor OECT, a phase inverter, a NAND gate and a NOR gate, wherein the OECT, the phase inverter, the NAND gate and the NOR gate are packaged on the substrate through the electrode layer, the semiconductor active layer, the electrolyte layer, the gate layer, the through hole, the conductive slurry and the packaging layer, so that a high-integration-level OECT circuit is obtained; in the packaging process, the sampling back-to-back folding and stacking structure breaks through the limitation of plane integration, and three-dimensional high-density arrangement of the OECT device and the circuit thereof is realized in a unit projection area.

The application belongs to the technical field of circuit and provides a protection circuit and equipment, the protection circuit comprises a first input end, a second input end, an output end, a first comparator, a second comparator, a third comparator, a first NOR gate, a second NOR gate, a first MOS tube, a second MOS tube and a NOT gate; the first input end is connected with the first MOS tube, the first comparator and the second comparator respectively, the first comparator and the first MOS tube are connected with the output end, the first comparator is further connected with the first NOR gate, and the first NOR gate is further connected with the first MOS tube; the second input end is connected with the second comparator, the second MOS tube and the third comparator respectively, the third comparator and the second MOS tube are connected with the output end, the third comparator is further connected with the second NOR gate, the second NOR gate is further connected with the second MOS tube, the second NOR gate and the second comparator are connected with the NOT gate, and the NOT gate is further connected with the first NOR gate. The application improves the reliability of voltage protection between circuits by combining the comparator with the NOT gate and the MOS tube.

The invention discloses a large-area organic single crystal transistor and a preparation method and application thereof, and belongs to the field of organic semiconductors. The organic single crystal transistor sequentially comprises a flexible seamless embedded metal electrode, a metal oxide layer, an organic semiconductor layer, a polymer insulating layer and a patterned gate layer from bottom to top. The organic single crystal transistor provided by the invention has high device performance and no hysteresis phenomenon; due to the highly uniform carrier mobility, logic gate circuits such as phase inverters, NAND gates and NOR gates and complex circuits such as oscillators can be prepared through circuit design. And a scheme is provided for application, scientific research and industrialization of the organic flexible circuit.

This invention relates to the field of integrated circuits, specifically to a time residual processing circuit, a correlation multiple sampling method, an SS-ADC circuit, and a chip. The time residual processing circuit extracts the residual signal from the quantization result based on the output of the comparator in the SS-ADC and completes the quantization of the time residual. The time residual processing circuit consists of a D flip-flop, an NOR gate, two resistors of the same value, four NMOS transistors, two capacitors of different values, and a comparator. A charging and discharging channel formed by the two capacitors is used to perform a rate-multiplication of the pulse width of the residual signal. The proposed correlation multiple sampling method and its circuit adjust the ramp signal type and the number of repeated samplings based on the light intensity of the input signal during the pixel signal quantization stage, and quantize the time residual of the process to correct the comparator output. This invention solves the problems of insufficient accuracy and high power consumption of the SS-ADC used in existing CIS circuits.

A computing-in-memory circuit including latches and NOR gates is provided. Each latch has a word line, a bit line, a complementary bit line, and first and second output ends. The bit line is coupled to a local bit line of one memory string in a memory array. The complementary bit line is coupled to a local complementary bit line of the memory string. The memory string includes storage units, each having a memory cell pair. The second output end provides a weight signal, sensed by the latch, from the memory cell. Each NOR gate has a first input end coupled to the second output end of the latch, a second input end receiving an external input signal, and an output end outputting a product of the weight and input signals.

The utility model relates to the technical field of power equipment, and discloses a relay fault detection circuit and a power distribution terminal controller, and the circuit comprises a coil disconnection monitoring circuit and a contact adhesion monitoring circuit. The coil disconnection monitoring circuit comprises an XNOR gate and a first photoelectric coupler, a first input end of the XNOR gate is connected with a first voltage through a detected relay coil, is connected with the detected relay coil through a resistor R12, and is grounded through a pull-down resistor, a second input end is connected with a closing control signal, and an output end outputs a coil fault signal. The positive electrode of the input end of the first photoelectric coupler is connected with a first voltage, the negative electrode of the input end is connected with a closing control signal, the two output ends of the first photoelectric coupler are connected with the end, back to the first voltage, of a detected relay coil and the ground respectively, and the contact adhesion monitoring circuit is used for outputting a contact fault signal. The circuit and the controller can detect the fault of the relay before closing, thereby avoiding accidents caused by the fault of the relay.

This invention relates to a restriction authorization module for setting limits on computing chips. This authorization module is configured as a main module for restricting computational operations on the computing chip. The authorization module authorizes the operation of the actual design in the computing device (such as a CPU, GPU, AI-based neural network model, or any basic logic gate such as AND, OR, NOT, XOR, XNOR, NAND, NOR, NOR, etc.) via an enable signal. Encryption enable logic can be set for non-on-chip systems. Replaceable and / or reconfigurable measurement units are configured to measure one or more parameters, wherein the measurement unit is adapted to be reconfigured for on-chip systems if the restriction authorization is used for repeated operations. Different types of security mode settings are implemented, which trigger a reset in the case of reconfigurable measurement units. The restriction authorization design logic is operable when the measurement unit does not reach the measurement limit. The measurement unit provides enable logic triggering, which further enables the actual design to operate; however, if the measurement unit reaches the measurement limit, the measurement unit triggers enable logic, rendering the actual design inoperable.

The invention discloses an oscillator circuit without a comparator and reference voltage, which belongs to the field of integrated circuits and comprises a current-limiting resistor R, integrating capacitors C1 and C2, P-type charging and discharging switch tubes PM1 to PM3, N-type charging and discharging switch tubes NM1 to NM3, digital logic circuits INV1 to INV3, a NOR gate NOR1, a NAND gate NAND1 and a buffer BUF1. According to the invention, the structure is simple, and stable oscillation can be realized only by a small number of basic components; dependence on a comparator or a high-precision reference voltage source in a traditional scheme is abandoned, system power consumption is effectively reduced, and meanwhile the chip area is remarkably reduced. By adjusting resistance and capacitance parameters, the frequency and the duty ratio of the output square wave can be flexibly adjusted, and the wide application prospect is achieved.

The application discloses a memory-compute FPGA architecture. Memory-compute cores, memory blocks and logic function blocks used for replacing part of the logic function blocks are arranged in a row-column array and arranged in an island type architecture. In the memory-compute cores, there are SRAMs arranged in a row-column array, the SRAMs store one-bit data, the output ends of an address decoding circuit are connected with each row of the SRAM array, the output ends of a write control circuit are connected with each column of the SRAM array, each eight columns of the SRAM array and an input register are connected with an 8-bit input port of an addition tree through a multiplexer and eight NOR gates, and the output port of the addition tree is connected with an output register through a shift and addition module and a quantization module in sequence. The application realizes in-memory computation on the FPGA, utilizes the parallelism and reconfigurability of the FPGA to support mapping of various networks, and utilizes in-memory computation technology to reduce data movement and further reduce computation power consumption.

The application discloses a kind of logic circuits based on high electron mobility transistor, belong to semiconductor device technical field, including by or non-gate and non-gate combination or gate circuit, and by and non-gate and non-gate combination and gate circuit.Or non-gate, and non-gate and non-gate are respectively integrated by parallel / series connection of depletion-mode HEMT device and enhancement-mode HEMT device.Construction is adopted in the present application lower layer gradual barrier layer or ladder gradual barrier layer, in combination with ion implantation area design, accurately control threshold voltage from material growth source, completely solve the technical problems of poor threshold voltage consistency and low stability caused by traditional gate recess etching process.Circuit noise tolerance is improved, static power consumption is effectively reduced, and is suitable for high-performance, low-power radio frequency and digital integrated electronic system.

The application provides a timing circuit for improving reading speed, a first delay module, a second delay module and a third delay module, a first DQ flip-flop, a second DQ flip-flop, a third DQ flip-flop, a second NOR gate, a NAND gate and a delay unit; a first output end of the first delay module is used for outputting a first delay clock signal, a second output end of the first delay module and a read end are respectively connected with input ends of the NAND gate, and an output end of the NAND gate is used for outputting a clear signal; output ends of the delay unit are respectively connected with CLK ends of the first DQ flip-flop and the third DQ flip-flop, so that a second delay clock signal lags behind a signal of the RSTB end. The application generates a logical relationship between the CLR signal and a delay signal of the first delay module, that is, when the CLR signal is high, no matter what state of the first delay clock signal is at this time, the second delay clock signal is low, and the truncation function is normal.

The invention discloses a double-edge quantizer and a high-resolution time measurement quantization circuit. The double-edge quantizer comprises a band-enabled NAND gate RS latch LATCH1 and a band-enabled NOR gate RS latch LATCH2, the LATCH1 and the LATCH2 are connected in parallel, rising edge phase discrimination and falling edge phase discrimination can be carried out on input periodic signals respectively, and phase discrimination results are output. Compared with a conventional NAND gate RS latch, the LATCH1 is additionally provided with a tube P3 and a tube P4, a grid electrode of the tube P3 is connected with a power supply, and a grid electrode of the tube P4 is connected with an enable signal EN; compared with a conventional NOR gate RS latch, the LATCH2 is additionally provided with an N7 tube and an N8 tube, a grid electrode of a P8 is grounded, a grid electrode of the N7 tube is connected with an inverse signal ENB of an enable signal, and the P3 tube and the N8 tube play roles in balancing and symmetry of a circuit structure; and when the EN and the ENB are enabled, Q1B and Q2B signals are respectively preset as a high level and a low level.

The application discloses a kind of low-power dynamic latching comparators, belong to comparator circuit structure technical field, comprising: 7 transmission gates, 2 inverters, 2 two-input nor gates, first sampling capacitor and second sampling capacitor;2 inverters are connected in head and tail to constitute amplification circuit, 2 two-input nor gates are connected to each other to form dynamic latch circuit, 7 transmission gates are composed of first transmission gate to seventh transmission gate, by specific connection relationship and timing control, first sampling capacitor and second sampling capacitor are collected input signal and reference signal respectively through first transmission gate and second transmission gate, then input signal and reference signal are transmitted to both ends of amplification circuit to compare, amplification circuit amplifies comparison result, then final result is latched into dynamic latch circuit;The application used are all simple gate circuit and MOM capacitor, amplification circuit is only connected in head and tail by 2 inverters, and circuit scale is small, so that power consumption is greatly reduced.

A metastable error field correction circuit of a successive approximation analog-to-digital converter comprises an OR gate and an AND gate constituting an error correction module and an OR gate, a flip-flop and a delay unit constituting an error detection module, wherein: the logical input ends of the OR gate and the AND gate of the error correction module are connected with the output end of the comparator of the analog-to-digital converter to be tested, the logical output ends of the OR gate and the AND gate are respectively output to the OR gate of the error detection module to obtain a decision signal whether a metastable phenomenon occurs, the flip-flop generates an error pre-correction signal according to the decision signal and the clock signal of the comparator of the analog-to-digital converter to be tested, and the delay unit generates a pair of error correction signals which are mutually inverted according to the decision signal and the error pre-correction signal of the flip-flop and outputs them to the OR gate and the AND gate of the error correction module to generate a corrected signal and then outputs the corrected signal to a latch. The present application corrects the error caused by the metastable state of the comparator in the field, can determine that the error is less than the acceptable range, and the forced setting will not cause error, thereby significantly improving the reliability of the ADC and ensuring that the ADC can still maintain high precision and stability under variable input conditions.

The invention discloses a quick response level shift circuit with enhanced common mode transient rejection capability, which comprises a voltage domain conversion module, the voltage domain conversion module is respectively connected with a level shift input signal VIN, a dv / dt noise suppression module and a delay reduction module, and the delay reduction module is connected with a starting circuit module and a level shift output signal VOUT. According to the quick response level shift circuit with the enhanced common-mode transient rejection capability, on one hand, low-level signals are directly collected through the structure of the NOR gate and the T trigger, time delay on a transmission slow path is eliminated, and transmission time delay and dynamic power consumption of the level shift circuit are effectively reduced; and on the other hand, dv / dt noise is detected and eliminated in real time by adding the dv / dt noise suppression module, and the delay reduction module and the dv / dt noise suppression module are mutually independent and do not influence each other, so that collaborative optimization of the speed and the anti-noise capability can be considered finally.