380results about "Pulse generation by logic circuits" patented technology

The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking, relates to the technical field of integrated circuits, and is used for solving the technical problems that an existing injection locking oscillator limits the frequency tuning range and cannot effectively suppress noise. The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking. The low-phase noise ring voltage-controlled oscillator comprises a first ring oscillator unit and a second ring oscillator unit, the n first ring oscillator units are connected in series to form a chain structure; the second ring oscillator unit is provided with a cross coupling inverter complementary injection unit and a tail current source injection unit; a first output end of the chain structure is connected with a second input end of the second ring oscillator unit, and a second output end of the chain structure is connected with a first input end of the second ring oscillator unit; a first signal is injected into a cross-coupling inverter complementary injection unit and a tail current source injection unit, and a second ring oscillator unit receives a second signal output by a chain structure and then outputs a third signal.

The invention aims to provide a phase noise and maximum oscillation frequency adjustable ring oscillator and a control method. The oscillator comprises a main path and a third auxiliary path, the third auxiliary path is connected with the main path and is used for improving the oscillation frequency; by inserting the adjustable phase inverter, when the frequency of the ring oscillator does not meet the specification under the extreme corner condition, the oscillation frequency is improved by adjusting the phase inverter to sacrifice some phase noise.

The invention belongs to the technical field of electronic circuits, and particularly relates to an oscillator circuit for a PWM controller. Comprising an oscillator module which comprises a feedback loop and a current detection circuit; the hiccup module is used for gating and outputting an input signal by a data selector according to the level of the input PWM logic control signal so as to control the on-off of a transmission gate, establishing a charging and discharging process and providing a delay starting function for the oscillator module; and the jittering frequency module outputs current sources Iref0 of different sizes by performing combined gating on a current source I'ref and current sources I1-I4, outputs four paths of current sources Iref1-Iref4 of different sizes through a current mirror array mirror image, and provides charging and discharging current for the oscillator module and the hiccup module. By dynamically adjusting the PWM frequency, the switching frequency is matched with the load requirement, the invalid switching frequency is reduced, and the power consumption is greatly reduced.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

A method of a signal transmission device includes: providing at least one delay line circuit having a plurality of first delay units connected in series; providing a control voltage as a supply voltage provided for a first delay unit of the at least one delay line circuit; and adjusting the control voltage to maintain a delay amount of the first delay unit at a specific delay amount when a variation of the delay amount of the first delay unit occurs.

The invention relates to a passive wireless temperature sensor circuit, which comprises a transceiving antenna, an RF-DC rectifier circuit, a temperature sensing circuit and a backscatter circuit, the RF-DC rectifier circuit receives external radio frequency energy based on the transmit-receive antenna and then outputs direct current for power supply. The temperature sensing circuit comprises a complementary absolute temperature voltage generator and a ring oscillator; the complementary absolute temperature voltage generator comprises an MOS tube and generates CTAT voltage based on temperature characteristics of the MOS tube. The ring oscillator converts the CTAT voltage into an oscillation frequency signal of the ring oscillator and then outputs a square wave frequency signal with a negative temperature coefficient; the backscattering circuit backscatters the square wave frequency signal through the transceiving antenna; the CTAT key generation circuit built by the MOS tube generates CTAT voltage, a temperature frequency conversion chain is built through the CTAT voltage and the ring oscillator, temperature information is converted into frequency information of the oscillator, the power consumption of the temperature sensing circuit can be effectively reduced, and meanwhile the voltage coefficient of the CTAT voltage is increased by combining the temperature characteristic of the MOS tube.

Aspects of the disclosure are directed to voltage sensing for safety-critical applications. In accordance with one aspect, the disclosure includes a multi-phase ring oscillator (RO) configured to operate in a first voltage domain; a frequency counter coupled to the multi-phase RO, the frequency counter configured to accumulate a plurality of phase cycles from the multi-phase RO over a time duration to generate a digital count word; an alarm processor coupled to the frequency counter, the alarm processor configured to receive an alarm state signal from the frequency counter; and a heartbeat detector coupled to the multi-phase RO, the heartbeat detector configured to operate in a second voltage domain and configured to detect a periodic recurrence of a heartbeat pulse to determine an integrity of the sensor function as a whole and alarm state signal in particular.

Multi-phase oscillator circuits are disclosed. According to one aspect, a multi-phase oscillator circuit for a millimeter wave (mmW), transceiver is provided. The multi-phase oscillator circuit includes a plurality of inductor-coupled ring oscillators, each inductor-coupled ring oscillator comprising a plurality of single stage active delay cells, an output of each of the plurality of inductor-coupled ring oscillators being inductively coupled to an output of another one of the plurality of inductor-coupled ring oscillators.

A circuit that is capable of generating a negative voltage on a negative voltage supply node. The circuit includes a negative voltage generation circuit, an oscillator and an oscillator control signal generator. The negative voltage generation circuit generates a negative voltage on the negative voltage supply node in response to receiving a signal from the oscillator. The negative voltage generated by the negative voltage generation circuit depends upon the frequency of the signal from the oscillator. The oscillator control signal generator controls the frequency of the signal from the oscillator by sensing the negative voltage present on the negative voltage supply node, and by increasing or decreasing the frequency of the signal from the oscillator accordingly. Thus, charge is replenished to the negative voltage supply node to more closely match the drawing of charge from that negative voltage supply node, thereby more accurately generating the negative voltage.

The invention discloses a universal multiphase clock generation circuit and a combinational logic circuit thereof. The combinational logic circuit comprises a first-stage NAND gate and a second-stage NAND gate which are cascaded, the generation circuit is constructed by taking the combinational logic circuit as a basic unit; the generation circuit is a closed loop formed by connecting 2N basic units end to end; the first-stage NAND gates of the odd-numbered basic units form latches pairwise, and the first-stage NAND gates of the even-numbered basic units also form latches pairwise; each basic unit takes the output of the adjacent previous basic unit as the input and outputs a basic clock signal with a preset duty ratio based on a preset selection signal; performing odd number of times of phase inversion on the 2N basic clock signals output by the 2N basic units to obtain 2N-phase non-overlapping clock signals; and when N is an odd number, performing NAND operation on the N groups of adjacent two basic clock signals to obtain N-phase non-overlapping clock signals.

A level shifter includes a first buffer circuit, a first capacitor, a second capacitor, a cross-coupled inverter, and a second buffer circuit. The first buffer circuit is configured to drive a first input signal and a second input signal with a first high power supply voltage and a first low power supply voltage to generate a first main driving signal and a second main driving signal. The first capacitor, the second capacitor, and the cross-coupled inverter are configured to generate signals of a first node and a second node based on the first and second main driving signals. The second buffer circuit is configured to drive the signals of the first and second nodes with a second high power supply voltage and a second low power supply voltage to generate a first output signal and a second output signal.

A temperature compensated oscillator includes: a current source configured to generate a proportional to absolute temperature (PTAT) current; and a ring oscillator which has a complementary to absolute temperature (CTAT) oscillation frequency and is configured to receive the PTAT current to generate an oscillation signal. The current source includes a tracking MOS device and a resistor which are coupled in series. The tracking MOS device and at least one MOS device of the ring oscillator have the same conductive type, and a gate-source voltage of the tracking MOS device and a gate-source voltage of the at least one MOS device have the same CTAT coefficient, such that when the temperature compensated oscillator operates, the tracking MOS device and the at least one of the first MOS device have a tracking effect to compensate the CTAT oscillation frequency.

A layered pulse generator for a vertical-cavity surface-emitting laser (“VCSEL”) driver is disclosed consisting of three elements: a low-speed pulse generator, a high-speed pulse generator, and a pulse generator selector, all of which are on-chip with the VCSEL driver. By providing these elements on-chip, overall system power and complexity are reduced while allowing for significantly higher pulse train frequencies compared with known systems. The high-speed pulse generator is capable of generating pulses faster and with higher resolution than that of the low-speed pulse generator. The high-speed pulse generator uses multiple clock outputs, phase shifted, and synthesized into a single pulse waveform capable of wide-ranging frequencies, duty cycles and pulse counts.

An automatic gain adjustor for a hybrid oscillator can be employed to overcome the frequency limitations of hybrid phase lock loops (PLLs). For example, an automatic gain adjustor for a hybrid oscillator can include a hybrid oscillator that is configured to receive a coarse tuning signal and a gain adjustment signal and generate an output signal with any frequency within the specified frequency range of the hybrid PLL. The automatic gain adjustor for a hybrid PLL may further include a fine tuning array that receives one or more fine tuning selection signals and generates a gain adjustment signal that is received by the hybrid oscillator. The fine tuning array generates a gain adjustment signal to adjust the gain of the hybrid oscillator according to an operating frequency range of the hybrid oscillator.

The object of the present invention is to provide a phase noise and maximum oscillation frequency adjustable ring oscillator and a control method. The oscillator includes: a main path and a third auxiliary path; the third auxiliary path is connected to the main path for increasing the oscillation frequency; by inserting an adjustable inverter, when the frequency of the ring oscillator does not meet the requirements under extreme corner conditions, the oscillation frequency can be increased by sacrificing some phase noise by adjusting the inverter.

The invention provides a scanning window signal generating circuit, which comprises an oscillator for generating an oscillation signal; the scanning logic module is used for generating a plurality of scanning window signals based on the oscillation signals and feeding back the scanning window signals to the oscillator, so that the length of one oscillation period of the oscillation signal generated by the oscillator in the scanning window of each scanning window signal is a corresponding preset time length; the length of the scanning window of each scanning window signal is equal to the corresponding preset duration, and the scanning window of each scanning window signal corresponds to one oscillation period of the oscillation signal. Therefore, the lengths of the scanning windows of various scanning window signals can be flexibly set, and the circuit design complexity is reduced.

The application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit comprises a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit, wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generating circuit, and a gate end of the second transistor is connected to a drain end of the second transistor. Thus, the substrate end of the first transistor can output a potential which changes with any one of the supply voltage, the operating temperature and the manufacturing process.

An oscillator circuit (200) includes a ring oscillator (202) and a ramp generator (204). The ring oscillator (202) includes a first inverter (214) and a second inverter (218). The first inverter (214) has a first inverter input, a first inverter output, and a first power terminal. The second inverter (218) has a second inverter input, a second inverter output, and a second power terminal. The second inverter input is coupled to the first inverter output, and the second inverter output is coupled to the first inverter input. The ramp generator circuit (204) has a ramp output coupled to the first power terminal and the second power terminal.

The invention discloses a low-phase noise ring oscillator of a distributed network, which belongs to the technical field of integrated circuits, and comprises a first ring oscillator core, a second ring oscillator core and a third ring oscillator core which have the same structure, the first ring oscillator core, the second ring oscillator core and the third ring oscillator core are closed-loop structures formed by a plurality of phase inverters and a plurality of coupling units; a distributed coupling network is formed among the first ring oscillator core, the second ring oscillator core and the third ring oscillator core; the first input end of each coupling unit in the first ring oscillator core is connected with the second input end of the corresponding coupling unit in the third ring oscillator core, and the second input end of each coupling unit in the first ring oscillator core is connected with the first input end of the corresponding coupling unit in the second ring oscillator core; and the second input end of the coupling unit in the second ring oscillator core is connected with the first input end of the corresponding coupling unit in the third ring oscillator core. On the premise that power consumption and the chip area are not remarkably increased, the phase noise performance is remarkably improved.

According to one embodiment, an oscillation circuit includes: a ring oscillator; a first transistor having a gate terminal coupled to an output port of the ring oscillator and a drain terminal coupled to a first node; a second transistor having a drain terminal and a gate terminal that are both coupled to the first node; a third transistor having a gate terminal coupled to the first node and a drain terminal coupled to a second node; a fourth transistor having a gate terminal coupled to the first node and a drain terminal coupled to a third node; a fifth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node; and a voltage buffer having an input port coupled to the second node.

The invention relates to a fast latch based on logic isolation. The fast latch comprises a transmission gate module which adopts a plurality of transmission gates controlled by clock signals to transmit input signals to corresponding generation nodes. The generation module is used for generating a feedback node signal by adopting a plurality of mutually connected phase inverters; the feedback module is used for receiving feedback node signals and feeding back each feedback node signal to a corresponding generation node by adopting a cross feedback loop, and in a normal working state, when a clock signal is at a high level, the fast latch works in a transparent mode; when the clock CLK is at a low level, enabling the fast latch to work in a holding mode; and when a single node or double nodes are overturned, the quick latch is self-repaired. According to the latch, logic isolation is realized through a cross feedback loop, and soft errors can be repaired and correct data can be stored even if a radiation event occurs; the fast latch can provide complete DNU elasticity, and has a faster speed and a smaller area.

A circuit includes a voltage conversion unit from a power management unit library. The voltage conversion unit comprises a high-voltage domain subunit and a low-voltage domain subunit, wherein multiple high-voltage conversion modules in the high-voltage domain subunit and multiple low-voltage conversion modules in the low-voltage domain subunit are alternately connected to form a ring oscillator. The circuit includes a first control signal generation unit, a first selection output unit, a second control signal generation unit, and a second selection output unit. This invention enables efficient testing of the voltage conversion unit.

A control circuit for a ring oscillator, and a ring oscillation apparatus, relating to the field of oscillator signals. A power supply provides a power supply voltage for the ring oscillator by means of a reference voltage generation module and an operational amplifier, and a feedback control module regulates the voltage of a non-inverting input end of the operational amplifier on the basis of a real-time situation of the frequency of an output signal of the ring oscillator, thereby affecting the power supply voltage outputted by means of the operational amplifier to the ring oscillator. The frequency of the output signal of the ring oscillator is adjusted by regulating the power supply voltage to form feedback control on the output signal of the ring oscillator, and the frequency of the output signal of the ring oscillator is kept within a stable small range by means of feedback of dynamic adjustment, thereby improving the stability and reliability of the frequency of the output signal of the ring oscillator, reducing frequency distribution of the output signal of the ring oscillator, avoiding the impact of factors such as device parameters on the frequency of the output signal of the ring oscillator, and thus improving frequency accuracy.

The invention relates to operating point stabilization of VCO-ADC using switched capacitor frequency to current conversion. A circuit includes a micro-electro-mechanical system (MEMS) microphone configured to generate a voltage signal at an output terminal of the MEMS microphone in response to a sound signal; a voltage controlled oscillator (VCO) coupled to an output terminal of the MEMS microphone and configured to output a frequency modulated signal at an output terminal of the VCO, the frequency modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital (FTD) converter coupled to an output terminal of the VCO and configured to convert the frequency modulated signal to a frequency proportional digital output signal; a frequency voltage (FTV) conversion circuit coupled to an output terminal of the VCO and configured to generate a bias voltage at the output terminal of the FTV conversion circuit according to a frequency modulation signal; and a resistor coupled between the output terminal of the MEMS microphone and the output terminal of the FTV conversion circuit.

An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A1-A4) connected in a ring and has a first and a second supply terminal (s1, s2). Each amplifier circuit (A1-A4) comprises an input transistor (M1) whose gate is connected to an input (in) of the amplifier circuit, whose drain is connected to an internal node (x) of the amplifier circuit, and whose source is connected to the first supply terminal (s1). Furthermore, each amplifier circuit (A1-A4) comprises a first resonance circuit (R1) comprising a first inductor (L S ) and a first capacitor (C S ), wherein the first inductor (L S ) is connected between the internal node (x) and an output (out) of the amplifier circuit, and the first capacitor (C S ) is connected between the output (out) of the amplifier circuit and one of the first and second supply terminals (s1, s2). Furthermore, each amplifier circuit (A1-A4) comprises a second resonance circuit (R2) comprising a second inductor (L P ) and a second capacitor (C P ), wherein the second inductor (L P ) and the second capacitor (C P ) are connected in parallel between the internal node (x) and the second supply terminal (s2).

The present application relates to a semiconductor device and a control method thereof. A semiconductor device capable of self-diagnosing a clock monitoring circuit without increasing the size of the circuit is provided. According to one embodiment, the semiconductor device includes a first oscillator circuit, a clock monitoring circuit, and a timing signal generating circuit, which is used to periodically switch the operation mode of the clock monitoring circuit to one of a first mode to a third mode, and the clock monitoring circuit includes: a clock counter, which is configured to count the number of oscillations of the clock signal in the first mode, and is configured to shift the pulse of the input signal to the output signal in normal times in the third mode; a comparison circuit, which is used to compare whether the count value of the clock counter per predetermined period is within the expected value in the second mode; and an edge detection circuit, which is used to detect whether the pulse of the input signal is shifted to the output signal of the clock counter in the third mode.

An injection locked ring oscillator (ILRO) system is disclosed. The ILRO system includes an ILRO circuit configured to receive a plurality of injection control signals and a phase control signal, and to generate a plurality of output clock signals; a phase detector circuit configured to receive the output clock signals and to generate a phase output signal based on phase differences of particular pairs of the output clock signals; and a phase to voltage circuit configured to receive the phase output signal from the phase detector circuit, and to generate the phase control signal based on the phase output signal, where the phase control signal presents a negative feedback phase signal to the ILRO circuit for the phase differences in the particular pairs of the output clock signals.

An apparatus comprising a local oscillator (LO) for driving a mixer, the LO being configured to oscillate at an oscillation frequency, and generate a first set of LO signals, wherein each of the first set of LO signals has a LO signal frequency equal to a first multiplication factor m multiplied by the oscillation frequency, the first multiplication factor m, being an integer greater than or equal to two, and each of the first set of LO signals is separated by adjacent LO signals by a phase difference equal to 360° divided by a first variable n, the first variable n being an integer that is greater than or equal to two.

An apparatus includes a first inverter having an input terminal and an output terminal, a first capacitive device connected between the input terminal and the output terminal of the first inverter, and a resistor network coupled to the first capacitive device, wherein the first inverter is configured as a negative amplifier, and the first capacitive device and the resistor network are configured to determine a frequency of an oscillator.

The purpose of the present invention is to provide a pulse width adjustment circuit having a configuration capable of stably reducing phase noise.　A pulse width adjustment circuit according to the present technology comprises: a delay circuit that has a plurality of cascade-connected inverters and delays an input signal; a control circuit that controls at least two inverters including one inverter among the plurality of inverters; and an output circuit that outputs, as an injection signal, a logical operation result of a signal inputted to the one inverter and a signal outputted from the one inverter or a signal equivalent to the logical operation result.