261results about "Pulse generation by logic circuits" patented technology

The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking, relates to the technical field of integrated circuits, and is used for solving the technical problems that an existing injection locking oscillator limits the frequency tuning range and cannot effectively suppress noise. The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking. The low-phase noise ring voltage-controlled oscillator comprises a first ring oscillator unit and a second ring oscillator unit, the n first ring oscillator units are connected in series to form a chain structure; the second ring oscillator unit is provided with a cross coupling inverter complementary injection unit and a tail current source injection unit; a first output end of the chain structure is connected with a second input end of the second ring oscillator unit, and a second output end of the chain structure is connected with a first input end of the second ring oscillator unit; a first signal is injected into a cross-coupling inverter complementary injection unit and a tail current source injection unit, and a second ring oscillator unit receives a second signal output by a chain structure and then outputs a third signal.

The invention belongs to the technical field of electronic circuits, and particularly relates to an oscillator circuit for a PWM controller. Comprising an oscillator module which comprises a feedback loop and a current detection circuit; the hiccup module is used for gating and outputting an input signal by a data selector according to the level of the input PWM logic control signal so as to control the on-off of a transmission gate, establishing a charging and discharging process and providing a delay starting function for the oscillator module; and the jittering frequency module outputs current sources Iref0 of different sizes by performing combined gating on a current source I'ref and current sources I1-I4, outputs four paths of current sources Iref1-Iref4 of different sizes through a current mirror array mirror image, and provides charging and discharging current for the oscillator module and the hiccup module. By dynamically adjusting the PWM frequency, the switching frequency is matched with the load requirement, the invalid switching frequency is reduced, and the power consumption is greatly reduced.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

The invention relates to a passive wireless temperature sensor circuit, which comprises a transceiving antenna, an RF-DC rectifier circuit, a temperature sensing circuit and a backscatter circuit, the RF-DC rectifier circuit receives external radio frequency energy based on the transmit-receive antenna and then outputs direct current for power supply. The temperature sensing circuit comprises a complementary absolute temperature voltage generator and a ring oscillator; the complementary absolute temperature voltage generator comprises an MOS tube and generates CTAT voltage based on temperature characteristics of the MOS tube. The ring oscillator converts the CTAT voltage into an oscillation frequency signal of the ring oscillator and then outputs a square wave frequency signal with a negative temperature coefficient; the backscattering circuit backscatters the square wave frequency signal through the transceiving antenna; the CTAT key generation circuit built by the MOS tube generates CTAT voltage, a temperature frequency conversion chain is built through the CTAT voltage and the ring oscillator, temperature information is converted into frequency information of the oscillator, the power consumption of the temperature sensing circuit can be effectively reduced, and meanwhile the voltage coefficient of the CTAT voltage is increased by combining the temperature characteristic of the MOS tube.

Aspects of the disclosure are directed to voltage sensing for safety-critical applications. In accordance with one aspect, the disclosure includes a multi-phase ring oscillator (RO) configured to operate in a first voltage domain; a frequency counter coupled to the multi-phase RO, the frequency counter configured to accumulate a plurality of phase cycles from the multi-phase RO over a time duration to generate a digital count word; an alarm processor coupled to the frequency counter, the alarm processor configured to receive an alarm state signal from the frequency counter; and a heartbeat detector coupled to the multi-phase RO, the heartbeat detector configured to operate in a second voltage domain and configured to detect a periodic recurrence of a heartbeat pulse to determine an integrity of the sensor function as a whole and alarm state signal in particular.

A level shifter includes a first buffer circuit, a first capacitor, a second capacitor, a cross-coupled inverter, and a second buffer circuit. The first buffer circuit is configured to drive a first input signal and a second input signal with a first high power supply voltage and a first low power supply voltage to generate a first main driving signal and a second main driving signal. The first capacitor, the second capacitor, and the cross-coupled inverter are configured to generate signals of a first node and a second node based on the first and second main driving signals. The second buffer circuit is configured to drive the signals of the first and second nodes with a second high power supply voltage and a second low power supply voltage to generate a first output signal and a second output signal.

A layered pulse generator for a vertical-cavity surface-emitting laser (“VCSEL”) driver is disclosed consisting of three elements: a low-speed pulse generator, a high-speed pulse generator, and a pulse generator selector, all of which are on-chip with the VCSEL driver. By providing these elements on-chip, overall system power and complexity are reduced while allowing for significantly higher pulse train frequencies compared with known systems. The high-speed pulse generator is capable of generating pulses faster and with higher resolution than that of the low-speed pulse generator. The high-speed pulse generator uses multiple clock outputs, phase shifted, and synthesized into a single pulse waveform capable of wide-ranging frequencies, duty cycles and pulse counts.

An automatic gain adjustor for a hybrid oscillator can be employed to overcome the frequency limitations of hybrid phase lock loops (PLLs). For example, an automatic gain adjustor for a hybrid oscillator can include a hybrid oscillator that is configured to receive a coarse tuning signal and a gain adjustment signal and generate an output signal with any frequency within the specified frequency range of the hybrid PLL. The automatic gain adjustor for a hybrid PLL may further include a fine tuning array that receives one or more fine tuning selection signals and generates a gain adjustment signal that is received by the hybrid oscillator. The fine tuning array generates a gain adjustment signal to adjust the gain of the hybrid oscillator according to an operating frequency range of the hybrid oscillator.

The application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit comprises a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit, wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generating circuit, and a gate end of the second transistor is connected to a drain end of the second transistor. Thus, the substrate end of the first transistor can output a potential which changes with any one of the supply voltage, the operating temperature and the manufacturing process.

The invention discloses a low-phase noise ring oscillator of a distributed network, which belongs to the technical field of integrated circuits, and comprises a first ring oscillator core, a second ring oscillator core and a third ring oscillator core which have the same structure, the first ring oscillator core, the second ring oscillator core and the third ring oscillator core are closed-loop structures formed by a plurality of phase inverters and a plurality of coupling units; a distributed coupling network is formed among the first ring oscillator core, the second ring oscillator core and the third ring oscillator core; the first input end of each coupling unit in the first ring oscillator core is connected with the second input end of the corresponding coupling unit in the third ring oscillator core, and the second input end of each coupling unit in the first ring oscillator core is connected with the first input end of the corresponding coupling unit in the second ring oscillator core; and the second input end of the coupling unit in the second ring oscillator core is connected with the first input end of the corresponding coupling unit in the third ring oscillator core. On the premise that power consumption and the chip area are not remarkably increased, the phase noise performance is remarkably improved.

According to one embodiment, an oscillation circuit includes: a ring oscillator; a first transistor having a gate terminal coupled to an output port of the ring oscillator and a drain terminal coupled to a first node; a second transistor having a drain terminal and a gate terminal that are both coupled to the first node; a third transistor having a gate terminal coupled to the first node and a drain terminal coupled to a second node; a fourth transistor having a gate terminal coupled to the first node and a drain terminal coupled to a third node; a fifth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node; and a voltage buffer having an input port coupled to the second node.

A circuit includes a voltage conversion unit from a power management unit library. The voltage conversion unit comprises a high-voltage domain subunit and a low-voltage domain subunit, wherein multiple high-voltage conversion modules in the high-voltage domain subunit and multiple low-voltage conversion modules in the low-voltage domain subunit are alternately connected to form a ring oscillator. The circuit includes a first control signal generation unit, a first selection output unit, a second control signal generation unit, and a second selection output unit. This invention enables efficient testing of the voltage conversion unit.

A control circuit for a ring oscillator, and a ring oscillation apparatus, relating to the field of oscillator signals. A power supply provides a power supply voltage for the ring oscillator by means of a reference voltage generation module and an operational amplifier, and a feedback control module regulates the voltage of a non-inverting input end of the operational amplifier on the basis of a real-time situation of the frequency of an output signal of the ring oscillator, thereby affecting the power supply voltage outputted by means of the operational amplifier to the ring oscillator. The frequency of the output signal of the ring oscillator is adjusted by regulating the power supply voltage to form feedback control on the output signal of the ring oscillator, and the frequency of the output signal of the ring oscillator is kept within a stable small range by means of feedback of dynamic adjustment, thereby improving the stability and reliability of the frequency of the output signal of the ring oscillator, reducing frequency distribution of the output signal of the ring oscillator, avoiding the impact of factors such as device parameters on the frequency of the output signal of the ring oscillator, and thus improving frequency accuracy.

The invention relates to operating point stabilization of VCO-ADC using switched capacitor frequency to current conversion. A circuit includes a micro-electro-mechanical system (MEMS) microphone configured to generate a voltage signal at an output terminal of the MEMS microphone in response to a sound signal; a voltage controlled oscillator (VCO) coupled to an output terminal of the MEMS microphone and configured to output a frequency modulated signal at an output terminal of the VCO, the frequency modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital (FTD) converter coupled to an output terminal of the VCO and configured to convert the frequency modulated signal to a frequency proportional digital output signal; a frequency voltage (FTV) conversion circuit coupled to an output terminal of the VCO and configured to generate a bias voltage at the output terminal of the FTV conversion circuit according to a frequency modulation signal; and a resistor coupled between the output terminal of the MEMS microphone and the output terminal of the FTV conversion circuit.

An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A1-A4) connected in a ring and has a first and a second supply terminal (s1, s2). Each amplifier circuit (A1-A4) comprises an input transistor (M1) whose gate is connected to an input (in) of the amplifier circuit, whose drain is connected to an internal node (x) of the amplifier circuit, and whose source is connected to the first supply terminal (s1). Furthermore, each amplifier circuit (A1-A4) comprises a first resonance circuit (R1) comprising a first inductor (L S ) and a first capacitor (C S ), wherein the first inductor (L S ) is connected between the internal node (x) and an output (out) of the amplifier circuit, and the first capacitor (C S ) is connected between the output (out) of the amplifier circuit and one of the first and second supply terminals (s1, s2). Furthermore, each amplifier circuit (A1-A4) comprises a second resonance circuit (R2) comprising a second inductor (L P ) and a second capacitor (C P ), wherein the second inductor (L P ) and the second capacitor (C P ) are connected in parallel between the internal node (x) and the second supply terminal (s2).

An apparatus includes a first inverter having an input terminal and an output terminal, a first capacitive device connected between the input terminal and the output terminal of the first inverter, and a resistor network coupled to the first capacitive device, wherein the first inverter is configured as a negative amplifier, and the first capacitive device and the resistor network are configured to determine a frequency of an oscillator.

A method for operating a fast start-up oscillator system, which includes a reference oscillator and a quartz oscillator connected to an electronic oscillator circuit, which is provided to supply a master clock signal to a start-up controller configured to perform a fast start-up procedure of the quartz oscillator via the reference oscillator. The start-up controller includes a calculation unit and a memory unit for storing data in connection with the reference oscillator for starting the quartz oscillator. The method includes parameterising the calculation unit for starting the quartz oscillator, generating excitation bursts, determining a phase deviation in different successive periods between the oscillation of the reference oscillator and the oscillation of the quartz oscillator, calculating a frequency error in the calculation unit, and correcting the frequency of the reference oscillator to the frequency of the quartz oscillator.

The invention discloses a delay unit and a broadband multi-sub-band ring oscillator circuit, the delay unit is characterized in that a PM5, a PM7, a PM13 and a first current limiting tube are connected in parallel between a source electrode and a drain electrode of a PM3, the first current limiting tube comprises a PM9, a PM11 and sub-band control switches CB2 and CB12, a PM6, a PM8, a PM14 and a second current limiting tube are connected in parallel between a source electrode and a drain electrode of a PM4, and the second current limiting tube comprises a PM10, a PM12 and sub-band control switches CB2 and CB12; switched capacitors C1-C4 are arranged between the VOP and the VON; the first group of switched capacitors and the second group of switched capacitors are connected in parallel between the VOP and the VON; the first group of switched capacitors comprises C1 and C2 which are connected in series and CB1 for controlling the switching of the C1 and C2, and the second group of switched capacitors comprises C3 and C4 which are connected in series and CB2 for controlling the switching of the C3 and C4; grid electrodes of the PM5 and the PM6 are connected with the sub-band control switch RB1, grid electrodes of the PM7 and the PM8 are connected with the RB2, grid electrodes of the PM9 and the PM10 are connected with the CB2, grid electrodes of the PM11 and the PM12 are connected with the CB12, and a control signal of the CB12 is generated by control signals of the CB1 and the CB2 through an AND gate.

The invention discloses a voltage-controlled oscillator, which belongs to the technical field of electronic circuits and comprises a source follower circuit, a pull-down circuit, a pull-up circuit and a plurality of delay circuits. The source follower circuit generates a regulating voltage according to a control voltage and an enable signal. When the regulating voltage conducts a first path in the pull-down circuit, the pull-down circuit pulls down the level of a first node to the ground so as to generate a pull-down signal through the first node. When the regulating voltage conducts a second path in the pull-up circuit, the pull-up circuit transmits the regulating voltage to a second node so as to generate a pull-up signal through the second node. The plurality of delay circuits are configured as a ring oscillator and are started according to the pull-down signal and the pull-up signal so as to generate an output oscillation signal according to the control voltage.

The application provides a ring oscillator circuit, comprising: a bias circuit and a delay circuit; the bias circuit is used for generating a first bias current and a second bias current, the first bias current is inversely proportional to a voltage drop resistance in the bias circuit and is proportional to a square root of a reference current; in the delay circuit, a first input end of a delay control circuit is used for obtaining the first bias current, and a second input end is used for obtaining the second bias current; a first capacitor is arranged in the delay control circuit, so that a rising delay time of an output end of the delay control circuit is proportional to the first capacitor, inversely proportional to the first bias current and proportional to a flip threshold of a delay inverter in the delay control circuit, wherein the flip threshold of the delay inverter is proportional to the square root of the reference current, so that an oscillation period of the ring oscillator circuit is mainly determined by the proportion of the resistance, the capacitance and the square root of the reference current in the circuit, and the relationship between the oscillation period and the size of the reference current is weakened.

The embodiment of the utility model relates to a scan chain circuit and a control circuit for loading a repetitive sequence to a trigger. The scan chain circuit is used for inputting a repetitive bit sequence to a trigger sequence comprising a multi-bit trigger and a unit trigger. One example includes a control circuit including a bit counter, a multiplexer, a first set of control circuits, and a second set of control circuits.

In the present invention, cross-coupled latches 15, 25, 35 are each formed by counter connection between multiple outputs A1-A3 of first inverters 11, 21, 31 and multiple outputs B1-B3 of second inverters 12, 22, 32. When controlled by a control circuit 50, a first output A1 of the first inverter 11 in a first loop L1 is pulled down to an L level, and a second output B2 of the second inverter 22 in a second loop L2 is also pulled down to the L level, thus achieving an initial reset state.

Circuits and methods that enable a charge pump to provide sufficient charge to the gate of a switch NFET to turn the NFET ON within a specified switching time requirement but with minimal generation of electronic noise. An embodiment includes a dual-oscillator circuit configured to output from a first oscillator a first frequency signal from a first oscillator during normal operation, and to output from a second oscillator a second frequency signal higher in frequency than the first frequency signal for a selected time determined by a counter. An embodiment includes a charge pump coupled to the dual-oscillator circuit and configured to output an electrical charge as a function of an applied frequency signal from the dual-oscillator circuit, wherein application of the second frequency signal output during counting increases the amount of electrical charge output by the charge pump.

The application discloses a ring type voltage-controlled oscillator and a multi-mode receiver, the ring type voltage-controlled oscillator comprising three double-path structure delay units connected in sequence, adopting a new structure of double common-source stages plus NMOS tube source following feedback, so that output noise voltage or current can be offset, and phase noise is reduced; meanwhile, the ring type voltage-controlled oscillator adds a varactor pair and a capacitor switch array at an output end, frequency tuning of the circuit can be realized by introducing the varactor and a tuning voltage, and the tuning range of the ring type voltage-controlled oscillator can be further increased through the capacitor switch array; and the ring type voltage-controlled oscillator further adds a biased I-MOS varactor pair in parallel on the basis of the A-MOS varactor pair, so that the poor capacitance characteristic of the A-MOS varactor can be compensated by the I-MOS varactor, and the tuning linearity of the ring type voltage-controlled oscillator can be optimized.

The application discloses a voltage-controlled oscillator and electronic equipment, the voltage-controlled oscillator comprises a sampling module, a voltage lifting module and an oscillator module; the sampling module is connected with the voltage lifting module, and the voltage lifting module is connected with the oscillator module; wherein the sampling module is used for inputting a clock signal and maintaining a voltage unchanged during a low voltage period of the clock signal; the voltage lifting module is used for lifting an input voltage signal; the oscillator module comprises a frequency control unit and an inverter chain; the frequency control unit is used for controlling an oscillation frequency and performing a one-phase transformation on a signal; the inverter chain is used for performing a signal delay and inversion; and the inverter chain comprises a plurality of inverter devices connected in sequence. The voltage-controlled oscillator does not need to use a power supply voltage as a control voltage, the oscillation amplitude is more stable, and sampling application can be conveniently and efficiently realized. The application can be widely applied in the technical field of electronic equipment.

Embodiments of the present invention relate to a multiphase oscillator circuit. In the described example, a ring oscillator (110) comprises a series of N stages in a first ring. Each stage includes a corresponding output (112, 114, 116), which is coupled to a corresponding input of the next stage in the first ring. N is a positive odd integer of at least three. A series of N level shifters (L1, L2, LN) in a second ring are respectively connected to the N stages. Each level shifter (L1, L2, LN) receives a corresponding clock output from the corresponding output (L1, L2, LN) of the stage to which it is connected and generates a corresponding boosted clock output (130) in response to the clock output. The boosted clock output (130) is coupled to control the impedance state of the next level shifter in the second ring.

This invention provides a superconducting voltage drive circuit and electronic product, comprising: an SFQ pulse input module that generates complementary set and reset signals based on SFQ pulses; each RS flip-flop that receives a set pulse and a reset pulse respectively, generating a magnetic flux quantum when the set pulse arrives and releasing the magnetic flux quantum when the reset pulse arrives; a series structure of asymmetric SQUID superconducting rings cascaded sequentially; a bias current source that provides DC bias to each asymmetric SQUID superconducting ring; each asymmetric SQUID superconducting ring correspondingly sensing the magnetic flux quantum in its respective RS flip-flop and generating a corresponding output voltage under the action of the bias current source; the voltages output by each asymmetric SQUID superconducting ring are superimposed to form a total output voltage, which is transmitted to an external receiving circuit via a transmission line; and a load RL connected to the output terminal of the series structure, representing the input impedance of the transmission line. This invention employs an asymmetric SQUID design, resulting in high output swing, fast operating speed, small circuit area, compact structure, and wide applicability.

A memory device may include memory cell array a clock circuit configured to generate a plurality of clock signals for access operations associated with the memory cell array. The clock circuit may include a ring oscillator circuit that is configured to equalize phase distortions of the plurality of clock signals.

An inverter and a ring oscillator (100) comprising a plurality of the inverters arranged in a ring is disclosed. Each inverter (200) comprises an inverter input (210) and an inverter output (220), wherein the inverter output (220) of each inverter (200) in the ring is coupled to the inverter input (210) of the respective next inverter (200) in the ring. At least one (200) of the plurality of inverters comprises: a first NMOS transistor (250), comprising a first gate terminal (252) coupled to the respective inverter input (210), a first drain terminal (254) coupled to the respective inverter output (220), and a first source terminal (256); and a second NMOS transistor (260), comprising a second gate terminal (262), a second drain terminal (264) and a second source terminal (266), wherein said second source terminal (266) is coupled to said first drain terminal (254).

The present disclosure provides a multi-phase clock circuit and a multi-phase clock signal generation method, which are applied to the field of integrated circuit technology. The multi-phase clock circuit includes: an injection switch control module configured to obtain an injection mode control signal representing a frequency injection ratio; an injection switch selection module configured to determine the injection phase of a four-phase injection clock signal according to the injection mode control signal; a buffer configured to input the four-phase injection clock signal into a ring oscillator according to the injection phase; the ring oscillator configured to generate N phase clock signals based on the four-phase injection clock signal and input the N phase clock signals into a phase detector; the phase detector configured to extract phase deviation information from the N phase clock signals; and a frequency matching control module configured to tune the ring oscillator according to the injection mode control signal, the frequency of the four-phase injection clock signal, and the phase deviation information. According to embodiments of the present disclosure, the frequency range of the clock signal can be widened.