145results about "Pulse generation by logic circuits" patented technology

A level shifter includes a first buffer circuit, a first capacitor, a second capacitor, a cross-coupled inverter, and a second buffer circuit. The first buffer circuit is configured to drive a first input signal and a second input signal with a first high power supply voltage and a first low power supply voltage to generate a first main driving signal and a second main driving signal. The first capacitor, the second capacitor, and the cross-coupled inverter are configured to generate signals of a first node and a second node based on the first and second main driving signals. The second buffer circuit is configured to drive the signals of the first and second nodes with a second high power supply voltage and a second low power supply voltage to generate a first output signal and a second output signal.

A layered pulse generator for a vertical-cavity surface-emitting laser (“VCSEL”) driver is disclosed consisting of three elements: a low-speed pulse generator, a high-speed pulse generator, and a pulse generator selector, all of which are on-chip with the VCSEL driver. By providing these elements on-chip, overall system power and complexity are reduced while allowing for significantly higher pulse train frequencies compared with known systems. The high-speed pulse generator is capable of generating pulses faster and with higher resolution than that of the low-speed pulse generator. The high-speed pulse generator uses multiple clock outputs, phase shifted, and synthesized into a single pulse waveform capable of wide-ranging frequencies, duty cycles and pulse counts.

The application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit comprises a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit, wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generating circuit, and a gate end of the second transistor is connected to a drain end of the second transistor. Thus, the substrate end of the first transistor can output a potential which changes with any one of the supply voltage, the operating temperature and the manufacturing process.

The invention discloses a low-phase noise ring oscillator of a distributed network, which belongs to the technical field of integrated circuits, and comprises a first ring oscillator core, a second ring oscillator core and a third ring oscillator core which have the same structure, the first ring oscillator core, the second ring oscillator core and the third ring oscillator core are closed-loop structures formed by a plurality of phase inverters and a plurality of coupling units; a distributed coupling network is formed among the first ring oscillator core, the second ring oscillator core and the third ring oscillator core; the first input end of each coupling unit in the first ring oscillator core is connected with the second input end of the corresponding coupling unit in the third ring oscillator core, and the second input end of each coupling unit in the first ring oscillator core is connected with the first input end of the corresponding coupling unit in the second ring oscillator core; and the second input end of the coupling unit in the second ring oscillator core is connected with the first input end of the corresponding coupling unit in the third ring oscillator core. On the premise that power consumption and the chip area are not remarkably increased, the phase noise performance is remarkably improved.

A circuit includes a voltage conversion unit from a power management unit library. The voltage conversion unit comprises a high-voltage domain subunit and a low-voltage domain subunit, wherein multiple high-voltage conversion modules in the high-voltage domain subunit and multiple low-voltage conversion modules in the low-voltage domain subunit are alternately connected to form a ring oscillator. The circuit includes a first control signal generation unit, a first selection output unit, a second control signal generation unit, and a second selection output unit. This invention enables efficient testing of the voltage conversion unit.

A control circuit for a ring oscillator, and a ring oscillation apparatus, relating to the field of oscillator signals. A power supply provides a power supply voltage for the ring oscillator by means of a reference voltage generation module and an operational amplifier, and a feedback control module regulates the voltage of a non-inverting input end of the operational amplifier on the basis of a real-time situation of the frequency of an output signal of the ring oscillator, thereby affecting the power supply voltage outputted by means of the operational amplifier to the ring oscillator. The frequency of the output signal of the ring oscillator is adjusted by regulating the power supply voltage to form feedback control on the output signal of the ring oscillator, and the frequency of the output signal of the ring oscillator is kept within a stable small range by means of feedback of dynamic adjustment, thereby improving the stability and reliability of the frequency of the output signal of the ring oscillator, reducing frequency distribution of the output signal of the ring oscillator, avoiding the impact of factors such as device parameters on the frequency of the output signal of the ring oscillator, and thus improving frequency accuracy.

An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A1-A4) connected in a ring and has a first and a second supply terminal (s1, s2). Each amplifier circuit (A1-A4) comprises an input transistor (M1) whose gate is connected to an input (in) of the amplifier circuit, whose drain is connected to an internal node (x) of the amplifier circuit, and whose source is connected to the first supply terminal (s1). Furthermore, each amplifier circuit (A1-A4) comprises a first resonance circuit (R1) comprising a first inductor (L S ) and a first capacitor (C S ), wherein the first inductor (L S ) is connected between the internal node (x) and an output (out) of the amplifier circuit, and the first capacitor (C S ) is connected between the output (out) of the amplifier circuit and one of the first and second supply terminals (s1, s2). Furthermore, each amplifier circuit (A1-A4) comprises a second resonance circuit (R2) comprising a second inductor (L P ) and a second capacitor (C P ), wherein the second inductor (L P ) and the second capacitor (C P ) are connected in parallel between the internal node (x) and the second supply terminal (s2).

The invention discloses a voltage-controlled oscillator, which belongs to the technical field of electronic circuits and comprises a source follower circuit, a pull-down circuit, a pull-up circuit and a plurality of delay circuits. The source follower circuit generates a regulating voltage according to a control voltage and an enable signal. When the regulating voltage conducts a first path in the pull-down circuit, the pull-down circuit pulls down the level of a first node to the ground so as to generate a pull-down signal through the first node. When the regulating voltage conducts a second path in the pull-up circuit, the pull-up circuit transmits the regulating voltage to a second node so as to generate a pull-up signal through the second node. The plurality of delay circuits are configured as a ring oscillator and are started according to the pull-down signal and the pull-up signal so as to generate an output oscillation signal according to the control voltage.

The application provides a ring oscillator circuit, comprising: a bias circuit and a delay circuit; the bias circuit is used for generating a first bias current and a second bias current, the first bias current is inversely proportional to a voltage drop resistance in the bias circuit and is proportional to a square root of a reference current; in the delay circuit, a first input end of a delay control circuit is used for obtaining the first bias current, and a second input end is used for obtaining the second bias current; a first capacitor is arranged in the delay control circuit, so that a rising delay time of an output end of the delay control circuit is proportional to the first capacitor, inversely proportional to the first bias current and proportional to a flip threshold of a delay inverter in the delay control circuit, wherein the flip threshold of the delay inverter is proportional to the square root of the reference current, so that an oscillation period of the ring oscillator circuit is mainly determined by the proportion of the resistance, the capacitance and the square root of the reference current in the circuit, and the relationship between the oscillation period and the size of the reference current is weakened.

The embodiment of the utility model relates to a scan chain circuit and a control circuit for loading a repetitive sequence to a trigger. The scan chain circuit is used for inputting a repetitive bit sequence to a trigger sequence comprising a multi-bit trigger and a unit trigger. One example includes a control circuit including a bit counter, a multiplexer, a first set of control circuits, and a second set of control circuits.

Circuits and methods that enable a charge pump to provide sufficient charge to the gate of a switch NFET to turn the NFET ON within a specified switching time requirement but with minimal generation of electronic noise. An embodiment includes a dual-oscillator circuit configured to output from a first oscillator a first frequency signal from a first oscillator during normal operation, and to output from a second oscillator a second frequency signal higher in frequency than the first frequency signal for a selected time determined by a counter. An embodiment includes a charge pump coupled to the dual-oscillator circuit and configured to output an electrical charge as a function of an applied frequency signal from the dual-oscillator circuit, wherein application of the second frequency signal output during counting increases the amount of electrical charge output by the charge pump.

The application discloses a voltage-controlled oscillator and electronic equipment, the voltage-controlled oscillator comprises a sampling module, a voltage lifting module and an oscillator module; the sampling module is connected with the voltage lifting module, and the voltage lifting module is connected with the oscillator module; wherein the sampling module is used for inputting a clock signal and maintaining a voltage unchanged during a low voltage period of the clock signal; the voltage lifting module is used for lifting an input voltage signal; the oscillator module comprises a frequency control unit and an inverter chain; the frequency control unit is used for controlling an oscillation frequency and performing a one-phase transformation on a signal; the inverter chain is used for performing a signal delay and inversion; and the inverter chain comprises a plurality of inverter devices connected in sequence. The voltage-controlled oscillator does not need to use a power supply voltage as a control voltage, the oscillation amplitude is more stable, and sampling application can be conveniently and efficiently realized. The application can be widely applied in the technical field of electronic equipment.

This invention provides a superconducting voltage drive circuit and electronic product, comprising: an SFQ pulse input module that generates complementary set and reset signals based on SFQ pulses; each RS flip-flop that receives a set pulse and a reset pulse respectively, generating a magnetic flux quantum when the set pulse arrives and releasing the magnetic flux quantum when the reset pulse arrives; a series structure of asymmetric SQUID superconducting rings cascaded sequentially; a bias current source that provides DC bias to each asymmetric SQUID superconducting ring; each asymmetric SQUID superconducting ring correspondingly sensing the magnetic flux quantum in its respective RS flip-flop and generating a corresponding output voltage under the action of the bias current source; the voltages output by each asymmetric SQUID superconducting ring are superimposed to form a total output voltage, which is transmitted to an external receiving circuit via a transmission line; and a load RL connected to the output terminal of the series structure, representing the input impedance of the transmission line. This invention employs an asymmetric SQUID design, resulting in high output swing, fast operating speed, small circuit area, compact structure, and wide applicability.

An inverter and a ring oscillator (100) comprising a plurality of the inverters arranged in a ring is disclosed. Each inverter (200) comprises an inverter input (210) and an inverter output (220), wherein the inverter output (220) of each inverter (200) in the ring is coupled to the inverter input (210) of the respective next inverter (200) in the ring. At least one (200) of the plurality of inverters comprises: a first NMOS transistor (250), comprising a first gate terminal (252) coupled to the respective inverter input (210), a first drain terminal (254) coupled to the respective inverter output (220), and a first source terminal (256); and a second NMOS transistor (260), comprising a second gate terminal (262), a second drain terminal (264) and a second source terminal (266), wherein said second source terminal (266) is coupled to said first drain terminal (254).

A ring oscillator has a first group of inverters that receive respective frequency control signals to control delays through the inverters. The frequency of the ring oscillator is dithered according to least significant bits of a frequency control word supplied by a loop filter of a phase-locked loop. Most significant bits of the frequency control word are used to generate the frequency control signals. An accumulator is clocked by an output of the ring oscillator and accumulates the least significant bits of the frequency control word. A selector circuit selects either N most significant bits of the frequency control word or the N most significant bits of the frequency control word +1 according to the selector signal to generate the frequency control signals.

A frequency detector (200) and a method thereof for measuring and tuning the frequency of a controlled oscillator are disclosed. The frequency detector (200) includes: a pulse generator (210) for generating sampling pulses; a sampling circuit system (220) for sampling the output state of the controlled oscillator (180); and a digital processing unit (230). The sampling circuit system (220) is configured to subsample the output state of the controlled oscillator (180) at two or more sampling frequencies, all of which are lower than the frequency of the controlled oscillator. The digital processing unit (230) is configured to calculate the frequency offset of the oscillator based on the sampled states, and to generate a control signal based on the frequency offset to tune the frequency of the oscillator.

The present specification provides a circuit architecture, an oscillator, a chip, and an electronic device. The circuit architecture comprises: an oscillation circuit having at least one oscillation loop, the oscillation loop comprising at least one frequency modulation node; the at least one frequency modulation unit comprises a control subunit and an energy storage subunit; the control subunit is provided with a first end, a second end and a control end; the first end is electrically connected with the frequency modulation node, and the second end is electrically connected with the first end of the energy storage subunit; the control end is configured to receive a control voltage; the second end of the energy storage subunit is electrically connected with a reference potential end; and the control subunit is configured to respond to the control voltage and adjust the energy storage subunit so as to enable the equivalent capacitance at the frequency modulation node to change along with the control voltage. The circuit architecture has the advantages that the structure is simple, and the output frequency linearity can be kept in a wide voltage range.

The apparatus includes: a ring oscillator including a set of cascaded current-starved inverters arranged in a ring; a set of field effect transistors (FETs) coupled in series with the set of cascaded current-starved inverters between an upper voltage rail and a lower voltage rail, respectively; a negative to absolute temperature (NTAT) current source configured to generate a NTAT current; and one or more current mirrors coupling the NTAT current source to the set of FETs.

The embodiment of the invention relates to a ring oscillator. A ring oscillator generates an output signal having a frequency controlled by a first frequency control current applied to a frequency control terminal. A first transistor of a first conductivity type receives a control voltage on a control terminal and supplies a first frequency control current at a first conductive terminal. A second transistor of a second conductivity type opposite the first conductivity type also receives the control voltage on the control terminal and supplies a second current to a second conductive terminal of the first transistor.

The application discloses a low-power-consumption mixing-priority type wideband receiver front-end module, which is based on a mixing-priority architecture, does not need to use an external matching network, realizes impedance matching from an antenna to a receiver front end, realizes high-Q band-pass filtering characteristics, and comprises a third harmonic mixer, a 12-stage ring voltage-controlled oscillator and a TIA transimpedance operational amplifier.The third harmonic mixer is connected with the 12-stage ring voltage-controlled oscillator and the TIA transimpedance operational amplifier.The 12-stage ring voltage-controlled oscillator provides a required local oscillator signal for the third harmonic mixer.The third harmonic mixer is used for down-converting an RF radio frequency signal into a zero intermediate frequency signal by using a third harmonic component of the local oscillator.The TIA transimpedance operational amplifier is used for effectively amplifying and filtering a zero intermediate frequency signal down-converted by the third harmonic mixer and then outputting the zero intermediate frequency signal.The application has lower power consumption than a conventional wideband receiver.

The invention discloses a PUF (Physical Unclonable Function) circuit based on a ring oscillator and a design method thereof, and belongs to the technical field of integrated circuits, the ring oscillator comprises an NAND gate and n phase inverters, the n phase inverters are connected end to end in series to form a linear structure, a first input end of the NAND gate is used for accessing input voltage, and a second input end of the NAND gate is used for accessing output voltage; the output end of the NAND gate is connected with the input end of the linear structure, the output end of the linear structure is used for providing output voltage, and the output end of the NAND gate and the output end of each phase inverter are grounded through the external capacitor. The ring oscillators with different stages are formed by using the NAND gate and the n phase inverters, the circuits of the ring oscillators are compensated by using the externally-hung capacitors, the output time delay of output voltage can be reduced by setting the proper number of the phase inverters and the capacitance value of the externally-hung capacitors, and the PUFRO operation speed can be accelerated by enabling oscillation signals to enter the multiplexer.

The present disclosure relates to direct time-of-flight (DTOF) sensors and time to digital converters (TDCs) for a DTOF. The disclosure presents an oscillation circuit array for such a TDC. The oscillation circuit array comprises a plurality of oscillators designed identically to each other, and at least two wiring lines. Each wiring line is configured to connect the plurality of oscillators. A first wiring line is arranged to form a first closed path that passes through each of the plurality of oscillators once, and a second wiring line is arranged to form a second closed path that passes through each of the plurality of oscillators once and is different from the first closed path. Further, the plurality of oscillators is designed to oscillate at a same frequency and are synchronized in phase.

The embodiments of the present application relate to the technical field of electronics. Provided are a ring oscillator and a communication apparatus, which can realize low power consumption and low phase noise. The ring oscillator comprises a first delay cell array, a second delay cell array, a first current source, a second current source, a first switch, and a second switch, wherein current in the first current source is less than current in the second current source. An output end of the first current source is coupled to a power supply end of the first delay cell array by means of the first switch, and an output end of the second current source is coupled to a power supply end of the second delay cell array by means of the second switch; when the second switch is turned on and the first switch is turned off, the second delay cell array operates; and when the second switch is turned off and the first switch is turned on, the first delay cell array operates.

This application relates to the field of electronic technologies, and provides a ring oscillator and a communication apparatus, to reduce phase noise of the ring oscillator and improve performance of the ring oscillator. The ring oscillator includes at least three differential inverting amplifiers that are coupled in a ring. A first output end and a second output end of each differential inverting amplifier are respectively coupled to a first input end and a second input end of a next adjacent differential inverting amplifier. The at least three differential inverting amplifiers include a first differential inverting amplifier, a first input end of the first differential inverting amplifier is coupled to a first output end of the first differential inverting amplifier, and a second input end of the first differential inverting amplifier is coupled to a second output end of the first differential inverting amplifier. A polarity of the first input end and a polarity of the first output end are a first polarity, a polarity of the second input end and a polarity of the second output end are a second polarity, and the first polarity is opposite to the second polarity.

An electronic circuit (200) is provided that is a high-speed CMOS logic circuit for frequency division of an input signal. The electronic circuit comprises a ring oscillator (201). The ring oscillator (201) comprises a plurality of gated inverters. At least one of the gated inverters (290) is configured to receive an oscillation signal (281) and a control signal at two complementary inputs. The electronic circuit (200) is configured to be partially gated such that the division ratio is selectable. A very high-speed multi-mode clock divider is achieved by clock partial gating, open-loop clock buffering, and avoiding slow combinatorial logic in the data path.

A frequency multiplier includes a first ring oscillator, a second ring oscillator that is turned on complementarily to the first ring oscillator, a combining circuit that combines a first output signal of the first ring oscillator and a second output signal of the second ring oscillator to generate a final output signal, and a calibration circuit that corrects a discontinuous pulse included in the final output signal based on feedback of the final output signal.

An integrated circuit includes a bandgap reference circuit configured to generate, from a digital chip supply voltage, a reference voltage and a proportional-to-absolute temperature (PTAT) voltage. A voltage-to-frequency (VTF) readout circuit to receive the reference voltage and the PTAT voltage as inputs. The VTF readout circuit includes sets of switched capacitors that operate as a voltage divider. The capacitors of the sets of switched capacitors are selectively charged by the PTAT voltage and generate a feedback voltage. A voltage-controlled oscillator (VCO) is driven by a difference between the feedback voltage and the reference voltage and generates a VCO clock. A clock generator generates a feedback clock based on the VCO clock. First switches of the sets of switched capacitors are controlled by the feedback clock.

The technology is directed to a di / dt circuit for detecting and measuring the di / dt droops on silicon. The circuit may be calibrated to account for silicon process spread. When a di / dt droop has been detected by the circuit, the magnitude of the droop can be measured by the circuit, allowing the system to determine the best course of action. For instance, when the measured droop is within predetermined limits, the system can continue to operate. However, in the event the measured droop is outside of the limits, the system can take different measures to reduce the clock frequency and therefore reduce the step change in power to prevent SDCs.

An apparatus includes a logic gate, a first inverter, a second inverter, a first resistor connected between the output of the logic gate and the input terminal of the first inverter, a first capacitor connected between the input terminal and the output terminal of the first inverter, a second resistor connected between the output terminal of the first inverter and the input terminal of the second inverter, a second capacitor connected between the input terminal of the second inverter and ground, and a third resistor connected between the output terminal of the second inverter and the logic gate, wherein the second input of the logic gate is configured to receive an enable signal, and wherein the first inverter is configured as a negative amplifier such that an effective capacitance provided by the first inverter and the first capacitor is greater than a physical capacitance of the first capacitor.

A device may include a substrate and an oscillation circuit integrated with the substrate. The oscillation circuit may include a field-emission-based vacuum transistor. The oscillation circuit may also include a capacitive transducer. An oscillation frequency of the oscillation circuit may be indicative of a magnitude of a temperature, a pressure, or a vibration at the capacitive transducer.