452results about "Pulse generation by logic circuits" patented technology

An injection-locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator and a controller. The plurality of delay elements is connected in a loop and coupled to a global power supply. Each delay element has an input driven by a preceding stage and an output that drives a next stage. Each voltage control circuit couples one of the plurality of delay elements to the global power supply. The phase comparator is coupled to in-phase and quadrature outputs of the injection-locked oscillator. The controller is coupled to an output of the phase comparator and is configured to drive control inputs of the two or more voltage control circuits. The control input of each voltage control circuit determines a level of a voltage drop across the each voltage control circuit.

A PUF circuit based on the threshold loss of MOSFETs comprises N stages of delay units and an arbiter. Each stage of delay unit comprises six inverters and four MOS transistors, wherein the four MOS transistors are all PMOS transistors or NMOS transistors. Each path in each stage of delay unit uses only one PMOS or NMOS transistor and does not use a transmission gate formed by a PMOS transistor and an NMOS transistor. Therefore, it reduces hardware cost. Each MOS transistor on the transmission path has a threshold loss, PMOS and NMOS transistors in a third inverter and a sixth inverter are in an on-state, and output terminals of the third inverter and the sixth inverter will be charged to a high level or discharged to a low level, thus greatly increasing a delay difference between two square signals and enhancing randomness.

The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking, relates to the technical field of integrated circuits, and is used for solving the technical problems that an existing injection locking oscillator limits the frequency tuning range and cannot effectively suppress noise. The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking. The low-phase noise ring voltage-controlled oscillator comprises a first ring oscillator unit and a second ring oscillator unit, the n first ring oscillator units are connected in series to form a chain structure; the second ring oscillator unit is provided with a cross coupling inverter complementary injection unit and a tail current source injection unit; a first output end of the chain structure is connected with a second input end of the second ring oscillator unit, and a second output end of the chain structure is connected with a first input end of the second ring oscillator unit; a first signal is injected into a cross-coupling inverter complementary injection unit and a tail current source injection unit, and a second ring oscillator unit receives a second signal output by a chain structure and then outputs a third signal.

An injection-locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator and a controller. The plurality of delay elements is connected in a loop and coupled to a global power supply. Each delay element has an input driven by a preceding stage and an output that drives a next stage. Each voltage control circuit couples one of the plurality of delay elements to the global power supply. The phase comparator is coupled to in-phase and quadrature outputs of the injection-locked oscillator. The controller is coupled to an output of the phase comparator and is configured to drive control inputs of the two or more voltage control circuits. The control input of each voltage control circuit determines a level of a voltage drop across the each voltage control circuit.

The invention discloses a ring oscillator which comprises a bias module and an oscillation module. The bias module comprises a current unit and a conversion unit which are connected, the current unit is used for generating a first current and a second current based on the reference current, and the conversion unit is used for generating a bias voltage based on the second current or generating the bias voltage based on a current difference between the first current and the second current; and a driving current is generated based on the current difference between the first current and the second current, the oscillation module is connected with the bias module to receive the bias voltage and the driving current, and an oscillation signal is generated based on the bias voltage and the driving current. The ring oscillator obtains a stable bias voltage as a working voltage of the oscillation module through two currents generated by the bias module based on a reference current, and obtains a driving current of the oscillation module based on a difference current of the two currents. The current has good temperature stability, so that the oscillation precision can be ensured.

The invention aims to provide a phase noise and maximum oscillation frequency adjustable ring oscillator and a control method. The oscillator comprises a main path and a third auxiliary path, the third auxiliary path is connected with the main path and is used for improving the oscillation frequency; by inserting the adjustable phase inverter, when the frequency of the ring oscillator does not meet the specification under the extreme corner condition, the oscillation frequency is improved by adjusting the phase inverter to sacrifice some phase noise.

The invention belongs to the technical field of electronic circuits, and particularly relates to an oscillator circuit for a PWM controller. Comprising an oscillator module which comprises a feedback loop and a current detection circuit; the hiccup module is used for gating and outputting an input signal by a data selector according to the level of the input PWM logic control signal so as to control the on-off of a transmission gate, establishing a charging and discharging process and providing a delay starting function for the oscillator module; and the jittering frequency module outputs current sources Iref0 of different sizes by performing combined gating on a current source I'ref and current sources I1-I4, outputs four paths of current sources Iref1-Iref4 of different sizes through a current mirror array mirror image, and provides charging and discharging current for the oscillator module and the hiccup module. By dynamically adjusting the PWM frequency, the switching frequency is matched with the load requirement, the invalid switching frequency is reduced, and the power consumption is greatly reduced.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

A method of a signal transmission device includes: providing at least one delay line circuit having a plurality of first delay units connected in series; providing a control voltage as a supply voltage provided for a first delay unit of the at least one delay line circuit; and adjusting the control voltage to maintain a delay amount of the first delay unit at a specific delay amount when a variation of the delay amount of the first delay unit occurs.

The invention relates to a passive wireless temperature sensor circuit, which comprises a transceiving antenna, an RF-DC rectifier circuit, a temperature sensing circuit and a backscatter circuit, the RF-DC rectifier circuit receives external radio frequency energy based on the transmit-receive antenna and then outputs direct current for power supply. The temperature sensing circuit comprises a complementary absolute temperature voltage generator and a ring oscillator; the complementary absolute temperature voltage generator comprises an MOS tube and generates CTAT voltage based on temperature characteristics of the MOS tube. The ring oscillator converts the CTAT voltage into an oscillation frequency signal of the ring oscillator and then outputs a square wave frequency signal with a negative temperature coefficient; the backscattering circuit backscatters the square wave frequency signal through the transceiving antenna; the CTAT key generation circuit built by the MOS tube generates CTAT voltage, a temperature frequency conversion chain is built through the CTAT voltage and the ring oscillator, temperature information is converted into frequency information of the oscillator, the power consumption of the temperature sensing circuit can be effectively reduced, and meanwhile the voltage coefficient of the CTAT voltage is increased by combining the temperature characteristic of the MOS tube.

The present application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit includes: a first transistor and a second transistor, the potential of the substrate end of the first transistor changes with the change of a first parameter, the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process of the potential generating circuit, and the potential of the substrate end of the second transistor changes with the change of the first parameter. Among them, the gate end of the first transistor is connected to the drain end of the first transistor, the substrate end of the first transistor serves as the first output end of the potential generating circuit, the gate end of the second transistor is connected to the drain end of the second transistor, and the substrate end of the second transistor serves as the second output end of the potential generating circuit. Thus, the first output end and the second output end can respectively output a potential that changes with any one of the power supply voltage, the operating temperature and the manufacturing process.

A device including delay cells connected in series and in a feedback loop to provide a ring oscillator. At least one of the delay cells in the ring oscillator is a stacked gate delay cell that includes two or more PMOS transistors having first drain / source paths connected in series to each other and having first gates connected to each other and two or more NMOS transistors having second drain / source paths connected in series to each other and to the first drain / source paths and having second gates connected to each other and to the first gates.

Aspects of the disclosure are directed to voltage sensing for safety-critical applications. In accordance with one aspect, the disclosure includes a multi-phase ring oscillator (RO) configured to operate in a first voltage domain; a frequency counter coupled to the multi-phase RO, the frequency counter configured to accumulate a plurality of phase cycles from the multi-phase RO over a time duration to generate a digital count word; an alarm processor coupled to the frequency counter, the alarm processor configured to receive an alarm state signal from the frequency counter; and a heartbeat detector coupled to the multi-phase RO, the heartbeat detector configured to operate in a second voltage domain and configured to detect a periodic recurrence of a heartbeat pulse to determine an integrity of the sensor function as a whole and alarm state signal in particular.

A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.

The present disclosure provides a voltage-controlled oscillator for a phase-lock loop circuit. The voltage-controlled oscillator is used to receive a control voltage and generate a clock signal, and includes a voltage-to-current device, a process compensation device, a subtraction unit and a clock signal generating module. The voltage-to-current device is used to generate a linear current according to the control voltage. The process compensation device is used to generate a compensation current according to the control voltage. The compensation current is proportional to a transistor operation speed corresponding to a process offset. The subtraction unit is electrically connected to the voltage-to-current device and the process compensation device, and is used to subtract the compensation current from the linear current to generate the control current. The clock signal generating module is electrically connected to the subtraction unit, and is used to generate the clock signal according to the control current.

Multi-phase oscillator circuits are disclosed. According to one aspect, a multi-phase oscillator circuit for a millimeter wave (mmW), transceiver is provided. The multi-phase oscillator circuit includes a plurality of inductor-coupled ring oscillators, each inductor-coupled ring oscillator comprising a plurality of single stage active delay cells, an output of each of the plurality of inductor-coupled ring oscillators being inductively coupled to an output of another one of the plurality of inductor-coupled ring oscillators.

A circuit that is capable of generating a negative voltage on a negative voltage supply node. The circuit includes a negative voltage generation circuit, an oscillator and an oscillator control signal generator. The negative voltage generation circuit generates a negative voltage on the negative voltage supply node in response to receiving a signal from the oscillator. The negative voltage generated by the negative voltage generation circuit depends upon the frequency of the signal from the oscillator. The oscillator control signal generator controls the frequency of the signal from the oscillator by sensing the negative voltage present on the negative voltage supply node, and by increasing or decreasing the frequency of the signal from the oscillator accordingly. Thus, charge is replenished to the negative voltage supply node to more closely match the drawing of charge from that negative voltage supply node, thereby more accurately generating the negative voltage.

The invention discloses a universal multiphase clock generation circuit and a combinational logic circuit thereof. The combinational logic circuit comprises a first-stage NAND gate and a second-stage NAND gate which are cascaded, the generation circuit is constructed by taking the combinational logic circuit as a basic unit; the generation circuit is a closed loop formed by connecting 2N basic units end to end; the first-stage NAND gates of the odd-numbered basic units form latches pairwise, and the first-stage NAND gates of the even-numbered basic units also form latches pairwise; each basic unit takes the output of the adjacent previous basic unit as the input and outputs a basic clock signal with a preset duty ratio based on a preset selection signal; performing odd number of times of phase inversion on the 2N basic clock signals output by the 2N basic units to obtain 2N-phase non-overlapping clock signals; and when N is an odd number, performing NAND operation on the N groups of adjacent two basic clock signals to obtain N-phase non-overlapping clock signals.

Provided is a reconfigurable Ring Oscillator (RO) Physical Unclonable Function (PUF), which comprises a NAND gate with a first input line and a second input line and a series of inverters with at least one memory cell placed between two inverters of the series of inverters, where an output of a last inverter provides input to the second input line, and where the memory cell comprises a Field Effect Transistor (FET). In addition, the reconfigurable RO PUF comprises a frequency counter, where the output of the last inverter provides input to the frequency counter. In normal operation mode, the first input line is on to enable ring oscillation and the FET is off. In reconfiguration mode, the first input line is off and the FET is on to enable reconfiguration.

A level shifter includes a first buffer circuit, a first capacitor, a second capacitor, a cross-coupled inverter, and a second buffer circuit. The first buffer circuit is configured to drive a first input signal and a second input signal with a first high power supply voltage and a first low power supply voltage to generate a first main driving signal and a second main driving signal. The first capacitor, the second capacitor, and the cross-coupled inverter are configured to generate signals of a first node and a second node based on the first and second main driving signals. The second buffer circuit is configured to drive the signals of the first and second nodes with a second high power supply voltage and a second low power supply voltage to generate a first output signal and a second output signal.

A temperature compensated oscillator includes: a current source configured to generate a proportional to absolute temperature (PTAT) current; and a ring oscillator which has a complementary to absolute temperature (CTAT) oscillation frequency and is configured to receive the PTAT current to generate an oscillation signal. The current source includes a tracking MOS device and a resistor which are coupled in series. The tracking MOS device and at least one MOS device of the ring oscillator have the same conductive type, and a gate-source voltage of the tracking MOS device and a gate-source voltage of the at least one MOS device have the same CTAT coefficient, such that when the temperature compensated oscillator operates, the tracking MOS device and the at least one of the first MOS device have a tracking effect to compensate the CTAT oscillation frequency.

The invention discloses a burr-free numerical control ring oscillator. The burr-free numerical control oscillator is realized based on a controllable delay chain and comprises a delay module, a control module and a decoding module. The delay module forms an oscillation loop, the control module processes control words and then outputs the control words to the decoding module, and the decoding module outputs the decoded control words to the delay module. According to the invention, the introduction of clock burrs during control word switching of the ring oscillator can be avoided, the output frequency of the ring oscillator is adjustable, the frequency range is wide, the circuit structure is simple, the design has universality, the portability is high, the overhead is low, and the ring oscillator is suitable for the field of highly integrated systems on chips and integrated circuits with higher requirements on portability.

A layered pulse generator for a vertical-cavity surface-emitting laser (“VCSEL”) driver is disclosed consisting of three elements: a low-speed pulse generator, a high-speed pulse generator, and a pulse generator selector, all of which are on-chip with the VCSEL driver. By providing these elements on-chip, overall system power and complexity are reduced while allowing for significantly higher pulse train frequencies compared with known systems. The high-speed pulse generator is capable of generating pulses faster and with higher resolution than that of the low-speed pulse generator. The high-speed pulse generator uses multiple clock outputs, phase shifted, and synthesized into a single pulse waveform capable of wide-ranging frequencies, duty cycles and pulse counts.

An automatic gain adjustor for a hybrid oscillator can be employed to overcome the frequency limitations of hybrid phase lock loops (PLLs). For example, an automatic gain adjustor for a hybrid oscillator can include a hybrid oscillator that is configured to receive a coarse tuning signal and a gain adjustment signal and generate an output signal with any frequency within the specified frequency range of the hybrid PLL. The automatic gain adjustor for a hybrid PLL may further include a fine tuning array that receives one or more fine tuning selection signals and generates a gain adjustment signal that is received by the hybrid oscillator. The fine tuning array generates a gain adjustment signal to adjust the gain of the hybrid oscillator according to an operating frequency range of the hybrid oscillator.

The signal generator includes the following: an oscillation generation circuit, configured to generate an initial oscillation signal based on an oscillation control signal; a duty cycle correction circuit, connected to an output end of the oscillation generation circuit and configured to adjust a duty cycle of the initial oscillation signal based on a duty cycle control signal, to generate an adjusted oscillation signal; an output interface, connected to an output end of the duty cycle correction circuit and configured to output the adjusted oscillation signal to an external test system; and an amplitude adjustment circuit, connected to the output end of the duty cycle correction circuit and configured to adjust an amplitude of the adjusted oscillation signal based on an amplitude control signal, to generate a test signal.

The object of the present invention is to provide a phase noise and maximum oscillation frequency adjustable ring oscillator and a control method. The oscillator includes: a main path and a third auxiliary path; the third auxiliary path is connected to the main path for increasing the oscillation frequency; by inserting an adjustable inverter, when the frequency of the ring oscillator does not meet the requirements under extreme corner conditions, the oscillation frequency can be increased by sacrificing some phase noise by adjusting the inverter.

The invention provides a scanning window signal generating circuit, which comprises an oscillator for generating an oscillation signal; the scanning logic module is used for generating a plurality of scanning window signals based on the oscillation signals and feeding back the scanning window signals to the oscillator, so that the length of one oscillation period of the oscillation signal generated by the oscillator in the scanning window of each scanning window signal is a corresponding preset time length; the length of the scanning window of each scanning window signal is equal to the corresponding preset duration, and the scanning window of each scanning window signal corresponds to one oscillation period of the oscillation signal. Therefore, the lengths of the scanning windows of various scanning window signals can be flexibly set, and the circuit design complexity is reduced.

The application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit comprises a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit, wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generating circuit, and a gate end of the second transistor is connected to a drain end of the second transistor. Thus, the substrate end of the first transistor can output a potential which changes with any one of the supply voltage, the operating temperature and the manufacturing process.

The disclosure concerns an oscillator circuit (10) for a signal transmitter, the oscillator circuit (10) comprising: - a resonant circuit (12) comprising a resonant inductor (LR) and a resonant capacitor (CR) parallel to the resonant inductor (LR) or comprising a crystal device, - a driving branch (14) comprising a pump capacitor (CP) connected to the resonant circuit (12), - a feedback branch (20) connected to the resonant circuit (12), - a phase shifting circuit (22) connected to the resonant circuit (12) via the feedback branch (20), - a comparator circuit (24) connected to the feedback branch (20) via the phase shifting circuit (22) and - a driver circuit (28) connected to an output of the comparator circuit (24) and operable to charge the pump capacitor (CP).

An oscillator circuit (200) includes a ring oscillator (202) and a ramp generator (204). The ring oscillator (202) includes a first inverter (214) and a second inverter (218). The first inverter (214) has a first inverter input, a first inverter output, and a first power terminal. The second inverter (218) has a second inverter input, a second inverter output, and a second power terminal. The second inverter input is coupled to the first inverter output, and the second inverter output is coupled to the first inverter input. The ramp generator circuit (204) has a ramp output coupled to the first power terminal and the second power terminal.