176 results about "Ring oscillator" patented technology

The invention discloses a multi-entropy source dynamic fusion true random number hardware generation system, which comprises a multi-entropy source acquisition module used for acquiring original entropy signals generated by at least two heterogeneous physical entropy sources in parallel, the heterogeneous physical entropy sources comprising an entropy source based on semiconductor junction thermal noise and an entropy source based on ring oscillator phase jitter; the entropy preprocessing module is used for carrying out adaptive gain adjustment and frequency band filtering on each original entropy signal and converting the original entropy signals into digital bit streams; the entropy source quality evaluation module is used for receiving each digital bit stream in real time and calculating a real-time quality evaluation score of each entropy source based on statistical characteristics of the digital bit streams, i is an entropy source identifier, and t is a time sequence; according to the method, the high randomness, high safety and high reliability of true random number generation can be fundamentally improved.

A random number generator comprises a ring generator and one or more inverter-based ring oscillators. The one or more inverter-based ring oscillators is configured to inject bits into the ring generator at a plurality of location. If there is more than one inverter-based ring oscillators, the inverter-based ring oscillators may have different numbers of inverting elements and may inject bits into the ring generator at different locations. At least one of the one or more inverterbased ring oscillators may be configured to inject bits into the ring generator at different locations from outputs of some or all its inverting elements. The random number generator may further comprise blocking circuitry configured to convert, based on a blocking signal, the ring generator into a circular shift register by blocking both the injection from the plurality of inverter-based ring oscillators and internal feedbacks in the ring generator.

The invention discloses an all-digital PVT sensor based on a ring oscillator, and relates to the field of PVT sensors, the all-digital PVT sensor comprises a process sensing circuit, a voltage sensing circuit and a temperature sensing circuit, the process sensing circuit comprises a process detection ring oscillator, the voltage sensing circuit comprises a voltage detection ring oscillator, and the temperature sensing circuit comprises a temperature detection ring oscillator. The temperature sensing circuit comprises a temperature sensitive ring oscillator; under the control of an enable signal, the process detection ring oscillator, the voltage detection ring oscillator and the temperature-sensitive ring oscillator start oscillation, and the process corner, the temperature and the power supply voltage of the detected chip are determined based on the oscillation frequencies of the process detection ring oscillator, the voltage detection ring oscillator and the temperature-sensitive ring oscillator. The PVT sensor is completely realized based on a digital circuit, an additional analog module does not need to be introduced, the area overhead is greatly reduced, and the PVT sensor has remarkable area advantage and structural simplicity while the high-precision detection capability is maintained.

A phase-locked loop. The phase-locked loop including a time-to-digital converter for acquiring a phase of a reference signal. A feedback signal formed from an output signal of the phase-locked loop is fed to the time-to-digital converter. The phase-locked loop including a digital-to-time converter which is configured to apply dithering to the feedback signal or to the reference signal. The digital-to-time converter is part of a ring oscillator with a predefined oscillation frequency. The phase-locked loop includes an evaluation unit for acquiring an actual frequency of the ring oscillator.

This provides a clock generation circuit that reduces the frequency of the clock signal when the power supply voltage increases. [Solution] The clock generation circuit 100 of the present invention includes a reference current setting unit 20, a bias voltage generation unit 110, and a ring oscillator 40. The bias voltage generation unit 110 generates a PBIAS voltage to be applied to each gate of the PMOS transistor MP3 of the ring oscillator 40, and an NBIAS voltage to be applied to each gate of the NMOS transistor MN3. In response to the power supply voltage Vcc reaching the target voltage, the bias voltage generation unit 110 increases the PBIAS voltage, thereby reducing the current supplied by the PMOS transistor MP3 and lowering the frequency of the clock signal OSC.

The application relates to a high-precision addressable ring oscillator test chip, method, device and medium, which comprises an addressing module, an output module and a plurality of ring oscillator test modules; the ring oscillator test module comprises a signal transmission module, a multifunctional test module and a plurality of ring oscillator test structures; the addressing module is used for selecting a ring oscillator test structure from the ring oscillator test structures of the plurality of ring oscillator test modules to perform a communication test; the multifunctional test module can switch the voltage compensation mode or the small-current test mode of the ring oscillator test structure based on a received control signal; when the characteristic parameters of the ring oscillator are measured, the voltage compensation mode can utilize voltage drop compensation to reduce the influence of the resistance voltage drop introduced in the test path, effectively improving the measurement precision, and the small-current test mode can effectively measure the static power supply current of the ring oscillator.

The invention discloses a low-phase noise ring oscillator of a distributed network, which belongs to the technical field of integrated circuits, and comprises a first ring oscillator core, a second ring oscillator core and a third ring oscillator core which have the same structure, the first ring oscillator core, the second ring oscillator core and the third ring oscillator core are closed-loop structures formed by a plurality of phase inverters and a plurality of coupling units; a distributed coupling network is formed among the first ring oscillator core, the second ring oscillator core and the third ring oscillator core; the first input end of each coupling unit in the first ring oscillator core is connected with the second input end of the corresponding coupling unit in the third ring oscillator core, and the second input end of each coupling unit in the first ring oscillator core is connected with the first input end of the corresponding coupling unit in the second ring oscillator core; and the second input end of the coupling unit in the second ring oscillator core is connected with the first input end of the corresponding coupling unit in the third ring oscillator core. On the premise that power consumption and the chip area are not remarkably increased, the phase noise performance is remarkably improved.

A circuit includes a voltage conversion unit from a power management unit library. The voltage conversion unit comprises a high-voltage domain subunit and a low-voltage domain subunit, wherein multiple high-voltage conversion modules in the high-voltage domain subunit and multiple low-voltage conversion modules in the low-voltage domain subunit are alternately connected to form a ring oscillator. The circuit includes a first control signal generation unit, a first selection output unit, a second control signal generation unit, and a second selection output unit. This invention enables efficient testing of the voltage conversion unit.

A control circuit for a ring oscillator, and a ring oscillation apparatus, relating to the field of oscillator signals. A power supply provides a power supply voltage for the ring oscillator by means of a reference voltage generation module and an operational amplifier, and a feedback control module regulates the voltage of a non-inverting input end of the operational amplifier on the basis of a real-time situation of the frequency of an output signal of the ring oscillator, thereby affecting the power supply voltage outputted by means of the operational amplifier to the ring oscillator. The frequency of the output signal of the ring oscillator is adjusted by regulating the power supply voltage to form feedback control on the output signal of the ring oscillator, and the frequency of the output signal of the ring oscillator is kept within a stable small range by means of feedback of dynamic adjustment, thereby improving the stability and reliability of the frequency of the output signal of the ring oscillator, reducing frequency distribution of the output signal of the ring oscillator, avoiding the impact of factors such as device parameters on the frequency of the output signal of the ring oscillator, and thus improving frequency accuracy.

True random number generators including ring oscillator circuits leveraging frequency and phase collapse events are described. An example ring oscillator circuit (ROC) includes a first oscillating loop comprising a first set of inverters, where the first oscillating loop is to oscillate at a first frequency and phase. The ROC further includes a second oscillating loop comprising a second set of inverters, which differs from the first set of inverters either in terms of a type of inverters or a number of inverters. The second oscillating loop is to oscillate at a second frequency and phase, different from the first frequency and phase. The ROC further includes a third oscillating loop to, as a result of mode switching from a first mode of operation into a second mode of operation, oscillate at a third frequency and phase, different from the first frequency and phase and the second frequency and phase.

The application discloses a ring oscillator and a phase-locked loop. The ring oscillator comprises: the output terminals of nth and mth delay units are connected to the main input terminals of (n+1)th and 1st delay units respectively; m is an odd number, the electrode polarity of the output terminal of the nth delay unit is opposite to the electrode polarity of the main input terminal of the (n+1)th delay unit, or the electrode polarity of the output terminal of the mth delay unit is opposite to the electrode polarity of the main input terminal of the 1st delay unit, m is an even number, the electrode polarity of the output terminal of the nth delay unit is the same as the electrode polarity of the main input terminal of the (n+1)th delay unit, or the electrode polarity of the output terminal of the mth delay unit is the same as the electrode polarity of the main input terminal of the 1st delay unit, n comprises an integer greater than or equal to 1 and less than m; the auxiliary input terminals of the (n+1)th and 1st delay units are connected to the main input terminals of the nth and mth delay units respectively. The technical scheme of the application can realize a ring oscillator with a high oscillation frequency.

This invention discloses a high-speed, high-precision voltage descent monitoring circuit, solving the problem of accurate and timely monitoring of voltage descent phenomena in large-scale integrated circuits, belonging to the fields of digital integrated circuit design and power management. This invention provides an optimized design method for ring oscillator point circuits, using standard cell type, threshold, drive capability, and power consumption as variables to find the ring oscillator circuit design with the highest voltage sensitivity, improving the resolution of the voltage descent monitoring circuit; it provides a one-fold, compact ring oscillator layout design to ensure load balance between nodes; it provides a Nyquist counter design to count the number of times nodes flip over a period of time, improving the voltage monitoring range and solving the metastable sampling problem of traditional counters; and it provides a high-speed voltage quantization circuit that processes coarse and fine quantization in parallel, improving the maximum sampling rate and quantization rate of the voltage descent monitoring circuit.

The invention discloses a voltage-controlled oscillator circuit, comprising: a current control circuit module configured to receive an input voltage and generate a control current responsive to the input voltage; the ring oscillator circuit module is connected with the current control circuit module and comprises a multi-stage inverter and a current adjusting unit which are connected in series to form a ring; the current adjusting unit is respectively connected to the current control circuit module and each stage of the multi-stage phase inverter, and is configured to synchronously and symmetrically adjust the pull-up current and the pull-down current of each stage of phase inverter in the multi-stage phase inverter in response to the control current; and the output driving circuit module is connected with an output node of the ring oscillator circuit module so as to shape and drive the oscillation signal generated by the ring oscillator circuit module and output a clock signal with a duty ratio of 50%. The circuit structure is simplified, the chip area is saved, the oscillator is allowed to directly work at the target frequency instead of double frequency, and the overall power consumption is reduced.

An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A1-A4) connected in a ring and has a first and a second supply terminal (s1, s2). Each amplifier circuit (A1-A4) comprises an input transistor (M1) whose gate is connected to an input (in) of the amplifier circuit, whose drain is connected to an internal node (x) of the amplifier circuit, and whose source is connected to the first supply terminal (s1). Furthermore, each amplifier circuit (A1-A4) comprises a first resonance circuit (R1) comprising a first inductor (L S ) and a first capacitor (C S ), wherein the first inductor (L S ) is connected between the internal node (x) and an output (out) of the amplifier circuit, and the first capacitor (C S ) is connected between the output (out) of the amplifier circuit and one of the first and second supply terminals (s1, s2). Furthermore, each amplifier circuit (A1-A4) comprises a second resonance circuit (R2) comprising a second inductor (L P ) and a second capacitor (C P ), wherein the second inductor (L P ) and the second capacitor (C P ) are connected in parallel between the internal node (x) and the second supply terminal (s2).

This application provides a security monitoring method and a microprocessor architecture. The method is applied to a microprocessor architecture including a processor core and a security monitoring module. The security monitoring module includes a ring oscillator with adjustable inverter stages. The method includes: when the security monitoring module detects a change in the process corner of the ring oscillator, it adjusts the inverter stages of the ring oscillator according to the current process corner of the ring oscillator and the operating frequency of the monitored module, so that the operating frequency of the ring oscillator is consistent with the operating frequency of the monitored module. The monitored module includes any module in the microprocessor architecture, and the ring oscillator serves as a reference frequency source for security monitoring of the monitored module. The above method can provide a stable reference frequency within the microprocessor architecture, thereby improving the accuracy and effectiveness of security monitoring of the monitored module.

The invention discloses a voltage-controlled oscillator, which belongs to the technical field of electronic circuits and comprises a source follower circuit, a pull-down circuit, a pull-up circuit and a plurality of delay circuits. The source follower circuit generates a regulating voltage according to a control voltage and an enable signal. When the regulating voltage conducts a first path in the pull-down circuit, the pull-down circuit pulls down the level of a first node to the ground so as to generate a pull-down signal through the first node. When the regulating voltage conducts a second path in the pull-up circuit, the pull-up circuit transmits the regulating voltage to a second node so as to generate a pull-up signal through the second node. The plurality of delay circuits are configured as a ring oscillator and are started according to the pull-down signal and the pull-up signal so as to generate an output oscillation signal according to the control voltage.

The application provides a ring oscillator circuit, comprising: a bias circuit and a delay circuit; the bias circuit is used for generating a first bias current and a second bias current, the first bias current is inversely proportional to a voltage drop resistance in the bias circuit and is proportional to a square root of a reference current; in the delay circuit, a first input end of a delay control circuit is used for obtaining the first bias current, and a second input end is used for obtaining the second bias current; a first capacitor is arranged in the delay control circuit, so that a rising delay time of an output end of the delay control circuit is proportional to the first capacitor, inversely proportional to the first bias current and proportional to a flip threshold of a delay inverter in the delay control circuit, wherein the flip threshold of the delay inverter is proportional to the square root of the reference current, so that an oscillation period of the ring oscillator circuit is mainly determined by the proportion of the resistance, the capacitance and the square root of the reference current in the circuit, and the relationship between the oscillation period and the size of the reference current is weakened.

Oscillator device (10) comprising: - a ring oscillator circuit (20) with at least one delay stage (50), wherein an output of a last delay stage is fed back to an input of a first delay stage, wherein each of the delay stages (50) is configured to receive a charging current and provide a delay which depends on the charging current, and wherein at least one of the delay stages (50) comprises a metal-oxide-semiconductor field-effect transistor; - a bias circuit (30) comprising an output terminal coupled to an input terminal of the ring oscillator circuit (20), wherein the bias circuit (30) is configured to receive a temperature-independent reference voltage (Vref) and comprises a current source with a primary n-channel metal-oxide-semiconductor NMOS transistor (M0), wherein the current source is configured toto supply a control current (Iptat) to the ring oscillator circuit (20) which is proportional to a difference between the temperature-independent reference voltage (Vref) and a gate-source voltage (Vgs) of the primary NMOS transistor (M0), wherein the gate-source voltage (Vgs) of the primary NMOS transistor (M0) includes a negative temperature coefficient, wherein the bias circuit (30) further comprises: - a differential amplifier (A) configured to compare the temperature-independent reference voltage (Vref) with a measurement voltage, - a feedback transistor (M3) with a gate-drain path of the feedback transistor (M3) arranged in a negative feedback loop of the differential amplifier (A), - a resistor network (R),wherein a drain of the feedback transistor (M3) is coupled to a first terminal (1) of the resistor network (R) and a drain of the primary NMOS transistor (M0) is coupled to a second terminal (2) of the resistor network (R) and the measurement voltage is tapped at the first terminal (1) of the resistor network (R), and a capacitor coupled to an output of the differential amplifier (A) and the first terminal (1).

The invention relates to the technical field of electronic equipment, and discloses a charging interface contact state monitoring system, which comprises an oscillating circuit configured to generate a frequency signal with an output frequency associated with a parasitic electrical parameter of at least one pin of a charging interface; the frequency measurement module is configured to measure the real-time output frequency of the oscillation circuit; and the processing module is configured to compare the real-time output frequency with a reference frequency and judge the contact state of the charging interface according to a comparison result. A parasitic electrical parameter which is inherent in an interface and does not need extra cost is used as a sensor, and the sensor is coupled with a very simple oscillating circuit (such as an annular oscillator which can be completely integrated in a chip), so that microscopic change of a physical contact state is ingeniously converted into frequency signal change which can be accurately measured. And the cost of an additional special sensor is obviously reduced or does not need to be increased.

The invention discloses a self-calibration type capacitor frequency conversion method, which comprises the following steps of: connecting a capacitor to be measured into a charging loop through a switch matrix, charging the capacitor to be measured, transferring charges of the capacitor to be measured to an integrating capacitor, and generating an integrating voltage; inputting the integral voltage into a five-stage ring oscillator so as to convert the integral voltage into a square wave signal, and performing pulse width amplification on the square wave signal through a time amplifier; a calibration engine is introduced, the calibration engine starts calibration by detecting calibration parameters, the current pulse width is obtained by sequentially switching the reference capacitor array to the measurement channel, and the current pulse width is compared with the stored factory calibration value of the reference capacitor; if the comparison deviation exceeds a threshold value, calculating a scale factor, superposing a second-order temperature compensation model on the scale factor, and finally outputting a calibrated capacitance value to be measured; according to the invention, the time-to-digital converter replaces the traditional ADC, and the intelligent switching reference capacitor array and the dynamic temperature compensation algorithm are combined, so that the full-working-condition self-calibration is realized.

Embodiments of the present disclosure relate to circuitry for regulating a hold voltage of a static random access memory. A static random access memory (SRAM) device disclosed herein includes an array of SRAM cells powered between a first voltage and a second voltage. A reference voltage generator generates a reference voltage proportional to absolute temperature, an amplitude curve of the reference voltage is based on a control word. A low dropout amplifier sets and maintains the second voltage equal to the reference voltage. A control circuitry generates the control word based on process variation information about the SRAM device. In one example, the control circuitry monitors an alarm bit cell and increments the control word, thereby increasing the amplitude curve of the reference voltage, until the alarm bit cell fails. In another example, the control circuitry measures an oscillation frequency of a ring oscillator, and selects the control word based on the measured oscillation frequency.

The invention provides a flexible wireless passive multi-mode sensing integrated acquisition method and system, and the method comprises the steps: carrying out the integrated preparation and manufacturing of a flexible antenna, a flexible chip and a multi-mode sensor, enabling a ring oscillator to start oscillation to generate a periodic waveform, and enabling a clock to generate a slow periodic signal after the frequency division of a counter; when the capacitor voltage of the multi-mode sensor reaches a set threshold value, counting is stopped, and a counting value is sent to a channel encoder for channel encoding through a single-slope ADC; the coded logic signal enters a modulation module after the current is amplified by a buffer, the modulated signal is reflected back to a reader, the signal is received, demodulated and extracted and then decoded, and a count value of the charging time and a clock signal are obtained; and acquiring a sensing physical quantity signal according to the count value of the charging time, and acquiring temperature information according to the clock signal. According to the technical scheme, the technical problems that in the prior art, a multimode integrated sensor is usually large in size, an external power source is needed for power supply, and the integration and intelligence degree is low are solved.

Electronic Device for Random Number Generation This description relates to an electronic device (1) comprising: a first ring oscillator (RO1) and a second ring oscillator (RO2); a synchronous flip-flop (FF); a counter (COUNTER); a first circuit (Nm CTRL) configured to modify a period of at least one of the two oscillators (RO1, RO2) so that an average difference between the periods of the two oscillators is equal to a target difference; and a second circuit (PROCESS) configured to: initialize a value of an integer K, calculate sums (VAL) of K successive values ​​of the counter (COUNTER), calculate an Allan variance (VAR) on the calculated sums (VAL), and set K to its current value if the calculated variance is greater than a first threshold and increment K otherwise. Figure for the abstract: Fig. 1

The invention discloses an orthogonal enhanced ring oscillator based on in-phase injection coupling, which belongs to the technical field of radio frequency integrated circuits and comprises a ring oscillator circuit and an orthogonal coupler circuit. The ring oscillator circuit is used for generating oscillation signals and comprises two cascaded differential ring oscillator basic units, and each stage of differential ring oscillator basic unit comprises an input pair transistor and a negative resistance pair transistor; the quadrature coupler circuit comprises a coupling transistor and four differential output nodes which are respectively connected with the first-stage differential ring oscillator basic unit and the second-stage differential ring oscillator basic unit to form an in-phase injection coupling structure. By introducing an in-phase injection coupling structure into the orthogonal enhanced ring oscillator, collaborative optimization of high-precision phase locking and low phase noise is realized, and the phase difference of multi-phase output signals is stably locked through pure switching operation on the premise of not consuming static power consumption.

This invention discloses a multi-oscillator true random number generator based on independent auxiliary TRNG control. It is characterized by comprising a main TRNG module and an auxiliary TRNG module. The main TRNG module provides a true random number sequence TR via an internal bus. The main TRNG module includes a random signal generation module, an asynchronous sampling circuit, and a post-processing circuit. The random signal generation module includes N ring oscillators RO_i, each RO_i having an independent enable terminal EN_i, i=0~N-1. The auxiliary TRNG module is a complete TRNG, outputting an M-bit auxiliary random number sequence F[M-1:0], where M>N≥2. The lower N bits of the auxiliary TRNG module's output F[N-1:0] are directly connected one-to-one to the enable terminal EN_i of the corresponding RO_i in the main TRNG module without any synchronization circuit, achieving EN_i=F[i], where F[i] corresponds to the i-th bit in F[N-1:0]. This invention can improve the entropy quality and attack resistance of the overall system.

A low temperature drift ring oscillator, a chip and a communication terminal are provided. [Solution] A low-temperature drift ring oscillator includes a temperature tracking compensation circuit, an inverter oscillation circuit, and a buffer shaping circuit. The temperature-dependent impedance of diode-connected PMOS and NMOS transistors is used to track and compensate for the temperature characteristics of the impedance of the PMOS and NMOS transistors of an inverter in the inverter oscillation circuit. At the same time, the proportional relationship of the temperature coefficients of each variable in the temperature tracking compensation circuit is adjusted based on a bias current with a specific temperature coefficient, thereby converting the impedance temperature characteristics of the diode-connected PMOS and NMOS transistors into a voltage with a compensated temperature characteristic, and using this voltage as the supply voltage for the inverter oscillation circuit. This ensures that the oscillation frequency of the clock signal output from the ring oscillator is hardly affected by temperature.

A programmable digitally-controlled oscillator (DCO) for time-domain symbol generation is described in an embodiment. The programmable DCO comprising: an odd number (n) of multi delay cells (MDGs) to form a ring oscillator, the odd number (n) being equal to or more than three, and the odd number (n) of MDCs being adapted to generate n-1 number of multiplexed phases for phase shift keying (PSK) modulation, wherein each of the n number of MDCs comprises: two or more multi jitter cells (MJCs), each of the two or more MJCs being adapted to activate a corresponding delay for tuning a period of one cycle to represent a corresponding bit of a frequency shift keying (FSK) modulation, wherein each of the two of more MJCs comprises: two or more replica basic delay cells (BDCs) configured to adjust jitter, wherein each of the two or more replica BDC is adapted to provide a predetermined jitter target and comprises: two or more sets of reconfigurable inverter gates having different channel lengths and corresponding frequency ranges, the two or more reconfigurable inverter gates being selectable based on a target frequency range. A backscattered software-defined radio (SDR) transmitter system is also described in an embodiment.

A ring oscillator has a first group of inverters that receive respective frequency control signals to control delays through the inverters. The frequency of the ring oscillator is dithered according to least significant bits of a frequency control word supplied by a loop filter of a phase-locked loop. Most significant bits of the frequency control word are used to generate the frequency control signals. An accumulator is clocked by an output of the ring oscillator and accumulates the least significant bits of the frequency control word. A selector circuit selects either N most significant bits of the frequency control word or the N most significant bits of the frequency control word +1 according to the selector signal to generate the frequency control signals.

The apparatus includes: a ring oscillator including a set of cascaded current-starved inverters arranged in a ring; a set of field effect transistors (FETs) coupled in series with the set of cascaded current-starved inverters between an upper voltage rail and a lower voltage rail, respectively; a negative to absolute temperature (NTAT) current source configured to generate a NTAT current; and one or more current mirrors coupling the NTAT current source to the set of FETs.

The embodiment of the invention relates to a ring oscillator. A ring oscillator generates an output signal having a frequency controlled by a first frequency control current applied to a frequency control terminal. A first transistor of a first conductivity type receives a control voltage on a control terminal and supplies a first frequency control current at a first conductive terminal. A second transistor of a second conductivity type opposite the first conductivity type also receives the control voltage on the control terminal and supplies a second current to a second conductive terminal of the first transistor.