419 results about "Ring oscillator" patented technology

The invention provides a clock signal generating circuit, a wired communication transceiver and electronic equipment, and the circuit outputs a first DC voltage comprising phase difference information and frequency difference information of a reference clock signal and a feedback clock signal through a phase frequency detection module. The pulse generator generates a narrow pulse signal based on the DC voltage and a reference clock signal, the oscillation frequency of each secondary ring oscillator in the cross-coupled ring oscillator is controlled by the first DC voltage, and the cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on each secondary ring oscillator. One output node in the cross coupling ring oscillator receives the narrow pulse signal, frequency and phase locking is completed in an injection locking mode, and the frequency divider is used for conducting frequency division processing on any high-frequency clock signal and outputting a feedback clock signal. Therefore, a high-frequency multi-phase clock signal with low phase noise and high phase precision can be generated by using the low-frequency reference clock signal.

The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking, relates to the technical field of integrated circuits, and is used for solving the technical problems that an existing injection locking oscillator limits the frequency tuning range and cannot effectively suppress noise. The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking. The low-phase noise ring voltage-controlled oscillator comprises a first ring oscillator unit and a second ring oscillator unit, the n first ring oscillator units are connected in series to form a chain structure; the second ring oscillator unit is provided with a cross coupling inverter complementary injection unit and a tail current source injection unit; a first output end of the chain structure is connected with a second input end of the second ring oscillator unit, and a second output end of the chain structure is connected with a first input end of the second ring oscillator unit; a first signal is injected into a cross-coupling inverter complementary injection unit and a tail current source injection unit, and a second ring oscillator unit receives a second signal output by a chain structure and then outputs a third signal.

The utility model discloses a digital auxiliary simulation LDO circuit without an off-chip capacitor. A simulation main loop of the circuit comprises an error amplifier, a buffer stage circuit, a simulation power stage circuit and a VG voltage detection circuit. The digital auxiliary loop includes a digital control logic circuit, a ring oscillator circuit, and a digital power stage circuit. By introducing the digital power adjusting tube, the parasitic capacitance of the grid electrode of the analog power tube is reduced, the pole of the grid electrode is located at high frequency, and on the basis, the super source follower is added to push the pole to higher frequency, so that the circuit has better loop stability. In a steady state, the digital auxiliary loop is forbidden, and the analog main loop can ensure strict adjustment, low quiescent current and no switching noise at the output end; when a load current suddenly changes, a ring oscillator in the digital auxiliary loop is called to generate a clock signal, and the number of conducted digital power tubes is changed, so that response time is not limited by a clock period, dependence on an external clock is avoided, meanwhile, voltage precision and rapid transient response are guaranteed, and static power consumption of the circuit is reduced.

The invention provides a multi-phase clock generator which outputs N injection current signals corresponding to different phases by processing an input clock signal, N is an integral multiple of 4, and a cross-coupled loop is arranged in a cross-coupled ring oscillator. The loop is respectively coupled with output nodes in N / 4 secondary ring oscillators based on a phase sequence, and the secondary ring oscillators realize high-working-frequency and high-stability oscillation frequency output and low-error phase alignment through a cross coupling mechanism, so that the secondary ring oscillators can output N oscillation clock signals with equally-spaced phases, and the phase alignment is realized. Since the injection current signal is input into each output node in the secondary ring oscillator based on the phase sequence, the frequency and the phase of the secondary ring oscillator are locked, the frequency is the same as the frequency of the input clock signal, and the phase noise is very low, so that the frequency and the phase of the secondary ring oscillator are locked. According to the invention, a high-speed multi-phase clock signal with low phase noise and high phase precision can be generated.

The invention discloses a multi-entropy source dynamic fusion true random number hardware generation system, which comprises a multi-entropy source acquisition module used for acquiring original entropy signals generated by at least two heterogeneous physical entropy sources in parallel, the heterogeneous physical entropy sources comprising an entropy source based on semiconductor junction thermal noise and an entropy source based on ring oscillator phase jitter; the entropy preprocessing module is used for carrying out adaptive gain adjustment and frequency band filtering on each original entropy signal and converting the original entropy signals into digital bit streams; the entropy source quality evaluation module is used for receiving each digital bit stream in real time and calculating a real-time quality evaluation score of each entropy source based on statistical characteristics of the digital bit streams, i is an entropy source identifier, and t is a time sequence; according to the method, the high randomness, high safety and high reliability of true random number generation can be fundamentally improved.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

The invention relates to a passive wireless temperature sensor circuit, which comprises a transceiving antenna, an RF-DC rectifier circuit, a temperature sensing circuit and a backscatter circuit, the RF-DC rectifier circuit receives external radio frequency energy based on the transmit-receive antenna and then outputs direct current for power supply. The temperature sensing circuit comprises a complementary absolute temperature voltage generator and a ring oscillator; the complementary absolute temperature voltage generator comprises an MOS tube and generates CTAT voltage based on temperature characteristics of the MOS tube. The ring oscillator converts the CTAT voltage into an oscillation frequency signal of the ring oscillator and then outputs a square wave frequency signal with a negative temperature coefficient; the backscattering circuit backscatters the square wave frequency signal through the transceiving antenna; the CTAT key generation circuit built by the MOS tube generates CTAT voltage, a temperature frequency conversion chain is built through the CTAT voltage and the ring oscillator, temperature information is converted into frequency information of the oscillator, the power consumption of the temperature sensing circuit can be effectively reduced, and meanwhile the voltage coefficient of the CTAT voltage is increased by combining the temperature characteristic of the MOS tube.

Aspects of the disclosure are directed to voltage sensing for safety-critical applications. In accordance with one aspect, the disclosure includes a multi-phase ring oscillator (RO) configured to operate in a first voltage domain; a frequency counter coupled to the multi-phase RO, the frequency counter configured to accumulate a plurality of phase cycles from the multi-phase RO over a time duration to generate a digital count word; an alarm processor coupled to the frequency counter, the alarm processor configured to receive an alarm state signal from the frequency counter; and a heartbeat detector coupled to the multi-phase RO, the heartbeat detector configured to operate in a second voltage domain and configured to detect a periodic recurrence of a heartbeat pulse to determine an integrity of the sensor function as a whole and alarm state signal in particular.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

A random number generator comprises a ring generator and one or more inverter-based ring oscillators. The one or more inverter-based ring oscillators is configured to inject bits into the ring generator at a plurality of location. If there is more than one inverter-based ring oscillators, the inverter-based ring oscillators may have different numbers of inverting elements and may inject bits into the ring generator at different locations. At least one of the one or more inverterbased ring oscillators may be configured to inject bits into the ring generator at different locations from outputs of some or all its inverting elements. The random number generator may further comprise blocking circuitry configured to convert, based on a blocking signal, the ring generator into a circular shift register by blocking both the injection from the plurality of inverter-based ring oscillators and internal feedbacks in the ring generator.

Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.

The invention relates to the field of electronic oscillation circuits, and discloses a low-noise ring oscillator. The ring oscillator comprises an oscillation loop formed by connecting 2N + 1 stages of delay unit modules end to end, each stage of delay unit module comprises a complementary MOS tube and a source electrode degeneration resistor, one end of the source electrode degeneration resistor is connected with a source electrode of the complementary MOS tube, the other end of the source electrode degeneration resistor is connected with a common potential, and the source electrode degeneration resistor is made of a low-noise polycrystalline silicon resistor. By introducing the source electrode degeneration resistor into the delay unit module and utilizing the characteristic that a resistor element has lower noise compared with an MOS (Metal Oxide Semiconductor) device, the proportion of an MOS tube in the integral noise contribution is effectively reduced, so that the phase noise performance of the ring oscillator is improved, and the ring oscillator is particularly suitable for an electronic circuit system needing a high-quality clock signal.

The invention relates to the technical field of state monitoring, in particular to an optical storage device state monitoring method and system based on an FPGA. The method comprises the following steps: acquiring FPGA structure data; deploying a ring oscillator unit in an FPGA idle logic resource area based on the FPGA structure data, and configuring a leakage current measurement channel on an FPGA programmable I / O pin to obtain leakage current measurement channel configuration data; acquiring RO oscillation frequency data and grid leakage current data according to the leakage current measurement channel configuration data; and performing mapping calculation on the RO oscillation frequency data and the grid leakage current data based on a preset temperature calibration curve and a voltage calibration curve. Through high-precision real-time monitoring and multiple regression modeling based on the FPGA, the diagnosis precision and intelligent early warning capability of the temperature and stress of the key area of the optical storage equipment are effectively improved, and the problem that a traditional monitoring system is insufficient in accuracy, real-time performance and pertinence is solved.

The invention provides an annular voltage-controlled oscillator for a micro-display. The annular voltage-controlled oscillator comprises a band-gap reference current source, an oscillator delay circuit, a temperature sensor and a voltage-controlled gain adjusting circuit, the temperature sensor is connected with the band-gap reference current source and is used for generating a control code SWA and controlling a current value generated by the band-gap reference current source; the band-gap reference current source is connected with the control end of the oscillator delay circuit and is used for copying a generated current value to the oscillator delay circuit; and the voltage-controlled gain adjusting circuit is connected with the output end of the oscillator delay circuit and is used for generating a control code SWB and controlling the oscillation frequency of the oscillator delay circuit. By adopting the temperature compensation and voltage-controlled gain adjustment circuit, the basic current and the load capacitance are adjusted according to the change of the temperature and the change of the control voltage, so that the output frequency of the ring oscillator does not change along with the temperature, and the constant voltage-controlled gain is realized under different control voltages.

The invention discloses an all-digital PVT sensor based on a ring oscillator, and relates to the field of PVT sensors, the all-digital PVT sensor comprises a process sensing circuit, a voltage sensing circuit and a temperature sensing circuit, the process sensing circuit comprises a process detection ring oscillator, the voltage sensing circuit comprises a voltage detection ring oscillator, and the temperature sensing circuit comprises a temperature detection ring oscillator. The temperature sensing circuit comprises a temperature sensitive ring oscillator; under the control of an enable signal, the process detection ring oscillator, the voltage detection ring oscillator and the temperature-sensitive ring oscillator start oscillation, and the process corner, the temperature and the power supply voltage of the detected chip are determined based on the oscillation frequencies of the process detection ring oscillator, the voltage detection ring oscillator and the temperature-sensitive ring oscillator. The PVT sensor is completely realized based on a digital circuit, an additional analog module does not need to be introduced, the area overhead is greatly reduced, and the PVT sensor has remarkable area advantage and structural simplicity while the high-precision detection capability is maintained.

The invention relates to the technical field of radio frequency integrated circuits, and particularly provides a low-jitter injection locking phase-locked loop based on multiphase injection, which comprises an injection locking path unit, a locking unit and an injection locking ring oscillator, the injection locking path unit can generate a multi-phase injection signal and a complementary injection signal according to the received reference signal; the injection locking ring oscillator receives the multi-phase injection signal and the complementary injection signal and then generates an oscillation signal; and then the locking unit locks the injection locking phase-locked loop according to the generated oscillation signal. According to the invention, the injection locking path unit generates the multi-phase injection signal and the complementary injection signal, so that the injection locking ring oscillator is subjected to multi-phase direct injection and cross coupling complementary injection, and the multi-phase direct injection can reduce the jitter of the phase-locked loop based on the ring oscillator. And phase deviation generated by multi-phase direct injection is eliminated through cross coupling complementary injection, so that the injection intensity is further improved, and the noise suppression bandwidth is effectively expanded.

A temperature compensated oscillator includes: a current source configured to generate a proportional to absolute temperature (PTAT) current; and a ring oscillator which has a complementary to absolute temperature (CTAT) oscillation frequency and is configured to receive the PTAT current to generate an oscillation signal. The current source includes a tracking MOS device and a resistor which are coupled in series. The tracking MOS device and at least one MOS device of the ring oscillator have the same conductive type, and a gate-source voltage of the tracking MOS device and a gate-source voltage of the at least one MOS device have the same CTAT coefficient, such that when the temperature compensated oscillator operates, the tracking MOS device and the at least one of the first MOS device have a tracking effect to compensate the CTAT oscillation frequency.

The invention relates to the field of true random number generation, and discloses a true random number generator based on a memristor and a generation method.The true random number generator comprises a biasing circuit, a current hunger type ring oscillator and a time-to-digital conversion circuit which are cascaded; the bias circuit comprises a memristor; the current hunger type ring oscillator comprises an inverter chain formed by cascading a plurality of current hunger type inverters. The invention solves the problems of poor randomness and high power consumption of true random numbers in the prior art, and has the characteristics of small occupied area, simple circuit structure and high generation rate.

The invention relates to a time sequence generation device. The present specification relates to an apparatus comprising a ring oscillator comprising a plurality of gates, each gate transmitting a fast clock signal. The first shift register includes successive first flip-flops, each of which is synchronized with a same first clock signal corresponding to one of the fast clock signals. The first shift register is looped back on itself and implements a second oscillator in which each first flip-flop transmits a slow clock signal. The second shift register includes successive second flip-flops, each of which is synchronized with a same second clock signal corresponding to one of the slow clock signals.

A phase-locked loop. The phase-locked loop including a time-to-digital converter for acquiring a phase of a reference signal. A feedback signal formed from an output signal of the phase-locked loop is fed to the time-to-digital converter. The phase-locked loop including a digital-to-time converter which is configured to apply dithering to the feedback signal or to the reference signal. The digital-to-time converter is part of a ring oscillator with a predefined oscillation frequency. The phase-locked loop includes an evaluation unit for acquiring an actual frequency of the ring oscillator.

The object of the present invention is to provide a phase noise and maximum oscillation frequency adjustable ring oscillator and a control method. The oscillator includes: a main path and a third auxiliary path; the third auxiliary path is connected to the main path for increasing the oscillation frequency; by inserting an adjustable inverter, when the frequency of the ring oscillator does not meet the requirements under extreme corner conditions, the oscillation frequency can be increased by sacrificing some phase noise by adjusting the inverter.

This provides a clock generation circuit that reduces the frequency of the clock signal when the power supply voltage increases. [Solution] The clock generation circuit 100 of the present invention includes a reference current setting unit 20, a bias voltage generation unit 110, and a ring oscillator 40. The bias voltage generation unit 110 generates a PBIAS voltage to be applied to each gate of the PMOS transistor MP3 of the ring oscillator 40, and an NBIAS voltage to be applied to each gate of the NMOS transistor MN3. In response to the power supply voltage Vcc reaching the target voltage, the bias voltage generation unit 110 increases the PBIAS voltage, thereby reducing the current supplied by the PMOS transistor MP3 and lowering the frequency of the clock signal OSC.

The application relates to a high-precision addressable ring oscillator test chip, method, device and medium, which comprises an addressing module, an output module and a plurality of ring oscillator test modules; the ring oscillator test module comprises a signal transmission module, a multifunctional test module and a plurality of ring oscillator test structures; the addressing module is used for selecting a ring oscillator test structure from the ring oscillator test structures of the plurality of ring oscillator test modules to perform a communication test; the multifunctional test module can switch the voltage compensation mode or the small-current test mode of the ring oscillator test structure based on a received control signal; when the characteristic parameters of the ring oscillator are measured, the voltage compensation mode can utilize voltage drop compensation to reduce the influence of the resistance voltage drop introduced in the test path, effectively improving the measurement precision, and the small-current test mode can effectively measure the static power supply current of the ring oscillator.

The utility model discloses a vehicle-mounted short-wave double-loop antenna lodging device, which comprises a case, a driving assembly, an antenna fixing platform and a rotating arm, the driving assembly is arranged in the case; the antenna fixing platform and the case are oppositely arranged, and the antenna fixing platform is provided with an antenna large-ring oscillator mounting interface, an antenna small-ring oscillator interface, an antenna supporting rod mounting interface, an antenna large-ring oscillator antenna adjustment connecting port and an antenna small-ring oscillator antenna adjustment connecting port; the antenna large-ring oscillator mounting interface is connected with the antenna large-ring oscillator antenna tuning connector; the antenna small ring oscillator interface is arranged at the center of the antenna support rod mounting interface and is connected with the antenna small ring oscillator antenna adjustment connector; and two ends of the rotating arm are respectively connected with the case and the side wall of the antenna fixing platform. According to the utility model, the installation height of the dual-ring antenna can be effectively reduced, so that the impact, vibration and wind resistance borne by the dual-ring antenna are reduced.

An oscillator circuit (200) includes a ring oscillator (202) and a ramp generator (204). The ring oscillator (202) includes a first inverter (214) and a second inverter (218). The first inverter (214) has a first inverter input, a first inverter output, and a first power terminal. The second inverter (218) has a second inverter input, a second inverter output, and a second power terminal. The second inverter input is coupled to the first inverter output, and the second inverter output is coupled to the first inverter input. The ramp generator circuit (204) has a ramp output coupled to the first power terminal and the second power terminal.

The invention discloses a low-phase noise ring oscillator of a distributed network, which belongs to the technical field of integrated circuits, and comprises a first ring oscillator core, a second ring oscillator core and a third ring oscillator core which have the same structure, the first ring oscillator core, the second ring oscillator core and the third ring oscillator core are closed-loop structures formed by a plurality of phase inverters and a plurality of coupling units; a distributed coupling network is formed among the first ring oscillator core, the second ring oscillator core and the third ring oscillator core; the first input end of each coupling unit in the first ring oscillator core is connected with the second input end of the corresponding coupling unit in the third ring oscillator core, and the second input end of each coupling unit in the first ring oscillator core is connected with the first input end of the corresponding coupling unit in the second ring oscillator core; and the second input end of the coupling unit in the second ring oscillator core is connected with the first input end of the corresponding coupling unit in the third ring oscillator core. On the premise that power consumption and the chip area are not remarkably increased, the phase noise performance is remarkably improved.

According to one embodiment, an oscillation circuit includes: a ring oscillator; a first transistor having a gate terminal coupled to an output port of the ring oscillator and a drain terminal coupled to a first node; a second transistor having a drain terminal and a gate terminal that are both coupled to the first node; a third transistor having a gate terminal coupled to the first node and a drain terminal coupled to a second node; a fourth transistor having a gate terminal coupled to the first node and a drain terminal coupled to a third node; a fifth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node; and a voltage buffer having an input port coupled to the second node.

A method for measuring a time-of-flight interval in a depth sensing system includes generating a coarse time count using a global clock signal shared across a plurality of pixels and external to the sensor array, wherein the coarse time count provides the most significant bits of the time-of-flight interval free of inter-pixel process variation; generating an intermediate time count within a pixel using a local ring oscillator based on completed oscillation cycles during a measurement interval; generating a fine time residual within the pixel based on at least one phase state of the ring oscillator, wherein the fine time residual provides the least significant bits; and deriving the time-of-flight interval from a combination of the coarse time count, the intermediate time count, and the fine time residual.

The present application relates to a kind of threshold adjustable RO PUF device and output sequence method, belong to information security technical field, solve the problem that the two key design indexes of existing RO PUF uniqueness and stability are difficult to compromise implementation.For threshold adjustment module, at least two ring oscillators and at least one counting comparison module;Wherein, every two ring oscillators is a group, and each group corresponds to a counting comparison module;Threshold adjustment module is used to set the threshold gear of the clock oscillation frequency difference generated by every two ring oscillators in each group;Wherein, threshold gear is adjustable;Counting comparison module is used to receive threshold gear and the clock oscillation frequency generated by two ring oscillators in corresponding group, obtains corresponding frequency difference threshold according to threshold gear, and the clock oscillation frequency difference generated by two ring oscillators is counted, obtains a bit output by comparing clock oscillation frequency difference with frequency difference threshold;The bit output corresponding to all groups is used as the output response data of RO PUF.

The present invention discloses a ring oscillator, chip, and electronic device that utilizes reverse clock compensation for reinforcement. The ring oscillator includes a compensation reinforcement circuit for reinforcing the output pin OUT1 of a delay node using reverse clock compensation. The compensation reinforcement circuit includes two PMOS transistors M1 and M2, and two NMOS transistors M3 and M4. The source of the PMOS transistor M1 is connected to voltage VDD, and its drain is connected to ground via a series connection of PMOS transistors M2, M3, and M4. The gates of the PMOS transistors M1 and M4 are connected to the output pin OUT1, and the gates of the PMOS transistors M2 and NMOS transistors M3 are both connected to the input pin IN3, which has a complementary signal to the output pin OUT1. The present invention aims to provide radiation hardening for the ring oscillator and improve its resistance to single-event interference.