496 results about "Ring oscillator" patented technology

The invention provides a clock signal generating circuit, a wired communication transceiver and electronic equipment, and the circuit outputs a first DC voltage comprising phase difference information and frequency difference information of a reference clock signal and a feedback clock signal through a phase frequency detection module. The pulse generator generates a narrow pulse signal based on the DC voltage and a reference clock signal, the oscillation frequency of each secondary ring oscillator in the cross-coupled ring oscillator is controlled by the first DC voltage, and the cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on each secondary ring oscillator. One output node in the cross coupling ring oscillator receives the narrow pulse signal, frequency and phase locking is completed in an injection locking mode, and the frequency divider is used for conducting frequency division processing on any high-frequency clock signal and outputting a feedback clock signal. Therefore, a high-frequency multi-phase clock signal with low phase noise and high phase precision can be generated by using the low-frequency reference clock signal.

An injection-locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator and a controller. The plurality of delay elements is connected in a loop and coupled to a global power supply. Each delay element has an input driven by a preceding stage and an output that drives a next stage. Each voltage control circuit couples one of the plurality of delay elements to the global power supply. The phase comparator is coupled to in-phase and quadrature outputs of the injection-locked oscillator. The controller is coupled to an output of the phase comparator and is configured to drive control inputs of the two or more voltage control circuits. The control input of each voltage control circuit determines a level of a voltage drop across the each voltage control circuit.

The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking, relates to the technical field of integrated circuits, and is used for solving the technical problems that an existing injection locking oscillator limits the frequency tuning range and cannot effectively suppress noise. The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking. The low-phase noise ring voltage-controlled oscillator comprises a first ring oscillator unit and a second ring oscillator unit, the n first ring oscillator units are connected in series to form a chain structure; the second ring oscillator unit is provided with a cross coupling inverter complementary injection unit and a tail current source injection unit; a first output end of the chain structure is connected with a second input end of the second ring oscillator unit, and a second output end of the chain structure is connected with a first input end of the second ring oscillator unit; a first signal is injected into a cross-coupling inverter complementary injection unit and a tail current source injection unit, and a second ring oscillator unit receives a second signal output by a chain structure and then outputs a third signal.

The utility model discloses a digital auxiliary simulation LDO circuit without an off-chip capacitor. A simulation main loop of the circuit comprises an error amplifier, a buffer stage circuit, a simulation power stage circuit and a VG voltage detection circuit. The digital auxiliary loop includes a digital control logic circuit, a ring oscillator circuit, and a digital power stage circuit. By introducing the digital power adjusting tube, the parasitic capacitance of the grid electrode of the analog power tube is reduced, the pole of the grid electrode is located at high frequency, and on the basis, the super source follower is added to push the pole to higher frequency, so that the circuit has better loop stability. In a steady state, the digital auxiliary loop is forbidden, and the analog main loop can ensure strict adjustment, low quiescent current and no switching noise at the output end; when a load current suddenly changes, a ring oscillator in the digital auxiliary loop is called to generate a clock signal, and the number of conducted digital power tubes is changed, so that response time is not limited by a clock period, dependence on an external clock is avoided, meanwhile, voltage precision and rapid transient response are guaranteed, and static power consumption of the circuit is reduced.

The invention provides a multi-phase clock generator which outputs N injection current signals corresponding to different phases by processing an input clock signal, N is an integral multiple of 4, and a cross-coupled loop is arranged in a cross-coupled ring oscillator. The loop is respectively coupled with output nodes in N / 4 secondary ring oscillators based on a phase sequence, and the secondary ring oscillators realize high-working-frequency and high-stability oscillation frequency output and low-error phase alignment through a cross coupling mechanism, so that the secondary ring oscillators can output N oscillation clock signals with equally-spaced phases, and the phase alignment is realized. Since the injection current signal is input into each output node in the secondary ring oscillator based on the phase sequence, the frequency and the phase of the secondary ring oscillator are locked, the frequency is the same as the frequency of the input clock signal, and the phase noise is very low, so that the frequency and the phase of the secondary ring oscillator are locked. According to the invention, a high-speed multi-phase clock signal with low phase noise and high phase precision can be generated.

A network of thermal sensors can be integrated within a semiconductor chip in a manner effective to provide local temperature monitoring and dynamic control of an associated device or system. The thermal sensors can include small area thermal ring oscillators located proximate to the core of a central processing unit (CPU), for example, and can be disposed on the chip at locations based on a designed output power density and attendant thermal gradients encountered during operation. In certain implementations, the presently-disclosed sensor configuration can be used to measure deviation from set threshold temperatures. Closed-loop control can be implemented to mitigate performance loss while adjusting the clock speed of the CPU independent of the system management unit.

The invention provides a transistor performance test method and a transistor performance test system, and the method comprises the steps: obtaining a signal state of a test signal after a preset oscillation time period based on the test signal outputted by an even-stage ring oscillator; obtaining a performance deviation result of the transistor according to the signal state; if the signal state is that the high level is maintained, the performance deviation result is that the performance of the PMOS transistor is superior to that of the NMOS transistor, if the signal state is that the low level is maintained, the performance deviation result is that the performance of the NMOS transistor is superior to that of the PMOS transistor, and if the signal state is that the oscillation is maintained, the performance deviation result is that the performance of the PMOS transistor and the performance of the NMOS transistor are balanced. Therefore, the preparation technology of the transistor is adjusted based on the performance deviation result of the transistor, and the preparation yield of the transistor is improved.

The invention discloses a multi-entropy source dynamic fusion true random number hardware generation system, which comprises a multi-entropy source acquisition module used for acquiring original entropy signals generated by at least two heterogeneous physical entropy sources in parallel, the heterogeneous physical entropy sources comprising an entropy source based on semiconductor junction thermal noise and an entropy source based on ring oscillator phase jitter; the entropy preprocessing module is used for carrying out adaptive gain adjustment and frequency band filtering on each original entropy signal and converting the original entropy signals into digital bit streams; the entropy source quality evaluation module is used for receiving each digital bit stream in real time and calculating a real-time quality evaluation score of each entropy source based on statistical characteristics of the digital bit streams, i is an entropy source identifier, and t is a time sequence; according to the method, the high randomness, high safety and high reliability of true random number generation can be fundamentally improved.

An injection-locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator and a controller. The plurality of delay elements is connected in a loop and coupled to a global power supply. Each delay element has an input driven by a preceding stage and an output that drives a next stage. Each voltage control circuit couples one of the plurality of delay elements to the global power supply. The phase comparator is coupled to in-phase and quadrature outputs of the injection-locked oscillator. The controller is coupled to an output of the phase comparator and is configured to drive control inputs of the two or more voltage control circuits. The control input of each voltage control circuit determines a level of a voltage drop across the each voltage control circuit.

The invention discloses a ring oscillator which comprises a bias module and an oscillation module. The bias module comprises a current unit and a conversion unit which are connected, the current unit is used for generating a first current and a second current based on the reference current, and the conversion unit is used for generating a bias voltage based on the second current or generating the bias voltage based on a current difference between the first current and the second current; and a driving current is generated based on the current difference between the first current and the second current, the oscillation module is connected with the bias module to receive the bias voltage and the driving current, and an oscillation signal is generated based on the bias voltage and the driving current. The ring oscillator obtains a stable bias voltage as a working voltage of the oscillation module through two currents generated by the bias module based on a reference current, and obtains a driving current of the oscillation module based on a difference current of the two currents. The current has good temperature stability, so that the oscillation precision can be ensured.

The invention aims to provide a phase noise and maximum oscillation frequency adjustable ring oscillator and a control method. The oscillator comprises a main path and a third auxiliary path, the third auxiliary path is connected with the main path and is used for improving the oscillation frequency; by inserting the adjustable phase inverter, when the frequency of the ring oscillator does not meet the specification under the extreme corner condition, the oscillation frequency is improved by adjusting the phase inverter to sacrifice some phase noise.

The invention relates to the technical field of integrated circuits, and discloses a clock signal generation circuit capable of reducing EMI (Electro-Magnetic Interference) through a jittering frequency technology, which comprises a reference voltage and jittering frequency module for generating a jittering Vref signal, a frequency regulation module for generating a Vout signal, and an operational amplifier module for comparing the Vout signal with the Vref signal, according to the high-speed clock, the ring oscillator module is used for generating clock signals with jitter frequency characteristics, the enabling control module is used for generating target clock signals, clock signal energy is distributed in a related frequency range instead of a single frequency point, and the frequency spectrum of the high-speed clock is broadened to a wider field.

The invention provides a financial data encryption transmission system and method based on a circuit board. The system comprises an identity authentication module, a main control circuit module, a secret key processing module and a distributed storage module which are connected in sequence, and a security monitoring module connected with the secret key processing module, the identity authentication module adopts a biological characteristic matching algorithm based on mahalanobis distance to realize identity authentication, the key processing module adopts a key fragmentation technology based on a threshold scheme, a true random number generator realized by combining a ring oscillator ensures key security, the distributed storage module adopts Reed-Solomon coding to realize reliable fragmentation storage, and the distributed storage module adopts a random number generator realized by combining a random number generator realized by combining a random number generator realized by combining a random number generator realized by a random number generator. The safety monitoring module monitors temperature, voltage and physical invasion behaviors in real time; the method can effectively improve the safety and reliability of the financial data transmission process, and is suitable for financial data processing scenes needing high safety guarantee.

A ring voltage-controlled oscillator with an adjustable output phase comprises a feed-forward ring oscillator and a voltage bias circuit, the voltage bias circuit outputs a control current to the feed-forward ring oscillator, and an input voltage of the voltage bias circuit is clamped by an operational amplifier and applied to a resistor so as to control the current. And the output clock frequency is changed through the feed-forward ring oscillator. Phase adjustment is achieved by creating an unbalanced feed-forward path in the ring oscillator, the ring oscillator has the capability of outputting frequency clock signals above GHz and a wide output frequency adjustment range, and the output phase of each clock can be controlled through an internally integrated control word structure. The output phase change is only related to the unbalance proportion between different stages, and the phase adjustable capability does not change along with the frequency change, so that the phase adjustment can be realized in a wider clock frequency range.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

The invention relates to a passive wireless temperature sensor circuit, which comprises a transceiving antenna, an RF-DC rectifier circuit, a temperature sensing circuit and a backscatter circuit, the RF-DC rectifier circuit receives external radio frequency energy based on the transmit-receive antenna and then outputs direct current for power supply. The temperature sensing circuit comprises a complementary absolute temperature voltage generator and a ring oscillator; the complementary absolute temperature voltage generator comprises an MOS tube and generates CTAT voltage based on temperature characteristics of the MOS tube. The ring oscillator converts the CTAT voltage into an oscillation frequency signal of the ring oscillator and then outputs a square wave frequency signal with a negative temperature coefficient; the backscattering circuit backscatters the square wave frequency signal through the transceiving antenna; the CTAT key generation circuit built by the MOS tube generates CTAT voltage, a temperature frequency conversion chain is built through the CTAT voltage and the ring oscillator, temperature information is converted into frequency information of the oscillator, the power consumption of the temperature sensing circuit can be effectively reduced, and meanwhile the voltage coefficient of the CTAT voltage is increased by combining the temperature characteristic of the MOS tube.

A test element group (TEG) disposed adjacent to at least one memory chip on a wafer includes a ring oscillator configured to output a clock signal based on a direct current (DC) signal received through a first pad and from a test device, a first divider configured to divide the clock signal and to output a first divided signal, and a sequential circuit set configured to receive the clock signal and the first divided signal, to generate a test signal based on the clock signal and the first divided signal, and to output the test signal to the test device through a second pad. The sequential circuit set includes a sequential circuit having a configuration corresponding to at least one circuit included in the at least one die.

A device including delay cells connected in series and in a feedback loop to provide a ring oscillator. At least one of the delay cells in the ring oscillator is a stacked gate delay cell that includes two or more PMOS transistors having first drain / source paths connected in series to each other and having first gates connected to each other and two or more NMOS transistors having second drain / source paths connected in series to each other and to the first drain / source paths and having second gates connected to each other and to the first gates.

Aspects of the disclosure are directed to voltage sensing for safety-critical applications. In accordance with one aspect, the disclosure includes a multi-phase ring oscillator (RO) configured to operate in a first voltage domain; a frequency counter coupled to the multi-phase RO, the frequency counter configured to accumulate a plurality of phase cycles from the multi-phase RO over a time duration to generate a digital count word; an alarm processor coupled to the frequency counter, the alarm processor configured to receive an alarm state signal from the frequency counter; and a heartbeat detector coupled to the multi-phase RO, the heartbeat detector configured to operate in a second voltage domain and configured to detect a periodic recurrence of a heartbeat pulse to determine an integrity of the sensor function as a whole and alarm state signal in particular.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.

A random number generator comprises a ring generator and one or more inverter-based ring oscillators. The one or more inverter-based ring oscillators is configured to inject bits into the ring generator at a plurality of location. If there is more than one inverter-based ring oscillators, the inverter-based ring oscillators may have different numbers of inverting elements and may inject bits into the ring generator at different locations. At least one of the one or more inverterbased ring oscillators may be configured to inject bits into the ring generator at different locations from outputs of some or all its inverting elements. The random number generator may further comprise blocking circuitry configured to convert, based on a blocking signal, the ring generator into a circular shift register by blocking both the injection from the plurality of inverter-based ring oscillators and internal feedbacks in the ring generator.

The invention discloses a low-power-consumption phase-locked loop circuit with an automatic frequency calibration function. Comprising a voltage-controlled oscillator, an automatic frequency calibration module, a programmable frequency divider, a phase frequency detector, a plurality of charge pump arrays and a switch filter, wherein the automatic frequency calibration module and the programmable frequency divider are in signal connection with the voltage-controlled oscillator; the phase frequency detector is in signal connection with the programmable frequency divider; the charge pump arrays are in signal connection with the phase frequency detector; the switch filter is in signal connection with the voltage-controlled oscillator; the voltage-controlled oscillator comprises a plurality of delay units, and the voltage-controlled oscillator is an annular oscillator formed by cascading a plurality of delay unit rings. The delay unit is a cross-coupled structure based on an inverter and comprises a plurality of transistors, and the plurality of transistors comprise a plurality of PMOS (P-channel Metal Oxide Semiconductor) transistors and a plurality of NMOS (N-channel Metal Oxide Semiconductor) transistors. According to the invention, under the low power supply voltage, four-phase intermediate frequency signals are output with extremely low power consumption, and the application requirements of rapid locking and low noise are met.

Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.

Multi-phase oscillator circuits are disclosed. According to one aspect, a multi-phase oscillator circuit for a millimeter wave (mmW), transceiver is provided. The multi-phase oscillator circuit includes a plurality of inductor-coupled ring oscillators, each inductor-coupled ring oscillator comprising a plurality of single stage active delay cells, an output of each of the plurality of inductor-coupled ring oscillators being inductively coupled to an output of another one of the plurality of inductor-coupled ring oscillators.

The invention relates to the field of electronic oscillation circuits, and discloses a low-noise ring oscillator. The ring oscillator comprises an oscillation loop formed by connecting 2N + 1 stages of delay unit modules end to end, each stage of delay unit module comprises a complementary MOS tube and a source electrode degeneration resistor, one end of the source electrode degeneration resistor is connected with a source electrode of the complementary MOS tube, the other end of the source electrode degeneration resistor is connected with a common potential, and the source electrode degeneration resistor is made of a low-noise polycrystalline silicon resistor. By introducing the source electrode degeneration resistor into the delay unit module and utilizing the characteristic that a resistor element has lower noise compared with an MOS (Metal Oxide Semiconductor) device, the proportion of an MOS tube in the integral noise contribution is effectively reduced, so that the phase noise performance of the ring oscillator is improved, and the ring oscillator is particularly suitable for an electronic circuit system needing a high-quality clock signal.

The invention relates to the technical field of state monitoring, in particular to an optical storage device state monitoring method and system based on an FPGA. The method comprises the following steps: acquiring FPGA structure data; deploying a ring oscillator unit in an FPGA idle logic resource area based on the FPGA structure data, and configuring a leakage current measurement channel on an FPGA programmable I / O pin to obtain leakage current measurement channel configuration data; acquiring RO oscillation frequency data and grid leakage current data according to the leakage current measurement channel configuration data; and performing mapping calculation on the RO oscillation frequency data and the grid leakage current data based on a preset temperature calibration curve and a voltage calibration curve. Through high-precision real-time monitoring and multiple regression modeling based on the FPGA, the diagnosis precision and intelligent early warning capability of the temperature and stress of the key area of the optical storage equipment are effectively improved, and the problem that a traditional monitoring system is insufficient in accuracy, real-time performance and pertinence is solved.

The invention particularly relates to an integrated circuit coupling failure analysis method based on a neural network. The method comprises the following steps: constructing a ring oscillator circuit; inputting a preset stress condition into a failure analysis model based on a neural network, and obtaining threshold voltage degradation amount prediction data output by the model; wherein the failure analysis model is used for predicting threshold voltage degradation of the PMOS device; the stress condition data is matched with the ring oscillator circuit; configuring the threshold voltage degradation amount prediction data to a grid electrode of a key transistor in a ring oscillator circuit, and obtaining corresponding circuit frequency degradation data; and performing data comparison on the circuit frequency degradation data and preset verification data to obtain a first data comparison result, and generating coupling failure analysis data based on the first data comparison result. According to the method, an analysis model for coupling failure of the NBTI and the HCD of the PMOS transistor is established, so that errors of data analysis are reduced, and the application range is widened.

The invention provides an annular voltage-controlled oscillator for a micro-display. The annular voltage-controlled oscillator comprises a band-gap reference current source, an oscillator delay circuit, a temperature sensor and a voltage-controlled gain adjusting circuit, the temperature sensor is connected with the band-gap reference current source and is used for generating a control code SWA and controlling a current value generated by the band-gap reference current source; the band-gap reference current source is connected with the control end of the oscillator delay circuit and is used for copying a generated current value to the oscillator delay circuit; and the voltage-controlled gain adjusting circuit is connected with the output end of the oscillator delay circuit and is used for generating a control code SWB and controlling the oscillation frequency of the oscillator delay circuit. By adopting the temperature compensation and voltage-controlled gain adjustment circuit, the basic current and the load capacitance are adjusted according to the change of the temperature and the change of the control voltage, so that the output frequency of the ring oscillator does not change along with the temperature, and the constant voltage-controlled gain is realized under different control voltages.

The invention discloses an all-digital PVT sensor based on a ring oscillator, and relates to the field of PVT sensors, the all-digital PVT sensor comprises a process sensing circuit, a voltage sensing circuit and a temperature sensing circuit, the process sensing circuit comprises a process detection ring oscillator, the voltage sensing circuit comprises a voltage detection ring oscillator, and the temperature sensing circuit comprises a temperature detection ring oscillator. The temperature sensing circuit comprises a temperature sensitive ring oscillator; under the control of an enable signal, the process detection ring oscillator, the voltage detection ring oscillator and the temperature-sensitive ring oscillator start oscillation, and the process corner, the temperature and the power supply voltage of the detected chip are determined based on the oscillation frequencies of the process detection ring oscillator, the voltage detection ring oscillator and the temperature-sensitive ring oscillator. The PVT sensor is completely realized based on a digital circuit, an additional analog module does not need to be introduced, the area overhead is greatly reduced, and the PVT sensor has remarkable area advantage and structural simplicity while the high-precision detection capability is maintained.