305 results about "Ring oscillator" patented technology

The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking, relates to the technical field of integrated circuits, and is used for solving the technical problems that an existing injection locking oscillator limits the frequency tuning range and cannot effectively suppress noise. The invention discloses a low-phase noise ring voltage-controlled oscillator based on multiphase injection locking. The low-phase noise ring voltage-controlled oscillator comprises a first ring oscillator unit and a second ring oscillator unit, the n first ring oscillator units are connected in series to form a chain structure; the second ring oscillator unit is provided with a cross coupling inverter complementary injection unit and a tail current source injection unit; a first output end of the chain structure is connected with a second input end of the second ring oscillator unit, and a second output end of the chain structure is connected with a first input end of the second ring oscillator unit; a first signal is injected into a cross-coupling inverter complementary injection unit and a tail current source injection unit, and a second ring oscillator unit receives a second signal output by a chain structure and then outputs a third signal.

The invention discloses a multi-entropy source dynamic fusion true random number hardware generation system, which comprises a multi-entropy source acquisition module used for acquiring original entropy signals generated by at least two heterogeneous physical entropy sources in parallel, the heterogeneous physical entropy sources comprising an entropy source based on semiconductor junction thermal noise and an entropy source based on ring oscillator phase jitter; the entropy preprocessing module is used for carrying out adaptive gain adjustment and frequency band filtering on each original entropy signal and converting the original entropy signals into digital bit streams; the entropy source quality evaluation module is used for receiving each digital bit stream in real time and calculating a real-time quality evaluation score of each entropy source based on statistical characteristics of the digital bit streams, i is an entropy source identifier, and t is a time sequence; according to the method, the high randomness, high safety and high reliability of true random number generation can be fundamentally improved.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

The invention relates to a passive wireless temperature sensor circuit, which comprises a transceiving antenna, an RF-DC rectifier circuit, a temperature sensing circuit and a backscatter circuit, the RF-DC rectifier circuit receives external radio frequency energy based on the transmit-receive antenna and then outputs direct current for power supply. The temperature sensing circuit comprises a complementary absolute temperature voltage generator and a ring oscillator; the complementary absolute temperature voltage generator comprises an MOS tube and generates CTAT voltage based on temperature characteristics of the MOS tube. The ring oscillator converts the CTAT voltage into an oscillation frequency signal of the ring oscillator and then outputs a square wave frequency signal with a negative temperature coefficient; the backscattering circuit backscatters the square wave frequency signal through the transceiving antenna; the CTAT key generation circuit built by the MOS tube generates CTAT voltage, a temperature frequency conversion chain is built through the CTAT voltage and the ring oscillator, temperature information is converted into frequency information of the oscillator, the power consumption of the temperature sensing circuit can be effectively reduced, and meanwhile the voltage coefficient of the CTAT voltage is increased by combining the temperature characteristic of the MOS tube.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

A random number generator comprises a ring generator and one or more inverter-based ring oscillators. The one or more inverter-based ring oscillators is configured to inject bits into the ring generator at a plurality of location. If there is more than one inverter-based ring oscillators, the inverter-based ring oscillators may have different numbers of inverting elements and may inject bits into the ring generator at different locations. At least one of the one or more inverterbased ring oscillators may be configured to inject bits into the ring generator at different locations from outputs of some or all its inverting elements. The random number generator may further comprise blocking circuitry configured to convert, based on a blocking signal, the ring generator into a circular shift register by blocking both the injection from the plurality of inverter-based ring oscillators and internal feedbacks in the ring generator.

The invention relates to the technical field of state monitoring, in particular to an optical storage device state monitoring method and system based on an FPGA. The method comprises the following steps: acquiring FPGA structure data; deploying a ring oscillator unit in an FPGA idle logic resource area based on the FPGA structure data, and configuring a leakage current measurement channel on an FPGA programmable I / O pin to obtain leakage current measurement channel configuration data; acquiring RO oscillation frequency data and grid leakage current data according to the leakage current measurement channel configuration data; and performing mapping calculation on the RO oscillation frequency data and the grid leakage current data based on a preset temperature calibration curve and a voltage calibration curve. Through high-precision real-time monitoring and multiple regression modeling based on the FPGA, the diagnosis precision and intelligent early warning capability of the temperature and stress of the key area of the optical storage equipment are effectively improved, and the problem that a traditional monitoring system is insufficient in accuracy, real-time performance and pertinence is solved.

The invention discloses an all-digital PVT sensor based on a ring oscillator, and relates to the field of PVT sensors, the all-digital PVT sensor comprises a process sensing circuit, a voltage sensing circuit and a temperature sensing circuit, the process sensing circuit comprises a process detection ring oscillator, the voltage sensing circuit comprises a voltage detection ring oscillator, and the temperature sensing circuit comprises a temperature detection ring oscillator. The temperature sensing circuit comprises a temperature sensitive ring oscillator; under the control of an enable signal, the process detection ring oscillator, the voltage detection ring oscillator and the temperature-sensitive ring oscillator start oscillation, and the process corner, the temperature and the power supply voltage of the detected chip are determined based on the oscillation frequencies of the process detection ring oscillator, the voltage detection ring oscillator and the temperature-sensitive ring oscillator. The PVT sensor is completely realized based on a digital circuit, an additional analog module does not need to be introduced, the area overhead is greatly reduced, and the PVT sensor has remarkable area advantage and structural simplicity while the high-precision detection capability is maintained.

The invention relates to a time sequence generation device. The present specification relates to an apparatus comprising a ring oscillator comprising a plurality of gates, each gate transmitting a fast clock signal. The first shift register includes successive first flip-flops, each of which is synchronized with a same first clock signal corresponding to one of the fast clock signals. The first shift register is looped back on itself and implements a second oscillator in which each first flip-flop transmits a slow clock signal. The second shift register includes successive second flip-flops, each of which is synchronized with a same second clock signal corresponding to one of the slow clock signals.

A phase-locked loop. The phase-locked loop including a time-to-digital converter for acquiring a phase of a reference signal. A feedback signal formed from an output signal of the phase-locked loop is fed to the time-to-digital converter. The phase-locked loop including a digital-to-time converter which is configured to apply dithering to the feedback signal or to the reference signal. The digital-to-time converter is part of a ring oscillator with a predefined oscillation frequency. The phase-locked loop includes an evaluation unit for acquiring an actual frequency of the ring oscillator.

This provides a clock generation circuit that reduces the frequency of the clock signal when the power supply voltage increases. [Solution] The clock generation circuit 100 of the present invention includes a reference current setting unit 20, a bias voltage generation unit 110, and a ring oscillator 40. The bias voltage generation unit 110 generates a PBIAS voltage to be applied to each gate of the PMOS transistor MP3 of the ring oscillator 40, and an NBIAS voltage to be applied to each gate of the NMOS transistor MN3. In response to the power supply voltage Vcc reaching the target voltage, the bias voltage generation unit 110 increases the PBIAS voltage, thereby reducing the current supplied by the PMOS transistor MP3 and lowering the frequency of the clock signal OSC.

The application relates to a high-precision addressable ring oscillator test chip, method, device and medium, which comprises an addressing module, an output module and a plurality of ring oscillator test modules; the ring oscillator test module comprises a signal transmission module, a multifunctional test module and a plurality of ring oscillator test structures; the addressing module is used for selecting a ring oscillator test structure from the ring oscillator test structures of the plurality of ring oscillator test modules to perform a communication test; the multifunctional test module can switch the voltage compensation mode or the small-current test mode of the ring oscillator test structure based on a received control signal; when the characteristic parameters of the ring oscillator are measured, the voltage compensation mode can utilize voltage drop compensation to reduce the influence of the resistance voltage drop introduced in the test path, effectively improving the measurement precision, and the small-current test mode can effectively measure the static power supply current of the ring oscillator.

The utility model discloses a vehicle-mounted short-wave double-loop antenna lodging device, which comprises a case, a driving assembly, an antenna fixing platform and a rotating arm, the driving assembly is arranged in the case; the antenna fixing platform and the case are oppositely arranged, and the antenna fixing platform is provided with an antenna large-ring oscillator mounting interface, an antenna small-ring oscillator interface, an antenna supporting rod mounting interface, an antenna large-ring oscillator antenna adjustment connecting port and an antenna small-ring oscillator antenna adjustment connecting port; the antenna large-ring oscillator mounting interface is connected with the antenna large-ring oscillator antenna tuning connector; the antenna small ring oscillator interface is arranged at the center of the antenna support rod mounting interface and is connected with the antenna small ring oscillator antenna adjustment connector; and two ends of the rotating arm are respectively connected with the case and the side wall of the antenna fixing platform. According to the utility model, the installation height of the dual-ring antenna can be effectively reduced, so that the impact, vibration and wind resistance borne by the dual-ring antenna are reduced.

The invention discloses a low-phase noise ring oscillator of a distributed network, which belongs to the technical field of integrated circuits, and comprises a first ring oscillator core, a second ring oscillator core and a third ring oscillator core which have the same structure, the first ring oscillator core, the second ring oscillator core and the third ring oscillator core are closed-loop structures formed by a plurality of phase inverters and a plurality of coupling units; a distributed coupling network is formed among the first ring oscillator core, the second ring oscillator core and the third ring oscillator core; the first input end of each coupling unit in the first ring oscillator core is connected with the second input end of the corresponding coupling unit in the third ring oscillator core, and the second input end of each coupling unit in the first ring oscillator core is connected with the first input end of the corresponding coupling unit in the second ring oscillator core; and the second input end of the coupling unit in the second ring oscillator core is connected with the first input end of the corresponding coupling unit in the third ring oscillator core. On the premise that power consumption and the chip area are not remarkably increased, the phase noise performance is remarkably improved.

According to one embodiment, an oscillation circuit includes: a ring oscillator; a first transistor having a gate terminal coupled to an output port of the ring oscillator and a drain terminal coupled to a first node; a second transistor having a drain terminal and a gate terminal that are both coupled to the first node; a third transistor having a gate terminal coupled to the first node and a drain terminal coupled to a second node; a fourth transistor having a gate terminal coupled to the first node and a drain terminal coupled to a third node; a fifth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node; and a voltage buffer having an input port coupled to the second node.

A method for measuring a time-of-flight interval in a depth sensing system includes generating a coarse time count using a global clock signal shared across a plurality of pixels and external to the sensor array, wherein the coarse time count provides the most significant bits of the time-of-flight interval free of inter-pixel process variation; generating an intermediate time count within a pixel using a local ring oscillator based on completed oscillation cycles during a measurement interval; generating a fine time residual within the pixel based on at least one phase state of the ring oscillator, wherein the fine time residual provides the least significant bits; and deriving the time-of-flight interval from a combination of the coarse time count, the intermediate time count, and the fine time residual.

The present application relates to a kind of threshold adjustable RO PUF device and output sequence method, belong to information security technical field, solve the problem that the two key design indexes of existing RO PUF uniqueness and stability are difficult to compromise implementation.For threshold adjustment module, at least two ring oscillators and at least one counting comparison module;Wherein, every two ring oscillators is a group, and each group corresponds to a counting comparison module;Threshold adjustment module is used to set the threshold gear of the clock oscillation frequency difference generated by every two ring oscillators in each group;Wherein, threshold gear is adjustable;Counting comparison module is used to receive threshold gear and the clock oscillation frequency generated by two ring oscillators in corresponding group, obtains corresponding frequency difference threshold according to threshold gear, and the clock oscillation frequency difference generated by two ring oscillators is counted, obtains a bit output by comparing clock oscillation frequency difference with frequency difference threshold;The bit output corresponding to all groups is used as the output response data of RO PUF.

The present invention discloses a ring oscillator, chip, and electronic device that utilizes reverse clock compensation for reinforcement. The ring oscillator includes a compensation reinforcement circuit for reinforcing the output pin OUT1 of a delay node using reverse clock compensation. The compensation reinforcement circuit includes two PMOS transistors M1 and M2, and two NMOS transistors M3 and M4. The source of the PMOS transistor M1 is connected to voltage VDD, and its drain is connected to ground via a series connection of PMOS transistors M2, M3, and M4. The gates of the PMOS transistors M1 and M4 are connected to the output pin OUT1, and the gates of the PMOS transistors M2 and NMOS transistors M3 are both connected to the input pin IN3, which has a complementary signal to the output pin OUT1. The present invention aims to provide radiation hardening for the ring oscillator and improve its resistance to single-event interference.

The application discloses a ring oscillator circuit, a PCB and a controller, comprising a voltage bias unit, an input end of the voltage bias unit being connected with an external control signal end, a first bias voltage output end and a second bias voltage output end of the voltage bias unit being respectively connected with an enable end of a delay unit, the second bias voltage output end of the voltage bias unit being further connected with an enable end of a buffer unit, an inverting output end of the delay unit being connected with a same-phase input end thereof and an input end of a first buffer driving unit, an output end of the first buffer driving unit being connected with an inverting input end of the buffer unit, a same-phase output end of the delay unit being connected with an inverting input end thereof and an input end of a second buffer driving unit, and an output end of the second buffer driving unit being connected with a same-phase input end of the buffer unit, so that the first buffer driving unit and the second buffer driving unit are used to pre-drive an original oscillation signal, and the clock signal output by the buffer unit has greater driving current output capacity.

A circuit includes a voltage conversion unit from a power management unit library. The voltage conversion unit comprises a high-voltage domain subunit and a low-voltage domain subunit, wherein multiple high-voltage conversion modules in the high-voltage domain subunit and multiple low-voltage conversion modules in the low-voltage domain subunit are alternately connected to form a ring oscillator. The circuit includes a first control signal generation unit, a first selection output unit, a second control signal generation unit, and a second selection output unit. This invention enables efficient testing of the voltage conversion unit.

A control circuit for a ring oscillator, and a ring oscillation apparatus, relating to the field of oscillator signals. A power supply provides a power supply voltage for the ring oscillator by means of a reference voltage generation module and an operational amplifier, and a feedback control module regulates the voltage of a non-inverting input end of the operational amplifier on the basis of a real-time situation of the frequency of an output signal of the ring oscillator, thereby affecting the power supply voltage outputted by means of the operational amplifier to the ring oscillator. The frequency of the output signal of the ring oscillator is adjusted by regulating the power supply voltage to form feedback control on the output signal of the ring oscillator, and the frequency of the output signal of the ring oscillator is kept within a stable small range by means of feedback of dynamic adjustment, thereby improving the stability and reliability of the frequency of the output signal of the ring oscillator, reducing frequency distribution of the output signal of the ring oscillator, avoiding the impact of factors such as device parameters on the frequency of the output signal of the ring oscillator, and thus improving frequency accuracy.

True random number generators including ring oscillator circuits leveraging frequency and phase collapse events are described. An example ring oscillator circuit (ROC) includes a first oscillating loop comprising a first set of inverters, where the first oscillating loop is to oscillate at a first frequency and phase. The ROC further includes a second oscillating loop comprising a second set of inverters, which differs from the first set of inverters either in terms of a type of inverters or a number of inverters. The second oscillating loop is to oscillate at a second frequency and phase, different from the first frequency and phase. The ROC further includes a third oscillating loop to, as a result of mode switching from a first mode of operation into a second mode of operation, oscillate at a third frequency and phase, different from the first frequency and phase and the second frequency and phase.

The application discloses a ring oscillator and a phase-locked loop. The ring oscillator comprises: the output terminals of nth and mth delay units are connected to the main input terminals of (n+1)th and 1st delay units respectively; m is an odd number, the electrode polarity of the output terminal of the nth delay unit is opposite to the electrode polarity of the main input terminal of the (n+1)th delay unit, or the electrode polarity of the output terminal of the mth delay unit is opposite to the electrode polarity of the main input terminal of the 1st delay unit, m is an even number, the electrode polarity of the output terminal of the nth delay unit is the same as the electrode polarity of the main input terminal of the (n+1)th delay unit, or the electrode polarity of the output terminal of the mth delay unit is the same as the electrode polarity of the main input terminal of the 1st delay unit, n comprises an integer greater than or equal to 1 and less than m; the auxiliary input terminals of the (n+1)th and 1st delay units are connected to the main input terminals of the nth and mth delay units respectively. The technical scheme of the application can realize a ring oscillator with a high oscillation frequency.

This invention discloses a high-speed, high-precision voltage descent monitoring circuit, solving the problem of accurate and timely monitoring of voltage descent phenomena in large-scale integrated circuits, belonging to the fields of digital integrated circuit design and power management. This invention provides an optimized design method for ring oscillator point circuits, using standard cell type, threshold, drive capability, and power consumption as variables to find the ring oscillator circuit design with the highest voltage sensitivity, improving the resolution of the voltage descent monitoring circuit; it provides a one-fold, compact ring oscillator layout design to ensure load balance between nodes; it provides a Nyquist counter design to count the number of times nodes flip over a period of time, improving the voltage monitoring range and solving the metastable sampling problem of traditional counters; and it provides a high-speed voltage quantization circuit that processes coarse and fine quantization in parallel, improving the maximum sampling rate and quantization rate of the voltage descent monitoring circuit.

The invention discloses a voltage-controlled oscillator circuit, comprising: a current control circuit module configured to receive an input voltage and generate a control current responsive to the input voltage; the ring oscillator circuit module is connected with the current control circuit module and comprises a multi-stage inverter and a current adjusting unit which are connected in series to form a ring; the current adjusting unit is respectively connected to the current control circuit module and each stage of the multi-stage phase inverter, and is configured to synchronously and symmetrically adjust the pull-up current and the pull-down current of each stage of phase inverter in the multi-stage phase inverter in response to the control current; and the output driving circuit module is connected with an output node of the ring oscillator circuit module so as to shape and drive the oscillation signal generated by the ring oscillator circuit module and output a clock signal with a duty ratio of 50%. The circuit structure is simplified, the chip area is saved, the oscillator is allowed to directly work at the target frequency instead of double frequency, and the overall power consumption is reduced.

The invention provides a true random number generator based on a multi-ring oscillator and a method, and is used for designing a full-digital FPGA (Field Programmable Gate Array) true random number generator architecture so as to effectively overcome many defects of a traditional random number generator. The advantages of pure digital implementation, environmental interference resistance, high throughput, interface self-verification, portability, expansibility design, interface reliability and the like are considered, and high-quality random number application requirements related to different application scenes in practical application can be met.

An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A1-A4) connected in a ring and has a first and a second supply terminal (s1, s2). Each amplifier circuit (A1-A4) comprises an input transistor (M1) whose gate is connected to an input (in) of the amplifier circuit, whose drain is connected to an internal node (x) of the amplifier circuit, and whose source is connected to the first supply terminal (s1). Furthermore, each amplifier circuit (A1-A4) comprises a first resonance circuit (R1) comprising a first inductor (L S ) and a first capacitor (C S ), wherein the first inductor (L S ) is connected between the internal node (x) and an output (out) of the amplifier circuit, and the first capacitor (C S ) is connected between the output (out) of the amplifier circuit and one of the first and second supply terminals (s1, s2). Furthermore, each amplifier circuit (A1-A4) comprises a second resonance circuit (R2) comprising a second inductor (L P ) and a second capacitor (C P ), wherein the second inductor (L P ) and the second capacitor (C P ) are connected in parallel between the internal node (x) and the second supply terminal (s2).

This application provides a security monitoring method and a microprocessor architecture. The method is applied to a microprocessor architecture including a processor core and a security monitoring module. The security monitoring module includes a ring oscillator with adjustable inverter stages. The method includes: when the security monitoring module detects a change in the process corner of the ring oscillator, it adjusts the inverter stages of the ring oscillator according to the current process corner of the ring oscillator and the operating frequency of the monitored module, so that the operating frequency of the ring oscillator is consistent with the operating frequency of the monitored module. The monitored module includes any module in the microprocessor architecture, and the ring oscillator serves as a reference frequency source for security monitoring of the monitored module. The above method can provide a stable reference frequency within the microprocessor architecture, thereby improving the accuracy and effectiveness of security monitoring of the monitored module.

The application belongs to the field of integrated circuits, and discloses an analog-to-digital converter with a sub-range ring oscillator time-to-digital converter based on a phase-locked loop, which adopts a multi-channel time-interleaved architecture, and a front end completes coarse quantization in a voltage domain through a SAR circuit, and a residual signal is subjected to amplification and voltage-to-time conversion, and then fine quantization in a time domain is realized by a rear-end sub-range ring oscillator TDC. In the design, RS-PL closed-loop regulation and control SRRO are introduced, frequency multiplication is realized by using a phase-locked loop, high resolution can be realized by using two N-stage ring oscillators and a locking circuit, frequency drift caused by PVT variation is compensated, and the problem that the minimum quantization time step of a traditional TDC is prone to drift is solved; a coarse-fine double-ring sub-range structure cooperates with a full-digital calibration circuit to correct cross-border error and phase offset error, and the quantization precision is improved. The whole oscillation source can be shared by multiple channels, and the hardware area and power consumption are effectively reduced. The device has the characteristics of high speed, low power consumption and anti-interference, and is suitable for high-speed communication scenes.

The invention discloses a delay unit and a broadband multi-sub-band ring oscillator circuit, the delay unit is characterized in that a PM5, a PM7, a PM13 and a first current limiting tube are connected in parallel between a source electrode and a drain electrode of a PM3, the first current limiting tube comprises a PM9, a PM11 and sub-band control switches CB2 and CB12, a PM6, a PM8, a PM14 and a second current limiting tube are connected in parallel between a source electrode and a drain electrode of a PM4, and the second current limiting tube comprises a PM10, a PM12 and sub-band control switches CB2 and CB12; switched capacitors C1-C4 are arranged between the VOP and the VON; the first group of switched capacitors and the second group of switched capacitors are connected in parallel between the VOP and the VON; the first group of switched capacitors comprises C1 and C2 which are connected in series and CB1 for controlling the switching of the C1 and C2, and the second group of switched capacitors comprises C3 and C4 which are connected in series and CB2 for controlling the switching of the C3 and C4; grid electrodes of the PM5 and the PM6 are connected with the sub-band control switch RB1, grid electrodes of the PM7 and the PM8 are connected with the RB2, grid electrodes of the PM9 and the PM10 are connected with the CB2, grid electrodes of the PM11 and the PM12 are connected with the CB12, and a control signal of the CB12 is generated by control signals of the CB1 and the CB2 through an AND gate.