341results about "Analogue conversion" patented technology

The invention relates to an integrator circuit for eliminating thermal noise and a Delta-sigma modulator, and belongs to the technical field of electronic signal processing, the modulator comprises at least two stages of integrators, a quantizer, a feedback DAC and an adder; the integrator comprises an integrator circuit, and the integrator circuit comprises a sampling module for sampling an input signal source; the double-path multi-phase clock control pre-amplification auxiliary storage circuit module alternately samples and stores thermal noise voltage and offset voltage; the integral amplifier is used for amplifying a signal output by the double-path multi-phase clock control pre-amplification auxiliary storage circuit module; and the integrating capacitor is connected between the integrating amplifier and the two-way multi-phase clock control pre-amplification auxiliary storage circuit module, and feeds back the signal after integration processing to the two-way multi-phase clock control pre-amplification auxiliary storage circuit module to realize signal modulation and noise shaping. The thermal noise introduced in the sampling process is effectively reduced, and the area of the whole chip is reduced while the signal-to-noise ratio is improved.

The invention relates to the technical field of amplifiers, and discloses an analog-to-digital converter combination instrument amplifier which comprises a first-stage amplifier, the first-stage amplifier is in signal connection with a second-stage amplifier, the second-stage amplifier is in signal connection with a front-end low-pass filter (LPF), the front-end low-pass filter (LPF) is in signal connection with an analog-to-digital converter (ADC), and the analog-to-digital converter (ADC) is in signal connection with the analog-to-digital converter. And an unbalanced input-to-balanced differential circuit output module is arranged between the second-stage amplifier signal and a front-end low-pass filter (LPF). From the perspective of signal processing and conversion, a precise signal transition bridge is constructed by adding an unbalanced input-to-balanced differential circuit output module, unbalanced signals output by a second-stage amplifier are converted into double-end balanced differential signals, common-mode noise interference is effectively resisted through a differential transmission mode, the signal purity is guaranteed, and the signal quality is improved. The front-end low-pass filter and the analog-to-digital converter are adaptive to differential signals, so that the signal transmission is stable and anti-interference, and the analog-to-digital conversion is more accurate.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

This application relates to sensing of signals with a common-mode variation. Embodiments describe a switching driver circuit with a modulator configured to control modulation of an output node between different switching voltages and a current sensor configured to sense a voltage drop across a sense resistor connected in series with the output node. The current sensor performs sensing during a first time window that occurs at regular intervals and the modulator avoids any transition in switching voltage at the first output node during the first time window. Embodiments also describe a sensing circuit for sensing a differential voltage with a common-mode variation which has a first sensing portion implemented to provide a floating voltage domain and a second sensing portion implemented to provide a static voltage domain. At least one switched capacitor provides a boundary between the voltage domains and is switched to transfer charge between the voltage domains.

Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

The invention provides an incremental analog-to-digital converter based on passive noise shaping and a signal processing method, which can be applied to the technical field of quantization. The incremental analog-to-digital converter comprises: an input integrating circuit configured to generate a (j-1) th low-order integrated voltage according to an input signal from a signal input end; generating a kth high-order integral voltage according to an input signal; the passive amplification circuit is configured to obtain a kth gain voltage according to the kth high-order integral voltage based on a predetermined amplification coefficient; the passive noise shaping circuit is configured to perform passive integration on the kth high-order integration voltage to obtain kth passive integration voltage, and perform passive gain on the kth passive integration voltage by using the kth gain voltage to obtain kth high-order gain voltage; a quantization circuit configured to quantize the M1 low-order integral voltages in M1 periods, respectively, to generate M1 coarse quantization values; m2 high-order gain voltages are quantized in M2 periods respectively, and M2 fine quantized values are generated.

A delta sigma modulator includes a comparator circuit with an output that provides a digital signal which is indicative of a voltage of an a signal received at its input terminal. The modulator includes a continuous-time path from the modular input terminal to an input terminal of a comparator of the comparator circuit. The modulator includes a first feedback loop connected to a first integrating node of the path that provides a first comparator circuit output controlled feedback current and a second a second feedback loop that provides a second comparator circuit output controlled feedback current to a second integrating node of the path that is connected to the input terminal of the comparator and connected to a capacitor.

The application provides a pulse density modulation interface implementation method and device of an analog-to-digital converter, electronic equipment and a storage medium. The method comprises the following steps: designing a circuit architecture of an analog-to-digital converter, and setting working variable parameters for components in the circuit architecture; determining a transfer function of an output signal and a transfer function of noise based on the working variable parameters; in the case that an oversampling rate (OSR) is a first set value, a filter order is a second set value, and a quantization bit number is a third set value, calculating an optimal solution of the transfer function of the noise; determining a value corresponding to the working variable parameters of the components according to the optimal solution; and selecting corresponding components for the circuit architecture based on the value, and generating a pulse density modulation interface of an analog-to-digital converter. The application can accurately design a PDM interface, and improves the signal processing performance of the interface.

The invention relates to an electronic circuit and a method for suppressing offset variations in a buffer.

Disclosed in the present invention is a floating inverter amplifier based on capacitor stacking, which boosts a power supply of the floating inverter amplifier to 2 times VDD by means of the capacitor stacking; under such condition, a transistor in the inverter may be better turned on, and a cascode structure can be applied to an inverting amplifier operating at a low power supply voltage. Furthermore, an ADC system employing the floating inverter amplifier of the present invention can process an input signal with a common-mode voltage of VDD and an amplitude up to 2 times VDD, which effectively addresses a problem of a reduced input signal amplitude under an ultra-low voltage, thereby increasing a signal-to-noise ratio of the system.

A delta-sigma modulator includes a comparator circuit having an output that provides a digital signal indicative of a voltage of a signal received at an input of the comparator circuit. The modulator includes a continuous-time path from a modular input to an input of a comparator of the comparator circuit. The modulator includes a first feedback loop connected to a first integrating node of the path and providing a first feedback current controlled by the comparator circuit output and a second second feedback loop providing a second feedback current controlled by the comparator circuit output to a second integrating node of the path, the second integrating node connected to the input of the comparator and to a capacitor.

The application provides a self-calibration circuit and method of a dynamic blood glucose monitoring chip. It relates to the field of dynamic blood glucose monitoring, and solves the problem of error caused by the input offset of the operational amplifier which cannot be calibrated. The circuit comprises a digital-to-analog converter which transmits a first voltage value to the positive input end of a first operational amplifier and transmits a second voltage value to the positive input end of a second operational amplifier; the output end of the first operational amplifier is connected to the counter electrode of a sensor; the reference electrode of the sensor is connected to the negative input end of the first operational amplifier, and the working electrode of the sensor is connected to the negative input end of the second operational amplifier; the output end of the second operational amplifier is transmitted to a first analog-to-digital converter, and the second end of the first analog-to-digital converter is accessed through a cross resistance. The application can calibrate the error caused by the input offset of the operational amplifier, the error caused by the drain current of all MOS tubes on the signal link, and the resistance value of the pre-operational amplifier circuit.

Analog front-end (AFE) system with an anti-aliasing filter circuit including a filter bypass switch configured to provide charge injection and / or clock pass-through independent of an input signal, wherein the AFE system comprises: at least one sampling capacitor of an analog-to-digital converter (ADC) circuit configured to sample an output of the anti-aliasing filter circuit; an amplification or buffer circuit with an input for receiving the input signal; and the anti-aliasing filter circuit coupled to an output of the amplification or buffer circuit, wherein the filter circuit comprises the following: a filter resistor; a filter capacitor coupled to one terminal of the filter resistor; and the filter bypass switch, which is connected in a bootstrapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage, wherein the filter bypass switch is connected in parallel to the filter resistor, wherein the filter bypass switch has an ON state and an OFF state, wherein, when in the ON state, the filter bypass switch is configured to bypass the filter resistance, allowing the amplification or buffer circuit to drive the at least one sampling capacitor through the filter bypass switch; and wherein, when in the OFF state, the filter bypass switch is designed to cause the amplification or buffer circuit to drive the at least one sampling capacitor through the filter resistor.

A processing apparatus includes: a distribution unit that divides an input signal into input signal blocks, and distributes, in dividing order, the divided input signal blocks to delta-sigma modulation circuits; a parallel circuit unit including the delta-sigma modulation circuits that perform delta-sigma modulation on the input signal blocks and output output signal blocks; and a coupling unit that couples the output signal blocks outputted from the parallel circuit unit, thereby to generate an output signal such that a first output signal block reflects a result obtained from a first delta-sigma modulation circuit, which performs delta-sigma modulation on a first input signal block corresponding to the first output signal block, performing delta-sigma modulation on the first input signal block, and a state of a second delta-sigma modulation circuit that performs delta-sigma modulation on a second input signal block located immediately before or after the first input signal block.

An example apparatus includes: a first switch having a first terminal and a second terminal; analog-to-digital converter (ADC) circuitry having an input and an output, the input of the ADC circuitry coupled to the first terminal of the first switch; digital-to-analog converter (DAC) circuitry having an input and an output, the input of the DAC circuitry coupled to the output of the ADC circuitry; combination circuitry having a first input, a second input, and an output, the first input of the combination circuitry coupled to the second terminal of the first switch, the second input of the combination circuitry coupled to the output of the DAC circuitry; amplifier circuitry having an input and an output, the input of the amplifier circuitry coupled to the output of the combination circuitry; and a second switch having a terminal coupled to the output of the amplifier circuitry.

A Delta-sigma (delta-sigma) device comprises a transducer (2) and a delta-sigma modulator (3), where the transducer (2) comprises: a sensing stage (100) for detecting a property of an environment (106) and an interface stage (101), where the sensing stage (100) is configured to detect the property of the environment (106); and the delta-sigma modulator (3) comprises: an input stage, a feed-forward low-pass filtering stage (102), an analog-to-digital encoder (104), an unfiltered in-modulator feedback path and a low-pass filtered in-modulator feedback path; wherein the input stage is connected to the interface stage (101) and comprises two subtraction stages (113, 114) of the input stage for receiving an unfiltered in-modulator feedback signal (109) and a low-pass filtered in-modulator feedback signal (110) and subtracting the unfiltered in-modulator feedback signal (109) and the low-pass filtered in-modulator feedback signal (110) from the sum of the one or more input converted signals (108), to obtain a delta error signal (111); the analog-to-digital encoder (104) converts the filtered delta error signal into a digital output signal dout (t) (112); the feedback path in the unfiltered modulator converts the dout (t) (112) into a feedback signal (109) in the unfiltered modulator; the low-pass filtering modulator internal feedback path converts the dout (t) (112) into a low-pass filtering modulator internal feedback signal (110).

The disclosure relates to a circuitry and a method for extracting a digitized DC voltage value representing a magnitude of a discrete-time signal received from a discrete-time system. A first full-wave rectifier performs a full-wave rectification of the discrete-time signal to obtain a full-wave rectified signal, and an oversampling analog-to-digital converter digitizes the full-wave rectified signal to obtain a bitstream. The oversampling ADC comprises a second-order or higher order delta-sigma modulator and a filter. The filter is configured to filter the bitstream to extract the digitized DC voltage value.

Circuits and methods are disclosed for minimizing charge loss due to negative transient voltages at summing terminals (116, 120) of an analog-to-digital converter (ADC) (104). The ADC is coupled to a multi-bit digital-to-analog converter (DAC) (112A) at the summing terminals (116, 120). The ADC and the DAC include PMOS transistors and NMOS transistors whose timing is controlled to reduce charge loss. The PMOS transistors are turned on before the NMOS transistors. Also, the PMOS transistors of the ADC are turned on at a slower rate than the PMOS transistors of the DAC.

The invention relates to a hybrid oversampling analog-to-digital converter. A circuit (100) includes a switched capacitor amplifier circuit (102), a multi-bit quantizer circuit (104), an accumulator circuit (106), a loop result register (110), and a result combining circuit (112). The switched capacitor amplifier circuit (102) has an output. The multi-bit quantizer circuit (104) has an input and an output, the input coupled to the output of the switched capacitor amplifier circuit (102). The accumulator circuit (106) has an input and an output, the input coupled to the output of the multi-bit quantizer circuit (104). The loop result register (110) has an input and an output, the input coupled to the output of the multi-bit quantizer (104). The result combining circuit (112) has a first input coupled to the output of the accumulator circuit (106) and a second input coupled to the output of the loop result register (110).

This invention discloses a conversion circuit and an electronic chip. The conversion circuit includes, in sequence, an input coarse quantization module, a discrete domain amplification module, a continuous domain amplification module, and an output fine quantization module. The discrete domain amplification module pre-amplifies the conversion result of the input coarse quantization module to suppress the gain noise of the continuous domain amplification module. The conversion circuit is a capacitor-to-digital converter or an analog-to-digital converter. This invention achieves the fusion of discrete and continuous domains in analog-to-digital or capacitor-to-digital converters, giving the entire circuit the advantages of both high energy efficiency and high precision.

An overload detector circuit comprises a first logic circuit and a second logic circuit. The first logic circuit receives a bitstream from a sigma-delta modulator (SDM) of a receiver channel. This circuit compares a current bit of the bitstream with a previous bit and outputs an indication of a match. The second logic circuit tracks a number of consecutive matches in the bitstream and outputs an indication of a first overload state when the number of consecutive matches meets a first threshold criterion.

A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a sigma-delta modulator having a modulator input and a modulator output, first system-level chopping switches located at the modulator input, an auxiliary path comprising an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the sigma-delta modulator, second system-level chopping switches located downstream of the sigma-delta modulator and the auxiliary path, and a signal combiner configured to combine a modulator output signal generated by the sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.

An ADC circuit is provided. The ADC circuit includes a continuous-time ΔΣ ADC including an integration circuit configured to integrate a difference signal, a switching circuit configured to perform switching to supply an analog signal supplied to an input terminal to the ΔΣ ADC in a first period and to supply a voltage signal corresponding to a voltage output from the integration circuit at an end of the first period in a second period after the first period, and a holding circuit configured to hold the voltage signal corresponding to the voltage output from the integration circuit at the end of the first period and provide the voltage signal to the ΔΣ ADC via the switching circuit in the second period. The ΔΣ ADC is configured to be able to perform gain adjustment for an analog signal input to the ΔΣ ADC.

The invention provides a digital filter, a parameter configuration method and a chip. The digital filter comprises a multi-order sinc filter and a multi-order comb filter which are connected, the order N and the down-sampling rate of the multi-order sinc filter, the order b of the multi-order comb filter and a plurality of corresponding weight coefficients are pre-determined and configured according to the frequency to be filtered; the multi-order sinc filter receives the coded signal, samples the coded signal for N times according to a preset down-sampling rate, and calculates an average value of each sampling result to obtain an average value signal; the multi-order comb filter performs weighting operation on the mean value signal through the first signal processing unit, the second signal processing unit and the corresponding weight coefficients, and sums the mean value signal through the accumulator to obtain an output signal; the output signal is a coded signal after the signal with the frequency to be filtered is filtered. The parameters of the digital filter are flexibly configured based on different application scenes.

Device for operating a passive infrared (PIR) detector with a first connection (IN) and a second connection (IP), the device comprising: - an electrical circuit arrangement (R G ), wherein the electrical circuit arrangement (R G ) forms a leakage resistance between the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR) to discharge the first terminal (IN) and the second terminal (IP) of the passive infrared detector (PIR); wherein the electrical circuit arrangement (R G ) includes a switch-capacitor circuit with transfer gates and storage capacities; and the device is set up for this purpose: - the transfer gates of the electrical circuit arrangement (R G) to switch alternately with a first clock (φ1) and a second clock (Φ2), and to advance a charge quantity by one node with each half-clock using the storage capacities, whereby the first clock (φ1) and the second clock (Φ2) do not overlap and, apart from the non-overlap, the first clock (φ1) is the inverse of the second clock (Φ2); and - to switch off the first clock (φ1) and the second clock (Φ2) during a measurement phase, so that the device is in a measurement state and the charge flow through the electrical circuit arrangement (R G ) is prevented.

A delta sigma modulator includes a comparator circuit with an output that provides a digital signal which is indicative of a voltage of an a signal received at its input terminal. The modulator includes a continuous-time path from the modular input terminal to an input terminal of a comparator of the comparator circuit. The modulator includes a first feedback loop connected to a first integrating node of the path that provides a first comparator circuit output controlled feedback current and a second a second feedback loop that provides a second comparator circuit output controlled feedback current to a second integrating node of the path that is connected to the input terminal of the comparator and connected to a capacitor.

To provide a battery voltage monitoring device that can be incorporated into a battery system.SOLUTION: A battery voltage monitoring device includes a clock generation circuit, and a switch circuit that includes a first N-type transistor (hereinafter referred to as Tr), a second N-type Tr, a first P-type Tr, and a second P-type Tr, in which a source (hereinafter referred to as S) and a back gate are connected to each other, and in which the drain (hereinafter referred to as D) of one of the first N-type Tr and the first P-type Tr is connected to the other S, one S is connected to a signal input portion, and the other D is connected to the signal output portion, and one D of the second N-type Tr and the second P-type Tr is connected to the other S, one S is connected to the signal input portion, and the other D is connected to the signal output portion, a first generation circuit that generates a first control signal for the first P-type Tr and a second control signal for the second P-type Tr, and a second generation circuit that generates a third control signal for the first N-type Tr and a fourth control signal for the second N-type Tr.SELECTED DRAWING: Figure 2

An analog-to-digital conversion (ADC) circuit for converting an analog signal supplied to an input terminal into a digital signal comprises a continuous-time delta-sigma ADC, which includes an integration circuit configured to integrate a differential signal; and a switching circuit configured to supply the analog signal supplied to the input terminal to the continuous-time delta-sigma ADC during a first period, and to supply a voltage signal corresponding to the voltage output of the integration circuit at the end of the first period to the continuous-time delta-sigma ADC during a second period after the first period.

High speed data weighted average (DWA) to binary conversion circuits are disclosed. A latch circuit latches a first data weighted average (DWA) data word in sequence and then latches a second DWA data word. A first detector circuit identifies a first bit position in the first DWA data associated with an end of a first string of logical one bits in the first DWA data word. A second detector circuit identifies a second bit position in the second DWA data word associated with an end of a second string of logical one bits in the second DWA data word. The DWA to binary conversion circuit converts the second DWA data word to a binary word by using the first bit position and the second bit position to identify a number of logical one bits present in the second DWA data word. A binary value equal to the identified number is outputted for the binary word.