523results about "Analogue conversion" patented technology

The invention relates to an integrator circuit for eliminating thermal noise and a Delta-sigma modulator, and belongs to the technical field of electronic signal processing, the modulator comprises at least two stages of integrators, a quantizer, a feedback DAC and an adder; the integrator comprises an integrator circuit, and the integrator circuit comprises a sampling module for sampling an input signal source; the double-path multi-phase clock control pre-amplification auxiliary storage circuit module alternately samples and stores thermal noise voltage and offset voltage; the integral amplifier is used for amplifying a signal output by the double-path multi-phase clock control pre-amplification auxiliary storage circuit module; and the integrating capacitor is connected between the integrating amplifier and the two-way multi-phase clock control pre-amplification auxiliary storage circuit module, and feeds back the signal after integration processing to the two-way multi-phase clock control pre-amplification auxiliary storage circuit module to realize signal modulation and noise shaping. The thermal noise introduced in the sampling process is effectively reduced, and the area of the whole chip is reduced while the signal-to-noise ratio is improved.

A digital microphone includes at least one integrator; a state detection and parameter control component directly coupled to an output of the integrator; and a signal processing component coupled to an output of the state detection and parameter control component, wherein a parameter of the signal processing component includes a first value in a first operational mode and a second value in a second operational mode different from the first operational mode.

A nested Δ-Σ analog-to-digital conversion system and method, compromising: an analog filter, an analog comparator, a first feedback digital-to-analog converter (DAC), a second feedback DAC placed in front of the first feedback DAC, and a digital filter and an MSB quantizer placed at the output of the analog comparator; wherein the input of the first feedback DAC is connected to the output of the analog comparator; the analog filter, the analog comparator, and the first feedback DAC form an internal analog Δ-Σ loop; the input of the second feedback DAC is connected to the output of the MSB quantizer; the output of the second feedback DAC is connected to the output of the first feedback DAC and to the input of the analog filter; and the second feedback DAC, the internal analog Δ-Σ loop, the digital filter, and the MSB quantizer form an external hybrid Δ-Σ loop.

A calibration circuit for correcting timing errors introduced by a DAC in a signal path of an ADC, the calibration circuit comprising: an input subtraction module configured to subtract an estimated error from an output of the ADC and provide a corrected output; a filter module configured to approximate an error transfer function corresponding to the DAC timing errors; a correlation module configured to correlate the corrected output with an output from the filter module to extract an error term; an integrator module configured to integrate the error term to provide an updated error coefficient; and a correction module configured to correlate the updated error coefficient with the output from the filter module to provide the estimated error to the input subtraction module.

The invention relates to the technical field of amplifiers, and discloses an analog-to-digital converter combination instrument amplifier which comprises a first-stage amplifier, the first-stage amplifier is in signal connection with a second-stage amplifier, the second-stage amplifier is in signal connection with a front-end low-pass filter (LPF), the front-end low-pass filter (LPF) is in signal connection with an analog-to-digital converter (ADC), and the analog-to-digital converter (ADC) is in signal connection with the analog-to-digital converter. And an unbalanced input-to-balanced differential circuit output module is arranged between the second-stage amplifier signal and a front-end low-pass filter (LPF). From the perspective of signal processing and conversion, a precise signal transition bridge is constructed by adding an unbalanced input-to-balanced differential circuit output module, unbalanced signals output by a second-stage amplifier are converted into double-end balanced differential signals, common-mode noise interference is effectively resisted through a differential transmission mode, the signal purity is guaranteed, and the signal quality is improved. The front-end low-pass filter and the analog-to-digital converter are adaptive to differential signals, so that the signal transmission is stable and anti-interference, and the analog-to-digital conversion is more accurate.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

Certain aspects of the present disclosure provide techniques and apparatus for digital-to-analog conversion. An example apparatus generally includes a digital-to-analog converter (DAC), an incremental analog-to-digital converter (IADC) having a first input coupled to a first output of the DAC, and a controller coupled to the DAC and the IADC. The controller is configured to determine a direct current (DC) offset associated with the DAC using the IADC and control a mission-mode digital input signal of the DAC based on the DC offset.

The invention discloses a capacitor mismatch error shaping circuit and method suitable for a multi-bit quantization Sigma-Delta ADC, and belongs to the technical field of integrated circuits, and the capacitor mismatch error shaping circuit comprises a data weight averaging module which is used for adopting a data weight averaging technology for high-bit quantization code words, and correcting the high-bit quantization code words according to the data weight averaging technology; averaging the mismatch error of the capacitor corresponding to the high-order quantization code word to obtain an averaged high-order capacitor; and the mismatch error shaping module is used for taking the averaged high-order capacitance as a reference, adopting a mismatch error shaping technology, keeping low-order feedback of the current low-order quantization code word of the lower polar plate of the capacitive digital-to-analog converter during Sigma-Delta ADC sampling, and realizing subtraction operation between two adjacent low-order quantization code words. According to the invention, the error caused by the mismatch of the CDAC capacitor fed back by the multi-bit quantization Sigma-Delta ADC can be effectively suppressed, the linearity of the system is improved, and the circuit overhead is remarkably reduced.

This application relates to sensing of signals with a common-mode variation. Embodiments describe a switching driver circuit with a modulator configured to control modulation of an output node between different switching voltages and a current sensor configured to sense a voltage drop across a sense resistor connected in series with the output node. The current sensor performs sensing during a first time window that occurs at regular intervals and the modulator avoids any transition in switching voltage at the first output node during the first time window. Embodiments also describe a sensing circuit for sensing a differential voltage with a common-mode variation which has a first sensing portion implemented to provide a floating voltage domain and a second sensing portion implemented to provide a static voltage domain. At least one switched capacitor provides a boundary between the voltage domains and is switched to transfer charge between the voltage domains.

Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

Processing circuitry comprising an analog-to-digital converter configured to perform the techniques of this disclosure. The analog-to-digital converter may obtain, based on electrical interactions with a resolver sensor, a noisy modulated digital cosine signal (NMDCS) and a noisy modulated digital sine signal (NMDSS). The processing circuitry includes a filter configured to process the NMDCS and the NMDSS to output a filtered NMDCS and a filtered NMDSS, and a rectifier configured to process the filtered NMDCS and the filtered NMDSS to output a rectified NMDCS and a rectified NMDSS. The processing circuitry includes a digital signal processor that executes a first trained machine learning model to process the rectified NMDCS and the rectified NMDSS to obtain a demodulated DCS and a demodulated DSS, and compute, based on the demodulated DCS and the demodulated DSS, an approximate angle of the rotating element.

The invention discloses an aliasing suppression strategy based on oversampling filtering. The aliasing suppression strategy comprises a mixed time frequency analysis module, an oversampling processing module, a delta-sigma modulator module, an RC filter module and a Sinc filter module. Wherein the mixed time-frequency analysis is used for performing frequency band analysis on a signal and judging whether an aliasing phenomenon exists or not according to a result; the oversampling processing is used for carrying out high-resolution digital sampling on the signal so as to fully capture the periodic change of the signal; the delta-sigma modulator is used for converting the oversampled signal into a high-speed and low-resolution sequence; the RC filter is used for converting a high-speed 1-bit sequence into a signal in an analog form, removing high-frequency noise and smoothing the signal; the Sinc filter further improves the frequency characteristic of the signal and inhibits residual high-frequency noise, a cleaner and smoother analog signal is obtained, and the analog signal is more suitable for subsequent signal processing and analysis. The method has higher signal reconstruction precision, stronger anti-aliasing and anti-noise capabilities, and greater flexibility and adjustability, and is suitable for various application scenes.

The invention discloses a piecewise linear quantization mixed structure analog-to-digital converter with a noise shaping function, and belongs to the field of analog-to-digital converters, the analog-to-digital converter comprises an input control circuit, a nonlinear quantization circuit, a noise shaping modulation circuit, an output control circuit and a digital decimation filter circuit, the control circuit samples an input signal; the non-linear quantization circuit determines a non-linear section where an input signal is located and provides reference voltage for the noise shaping modulation circuit; the noise shaping modulation circuit is used for performing noise shaping and fine quantization on an input signal; the output control circuit combines the two parts of quantization output and generates a high-speed low bit code stream; the digital decimation filter circuit receives a high-speed code stream and generates a high-precision digital code through decimation filtering; according to the technology provided by the invention, suitable nonlinear quantization characteristics are provided according to different signal characteristics, and meanwhile, higher quantization precision and a wider dynamic range can be realized.

The invention provides an incremental analog-to-digital converter based on passive noise shaping and a signal processing method, which can be applied to the technical field of quantization. The incremental analog-to-digital converter comprises: an input integrating circuit configured to generate a (j-1) th low-order integrated voltage according to an input signal from a signal input end; generating a kth high-order integral voltage according to an input signal; the passive amplification circuit is configured to obtain a kth gain voltage according to the kth high-order integral voltage based on a predetermined amplification coefficient; the passive noise shaping circuit is configured to perform passive integration on the kth high-order integration voltage to obtain kth passive integration voltage, and perform passive gain on the kth passive integration voltage by using the kth gain voltage to obtain kth high-order gain voltage; a quantization circuit configured to quantize the M1 low-order integral voltages in M1 periods, respectively, to generate M1 coarse quantization values; m2 high-order gain voltages are quantized in M2 periods respectively, and M2 fine quantized values are generated.

A digital-to-time converter (DTC) of a fractional-n PLL contains a delay generator and a current-drawing block. The current drawn by the delay generator from the power supply contains: (A) a fixed component having a first current magnitude regardless of magnitude of a second code specifying the desired delay; and (B) a variable component having a magnitude determined only by magnitude of the second code. The current-drawing block draws correction-current from the power supply, whose magnitude is determined only by a complement of the second code.

A delta sigma modulator includes a comparator circuit with an output that provides a digital signal which is indicative of a voltage of an a signal received at its input terminal. The modulator includes a continuous-time path from the modular input terminal to an input terminal of a comparator of the comparator circuit. The modulator includes a first feedback loop connected to a first integrating node of the path that provides a first comparator circuit output controlled feedback current and a second a second feedback loop that provides a second comparator circuit output controlled feedback current to a second integrating node of the path that is connected to the input terminal of the comparator and connected to a capacitor.

The application provides a pulse density modulation interface implementation method and device of an analog-to-digital converter, electronic equipment and a storage medium. The method comprises the following steps: designing a circuit architecture of an analog-to-digital converter, and setting working variable parameters for components in the circuit architecture; determining a transfer function of an output signal and a transfer function of noise based on the working variable parameters; in the case that an oversampling rate (OSR) is a first set value, a filter order is a second set value, and a quantization bit number is a third set value, calculating an optimal solution of the transfer function of the noise; determining a value corresponding to the working variable parameters of the components according to the optimal solution; and selecting corresponding components for the circuit architecture based on the value, and generating a pulse density modulation interface of an analog-to-digital converter. The application can accurately design a PDM interface, and improves the signal processing performance of the interface.

The invention relates to an electronic circuit and a method for suppressing offset variations in a buffer.

An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multibit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

Disclosed in the present invention is a floating inverter amplifier based on capacitor stacking, which boosts a power supply of the floating inverter amplifier to 2 times VDD by means of the capacitor stacking; under such condition, a transistor in the inverter may be better turned on, and a cascode structure can be applied to an inverting amplifier operating at a low power supply voltage. Furthermore, an ADC system employing the floating inverter amplifier of the present invention can process an input signal with a common-mode voltage of VDD and an amplitude up to 2 times VDD, which effectively addresses a problem of a reduced input signal amplitude under an ultra-low voltage, thereby increasing a signal-to-noise ratio of the system.

This invention provides an analog-to-digital converter (ADC) comprising: a switched-capacitor array for operating in a first ADC mode or a second ADC mode based on a received timing signal; a first logic unit for outputting a first timing signal to control the switched-capacitor array to operate in the first ADC mode; a second logic unit for outputting a second timing signal to control the switched-capacitor array to operate in the second ADC mode; a control unit for outputting a control signal to control the first logic unit to output the first timing signal and to control the second logic unit to output the second timing signal; and a comparator, the output of which is electrically connected to the first and second logic units to feed back the output voltage of the switched-capacitor array to the control unit through the first and second logic units. This satisfies the requirements for high-precision and fast sampling of signals at different time periods, and reduces the area of ​​the ADC by reusing the switched-capacitor array and the comparator.

In an embodiment, an apparatus (112) includes: a transmitting data path configured to transmit an outgoing data packet; and a receiving data path configured to receive an incoming data packet; a controller (212) configured to determine timing information of the incoming data packet; and dithering circuitry (116) configured to dither a reference signal according to the timing information to vary a frequency of the signal over time to generate a dithered recovered signal.

A delta-sigma modulator includes a comparator circuit having an output that provides a digital signal indicative of a voltage of a signal received at an input of the comparator circuit. The modulator includes a continuous-time path from a modular input to an input of a comparator of the comparator circuit. The modulator includes a first feedback loop connected to a first integrating node of the path and providing a first feedback current controlled by the comparator circuit output and a second second feedback loop providing a second feedback current controlled by the comparator circuit output to a second integrating node of the path, the second integrating node connected to the input of the comparator and to a capacitor.

A sigma-delta analog-to-digital converter comprises first and second injection branches (101, 102) and first and second feedback branches (121, 122) connected to an integration node (120). The first and second injection branches are configured to provide a charge injection from different input quantities selected from a differential voltage signal, a capacitance dependent signal and a current dependent signal. The first and second feedback branches are configured to provide a feedback charge injection of a fixed voltage signal or a differential voltage signal.

The application provides a self-calibration circuit and method of a dynamic blood glucose monitoring chip. It relates to the field of dynamic blood glucose monitoring, and solves the problem of error caused by the input offset of the operational amplifier which cannot be calibrated. The circuit comprises a digital-to-analog converter which transmits a first voltage value to the positive input end of a first operational amplifier and transmits a second voltage value to the positive input end of a second operational amplifier; the output end of the first operational amplifier is connected to the counter electrode of a sensor; the reference electrode of the sensor is connected to the negative input end of the first operational amplifier, and the working electrode of the sensor is connected to the negative input end of the second operational amplifier; the output end of the second operational amplifier is transmitted to a first analog-to-digital converter, and the second end of the first analog-to-digital converter is accessed through a cross resistance. The application can calibrate the error caused by the input offset of the operational amplifier, the error caused by the drain current of all MOS tubes on the signal link, and the resistance value of the pre-operational amplifier circuit.

Method for calibrating a multi-bit Delta-Sigma modulator comprising at least one main multi-bit digital-analogue converter in the return loop for generating a return signal subtracted from the input of the modulator, the main converter comprising a plurality of elementary source cells at least some of which, referred to as active cells, are associated with the various input bits of the converter for generating the return signal, the output level of these active source cells being adjustable under the action of a matching signal, the matching signal coming from a calibration circuit receiving an output signal from the modulator at its input, this calibration circuit comprising a generator of a calibration sequence.

Analog front-end (AFE) system with an anti-aliasing filter circuit including a filter bypass switch configured to provide charge injection and / or clock pass-through independent of an input signal, wherein the AFE system comprises: at least one sampling capacitor of an analog-to-digital converter (ADC) circuit configured to sample an output of the anti-aliasing filter circuit; an amplification or buffer circuit with an input for receiving the input signal; and the anti-aliasing filter circuit coupled to an output of the amplification or buffer circuit, wherein the filter circuit comprises the following: a filter resistor; a filter capacitor coupled to one terminal of the filter resistor; and the filter bypass switch, which is connected in a bootstrapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage, wherein the filter bypass switch is connected in parallel to the filter resistor, wherein the filter bypass switch has an ON state and an OFF state, wherein, when in the ON state, the filter bypass switch is configured to bypass the filter resistance, allowing the amplification or buffer circuit to drive the at least one sampling capacitor through the filter bypass switch; and wherein, when in the OFF state, the filter bypass switch is designed to cause the amplification or buffer circuit to drive the at least one sampling capacitor through the filter resistor.

A processing apparatus includes: a distribution unit that divides an input signal into input signal blocks, and distributes, in dividing order, the divided input signal blocks to delta-sigma modulation circuits; a parallel circuit unit including the delta-sigma modulation circuits that perform delta-sigma modulation on the input signal blocks and output output signal blocks; and a coupling unit that couples the output signal blocks outputted from the parallel circuit unit, thereby to generate an output signal such that a first output signal block reflects a result obtained from a first delta-sigma modulation circuit, which performs delta-sigma modulation on a first input signal block corresponding to the first output signal block, performing delta-sigma modulation on the first input signal block, and a state of a second delta-sigma modulation circuit that performs delta-sigma modulation on a second input signal block located immediately before or after the first input signal block.

An example apparatus includes: a first switch having a first terminal and a second terminal; analog-to-digital converter (ADC) circuitry having an input and an output, the input of the ADC circuitry coupled to the first terminal of the first switch; digital-to-analog converter (DAC) circuitry having an input and an output, the input of the DAC circuitry coupled to the output of the ADC circuitry; combination circuitry having a first input, a second input, and an output, the first input of the combination circuitry coupled to the second terminal of the first switch, the second input of the combination circuitry coupled to the output of the DAC circuitry; amplifier circuitry having an input and an output, the input of the amplifier circuitry coupled to the output of the combination circuitry; and a second switch having a terminal coupled to the output of the amplifier circuitry.