1584results about "Analogue/digital conversion" patented technology

A logarithmic amplifier includes programmable gain amplifiers each having a different gain, wherein an input of each of the programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and a summing circuit having inputs coupled to a corresponding output of each of the programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit generates a logarithmic transfer function having piecewise linear segments.

A method of operating a time-interleaved analog-to-digital converter (TIADC). The TIADC converts an input signal to generate a digital output signal and includes multiple asynchronous sub-ADCs. The asynchronous sub-ADCs each convert the input signal at a different time point to generate a digital output code, and each of the asynchronous sub-ADCs generates a completion signal upon completion of an analog-to-digital conversion operation. The method includes the following steps: generating an indication signal according to the completion signals, wherein the indication signal indicates multiple candidate sub-ADCs; selecting one of the candidate sub-ADCs as a target sub-ADC according to the indication signal; and correcting the digital output code of the target sub-ADC to generate the digital output signal.

Pixel circuits of a solid-state imaging device are arranged in pixel columns, wherein, for each pixel column, signal outputs of the pixel circuits are connected to a data signal line. The solid-state imaging device further includes comparator circuits, wherein each comparator circuit generates an active comparator signal in response to a voltage difference between a first comparator input and a second comparator input. Each first comparator input is connected to one of the data signal lines. A ramp generator circuit includes at least one resistor network and buffer circuits. The ramp generator circuit generates a voltage ramp signal based on voltages at voltage tap nodes of the at least one resistor network. Each buffer circuit passes a buffered voltage ramp signal to the second comparator input of at least one of the comparator circuits.

An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.

A current comparator includes: a first capacitor having a first end coupled to a first input signal; a second capacitor having a first end coupled to a second input signal; a first transistor having a control electrode coupled to the second end of the first capacitor; and a third transistor having a control electrode coupled to the second end of the second capacitor. The first current electrodes of the first and second transistors are coupled, and the second current electrodes of the first and second transistors are coupled to the first and second circuit nodes, respectively. A single-ended cascode amplifier has an input coupled to the second circuit node via a third capacitor. A set of auto-zero switches selectively shorts the control electrode of the first transistor and the second current electrode in response to an auto-zero control signal, and selectively shorts the control electrode of the second transistor and the second current electrode.

Certain aspects of the present disclosure generally relate to a digital-to-analog converter (DAC) circuit implemented with a dynamic stacked transistor architecture. The DAC circuit generally includes a first current-steering transistor and a second current-steering transistor. The DAC circuit may also include: a first stacked transistor coupled between the first current-steering transistor and a first output of the DAC circuit; a first switch coupled between a gate of the first stacked transistor and a bias voltage node; a second switch coupled between the gate of the first stacked transistor and a voltage rail; a second stacked transistor coupled between the second current-steering transistor and a second output of the DAC circuit; a third switch coupled between a gate of the second stacked transistor and the bias voltage node; and a fourth switch coupled between the gate of the second stacked transistor and the voltage rail.

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

A sigma-delta analog-to-digital converter is provided that includes an initial continuous-time integration stage having a variable input resistor and an integration capacitor. A switched-capacitor circuit charges and discharges a replica capacitor to a reference voltage to generate a bias current. A SAR-based tuning circuit includes a variable tuning resistor that generates a tuning voltage while conducting a mirrored version of the bias current. A resistance of the variable input resistor is adjusted responsive to a tuning code from the SAR-based tuning circuit.

A multi-channel analog-digital converter (ADC) subsystem for test device such as a spectrum analyzer may include multiple multi-channel ADCs to receive down-converted signals and convert the received signals to digital output signals, a field programmable gate array (FPGA) to select one or more ADCs based on a frequency, a bandwidth, and / or a signal type of each received signal and a characteristic of each ADC, and an ADC sample clock to provide a clock signal to the selected ADCs. Characteristics of the ADCs may include a resolution, a signal-to-noise-and-distortion ratio (SINAD), an effective number of bits (ENOB), a signal-to-noise ratio (SNR), a total harmonic distortion (THD), a total harmonic distortion plus noise (THD+N), and / or a spurious free dynamic range (SFDR).

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes an ADC with a continuous time integrator. The continuous time integrator includes an amplifier having an amplifier input and an amplifier output, a capacitor coupled between the amplifier input and the amplifier output, and a resistor. The resistor provides a first current for an integration in response to an analog input. The ADC also includes a DAC configured to generate a second current at an DAC output based on a digital output of the ADC and includes a switch circuit with a first switch circuit terminal coupled with the DAC output and a second switch circuit terminal coupled with the amplifier input. The switch circuit is configured to couple the DAC output with the amplifier input for a summation of the second current with the first current for the integration based on an integration control signal.

The invention discloses a high-speed and high-linearity margin amplifier and an analog-to-digital converter, belongs to the technical field of integrated circuits, and solves the technical problem that an existing source follower cannot meet high-speed and high-linearity indexes. The amplifier comprises a margin amplifier bias and output module, a phase inverter and a linear transconductance unit based on an AB-class super source follower structure, wherein the bias and output module, the linear transconductance unit and the phase inverter are connected in sequence. The linear transconductance unit can generate high-linearity transconductance, so that the linearity of the whole margin amplifier is improved, the symmetry of the positive output end and the negative output end of the margin amplifier under the condition of high-frequency or large-swing input can be ensured, and the high-speed and high-linearity index can be effectively met. In addition, a gain calibration module resistant to temperature and process changes is further introduced, and the influence caused by follow-up system environment temperature changes can be automatically compensated.

To provide a signal generating device and a signal generating method that can significantly increase an adjustable maximum phase difference between signals output from a plurality of transceivers.SOLUTION: A signal generating device includes a phase acquisition processing unit 31b for acquiring a voltage value measured by a phase detection unit while changing, from an initial value, the phase of a toggle pattern output from each transceiver, a phase difference calculation processing unit 31c for calculating an initial phase difference between a divided clock or external clock selected by a clock selection unit and an initial value of the phase of the toggle pattern based on the relationship between the voltage value acquired by the phase acquisition processing unit 31b and the amount of change from the initial value of the phase of the toggle pattern, and a phase movement processing unit 31d for moving the phase of the toggle pattern from the initial value by the initial phase difference such that the phase difference between the divided clock or external clock selected by the clock selection unit and the toggle pattern is within a predetermined range.SELECTED DRAWING: Figure 6

A controller for a multi-level power converter that utilizes a look-up-table (LUT) in combination with a fast flash analog-to-digital converter (ADC) circuit to implement a complex set of control states for the multi-level power converter. Since the set of control states can be pre-processed, a LUT is very well suited for such selecting such control states. This technique can be fast because the delay is only the LUT access time, rather than the propagation delay through a complex network of combinational logic. The fast flash ADC has been designed to achieve all the following: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages in a multi-level converter cell.

A ramp generation circuit includes a ramping voltage generator configured to generate a ramping voltage that changes depending on a first slope or a second slope, a blocking capacitor configured to transmit the ramping voltage to a transfer node, a signal output unit configured to amplify a voltage of the transfer node and to output a ramp output signal to an output node, and a ramp switch configured to selectively connect the transfer node to the output node.

The present invention provides a novel semiconductor device. The present invention uses a comparison unit for comparing two current values, a control unit, and a current output type digital-analog conversion unit to convert an analog signal into a digital signal. The control unit has the function of generating a sign bit indicating the magnitude relation between the two current values, the function of converting, by successive approximation, the difference between the two current values into the digital signal, and the function of outputting the sign bit and the digital signal.

A monotonic capacitor digital-to-analog converter (CDAC) is provided. The CDAC includes a converter array comprising a plurality of CDAC units, wherein each CDAC unit comprises a logic unit, a switch, and a capacitor, and wherein each logic unit comprises a first input, a second input, and a third input. The CDAC further includes a first set of control lines, and each of the first set of control lines is connected to the first inputs of the logic units of the CDAC units in a corresponding column of the converter array. The CDAC further includes a second set of control lines, and each of the second set of control lines is connected to the second inputs of the logic units of the CDAC units in a corresponding row of the converter array, but is disconnected from the second input of the logic unit of a CDAC unit in the corresponding row and the last column of the converter array. Each of the second set of control lines is further connected to the third inputs of the logic units of the CDAC units in a row of the converter array adjacent to the corresponding row.

A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND / OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.

The invention provides a single-ended input successive approximation analog-to-digital converter and an optical module chip. In a sampling stage, upper electrode plates of a plurality of first capacitors are connected with an input voltage Vin, part of lower electrode plates are connected with the input voltage Vin, and part of the lower electrode plates are connected with a reference voltage Vref; the upper electrode plates of the plurality of second capacitors are connected with a reference voltage Vref, part of the lower electrode plates are connected with an input voltage Vin, and part of the lower electrode plates are connected with the reference voltage Vref; in the pre-switching stage, an upper pole plate switch is switched off, and lower pole plate voltages of the multiple first capacitors and the multiple second capacitors are switched according to a preset mode, so that the upper pole plate voltages of the multiple first capacitors are all changed into a first preset voltage Vp, and the upper pole plate voltages of the multiple second capacitors are all changed into a second preset voltage Vn; in the comparison stage, the first preset voltage Vp and the second preset voltage Vn are input into the comparator for first-stage comparison. Through preset switching logic, single-ended analog-to-digital converter input can be converted into differential comparator input.

A comparator compares a differential voltage between a voltage to be converted as an analog input voltage and a comparative voltage generated by a D / A converting unit with a comparison reference voltage. A switching circuit selectively connects a capacitor, associated with the analog input voltage selected as the voltage to be converted, to an output terminal of an integrator. The integrator integrates the differential voltage in a state where an A / D converting section has performed conversion operation on a least significant bit. A comparison reference voltage generating unit uses, as the comparison reference voltage, a charge voltage for the capacitor associated with the analog input voltage selected as the voltage to be converted.

An analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) configured to change a signal level of a first node based on a first and second input analog signals, a second DAC configured to change a signal level of a second node based on one of the first input analog signal and the second input analog signal, a comparator configured to compare the signal level of the first node and the signal level of the second node, and a controller configured to generate a first digital value for the first DAC and a second digital value for the second DAC based on an output of the comparator during a first conversion phase corresponding to a first sampling phase, input the first digital value into the second DAC before a second sampling phase, and input the second digital value into the first DAC before the second sampling phase.

A capacitive digital-to-analog converter (CDAC) comprising a capacitive structure and a control logic circuit coupled to each other is provided. The control logic circuit comprises switch groups that each comprises first and second switch circuits. The first and second switch circuits each comprise first, second terminals, a first via and a control terminal. The first terminal is configured to receive a source voltage or a ground voltage through a first metal layer of the CDAC. The second terminal is configured to be coupled to the capacitive structure through the first via extending in a vertical direction. The control terminal is configured to receive one of a plurality of turn-on signals through a second metal layer of the CDAC. The capacitive structure is located at least in a third metal layer of the CDAC. The third metal layer is located above the first and second metal layers.

An integrated circuit (IC), comprising: a first gain stage configured to apply a first gain to a first signal to generate a first amplified signal; a first converter configured to convert the first signal to a first output signal; a first output pin for outputting the first output signal; gain update circuitry configured to: output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, subsequently output a first external gain control signal to a second output pin of the IC, wherein output of the first external gain control signal is delayed relative to output of the first internal gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first gain stage and the first output pin.

An apparatus for calibrating a digital filter to replicate a transfer function of a signal processing device comprising a detector with a first input to receive a first signal; a second input to receive a response signal of the signal processing device to the first signal; a signal modification block; a comparison block and a decimation block; wherein the comparison-block compares a phase and amplitude of the first signal after a correction has been applied by the signal modification block and decimation has been applied by the decimation block; and a feedback loop; wherein detector is configured to determine at least a feedback control signal at a first frequency and a second frequency, different to the first frequency and determine calibration information for programming of the transfer function of said digital filter.

The invention discloses a high-precision R-2R voltage type digital-to-analog converter based on a binary weighted code and a thermometer code, the digital-to-analog converter comprises a weighted resistance network, a thermometer decoder circuit and an operational amplifier module with a self-calibration function, the output of the weighted resistance network is connected with the operational amplifier module with the self-calibration function, and the output of the thermometer decoder circuit is connected with the operational amplifier module with the self-calibration function. The output of the thermometer decoder circuit is connected with a thermometer code part of the weighted resistance network, an external clock CLK signal and a common-mode voltage serve as input signals of the operational amplifier module with the self-calibration function, and an output signal of the weighted resistance network passes through the operational amplifier module with the self-calibration function to obtain final analog voltage output. The resistance network adopts a mixture of thermometer codes and an R-2R structure, static indexes of the DAC can be effectively optimized, the impedance matching problem of the resistance network is reduced, a self-calibration operational amplifier technology is further applied, the influence of offset voltage of an operational amplifier on output precision can be eliminated, and the output driving capacity of the DAC is improved.

The utility model provides a magnetic flux sensor signal measuring circuit and a peak holder. The magnetic flux sensor signal measuring circuit comprises a magnetic flux sensor. The signal input end of the amplifying and filtering assembly is connected with the signal output end of the magnetic flux sensor; the signal input end of the buffer conversion assembly is connected with the signal output end of the amplifying and filtering assembly; the signal input end of the control assembly is connected with the signal output end of the amplifying and filtering assembly and the signal output end of the buffering and converting assembly. According to the utility model, peak value tracking is carried out on a voltage signal through the buffer conversion assembly, so that a post-stage circuit has sufficient time for sampling and calculation, a high-precision integral voltage value is obtained, an accurate force value of a measured component is further obtained, and a sampling starting signal is generated through the control assembly, so that the measurement precision is improved. Compared with an existing mode of discretized sampling of the integral voltage signal, the problem that the peak value of the integral voltage signal is insufficient in tracking is solved.

A latch comparator is disclosed. The latch comparator includes a first reservoir capacitor; a preamplifier including first and second transistors respectively connected to first and second inputs, the first and second transistors selectably connectable to a first terminal of the first reservoir capacitor, and third and fourth transistors respectively connected to the first and second inputs, the third and fourth transistors selectably connectable to a second terminal of the first reservoir capacitor; and a latch, including a first portion serially connected between the first and third transistors and connected to a first output, and a second portion serially connected between the second and fourth transistors and connected to a second output.

A temperature-sensing circuit is provided, which includes: a search-control circuit, a voltage-reference circuit, a CTAT (complementary to absolute temperature) circuit, a digital-to-analog converter (DAC) circuit, a comparison circuit, and an SAR (successive approximation register) circuit. The search-control circuit generates a reference-voltage selection signal according to a plurality of control signals. The voltage-reference circuit selects a first reference voltage from a plurality of candidate reference voltages according to the reference-voltage selection signal, and provides a second reference voltage. The CTAT circuit converts the second reference voltage into a first comparison voltage. The DAC circuit converts the first reference voltage into a second comparison voltage. The comparison circuit compares the first comparison voltage and the second comparison voltage to generate a comparison-result signal. The SAR control circuit outputs each bit of a temperature-segment signal of an operating temperature according to the comparison-result signal. The control signals include the temperature-segment signal.

In an embodiment, a method includes connecting a first subset of a set of stages of a power amplifier to a supply voltage, connecting a second subset of the set of stages to a reference voltage different than the supply voltage, switching a third subset of the set of stages according to a switching frequency, assigning numbers of stages in the first subset, the second subset, and the third subset based on a power requirement of the power amplifier, and amplifying a transmit signal using the first subset, the second subset, and the third subset to generate an amplified transmit signal.

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a comparator circuit for a successive approximation type ADC (Analog to Digital Converter), which comprises a pre-amplifier stage circuit and a latch stage circuit, the pre-amplifier stage circuit is a cross coupling operational amplifier, and the latch stage circuit is a stroke-arm type latch comparator; a clock signal CLK is respectively input to the power supply ends of the cross coupling operational amplifier and the latch comparator; the positive input end of the cross-coupled operational amplifier is connected with a VIP signal, the negative input end of the cross-coupled operational amplifier is connected with a VIN signal, the negative output end of the cross-coupled operational amplifier is connected with the negative input end of the latch comparator, and the positive output end of the cross-coupled operational amplifier is connected with the positive input end of the latch comparator; a two-stage structure is adopted in the circuit structure, the characteristic that the first-stage operational amplifier is easy to process low voltage is combined with the characteristic that the second-stage latch is easy to process high voltage, and the voltage comparison speed of the comparator is effectively increased.

System and method for adaptively optimizing digital-to-analog converter input range values for improved signal-to-noise ratio for analog-in-memory computing (AIMC) systems. The method includes a step of tuning the input ranges of the digital-to-analog (DAC) converters of a “tile”, comprised of Processing Elements (PEs) in a crossbar arrangement, to minimize the matrix-vector-multiplication (MVM) error under the presence of some residual noise term that is applied to the output of the MVM. Alternatively, the method includes tuning the input ranges of the DAC converters to minimize the accuracy of a predefined task, e.g., a classification task, under the presence of some residual noise term applied to the output of each matrix-vector-multiplication. The DAC input value range is optimized with respect to a metric that depends on a residual noise source present in AIMC systems. In an embodiment, the system minimizes the error introduced by the residual noise and the quantization.