1204results about "Analogue/digital conversion" patented technology

A logarithmic amplifier includes programmable gain amplifiers each having a different gain, wherein an input of each of the programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and a summing circuit having inputs coupled to a corresponding output of each of the programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit generates a logarithmic transfer function having piecewise linear segments.

A method of operating a time-interleaved analog-to-digital converter (TIADC). The TIADC converts an input signal to generate a digital output signal and includes multiple asynchronous sub-ADCs. The asynchronous sub-ADCs each convert the input signal at a different time point to generate a digital output code, and each of the asynchronous sub-ADCs generates a completion signal upon completion of an analog-to-digital conversion operation. The method includes the following steps: generating an indication signal according to the completion signals, wherein the indication signal indicates multiple candidate sub-ADCs; selecting one of the candidate sub-ADCs as a target sub-ADC according to the indication signal; and correcting the digital output code of the target sub-ADC to generate the digital output signal.

A current comparator includes: a first capacitor having a first end coupled to a first input signal; a second capacitor having a first end coupled to a second input signal; a first transistor having a control electrode coupled to the second end of the first capacitor; and a third transistor having a control electrode coupled to the second end of the second capacitor. The first current electrodes of the first and second transistors are coupled, and the second current electrodes of the first and second transistors are coupled to the first and second circuit nodes, respectively. A single-ended cascode amplifier has an input coupled to the second circuit node via a third capacitor. A set of auto-zero switches selectively shorts the control electrode of the first transistor and the second current electrode in response to an auto-zero control signal, and selectively shorts the control electrode of the second transistor and the second current electrode.

Certain aspects of the present disclosure generally relate to a digital-to-analog converter (DAC) circuit implemented with a dynamic stacked transistor architecture. The DAC circuit generally includes a first current-steering transistor and a second current-steering transistor. The DAC circuit may also include: a first stacked transistor coupled between the first current-steering transistor and a first output of the DAC circuit; a first switch coupled between a gate of the first stacked transistor and a bias voltage node; a second switch coupled between the gate of the first stacked transistor and a voltage rail; a second stacked transistor coupled between the second current-steering transistor and a second output of the DAC circuit; a third switch coupled between a gate of the second stacked transistor and the bias voltage node; and a fourth switch coupled between the gate of the second stacked transistor and the voltage rail.

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

A sigma-delta analog-to-digital converter is provided that includes an initial continuous-time integration stage having a variable input resistor and an integration capacitor. A switched-capacitor circuit charges and discharges a replica capacitor to a reference voltage to generate a bias current. A SAR-based tuning circuit includes a variable tuning resistor that generates a tuning voltage while conducting a mirrored version of the bias current. A resistance of the variable input resistor is adjusted responsive to a tuning code from the SAR-based tuning circuit.

A multi-channel analog-digital converter (ADC) subsystem for test device such as a spectrum analyzer may include multiple multi-channel ADCs to receive down-converted signals and convert the received signals to digital output signals, a field programmable gate array (FPGA) to select one or more ADCs based on a frequency, a bandwidth, and / or a signal type of each received signal and a characteristic of each ADC, and an ADC sample clock to provide a clock signal to the selected ADCs. Characteristics of the ADCs may include a resolution, a signal-to-noise-and-distortion ratio (SINAD), an effective number of bits (ENOB), a signal-to-noise ratio (SNR), a total harmonic distortion (THD), a total harmonic distortion plus noise (THD+N), and / or a spurious free dynamic range (SFDR).

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes an ADC with a continuous time integrator. The continuous time integrator includes an amplifier having an amplifier input and an amplifier output, a capacitor coupled between the amplifier input and the amplifier output, and a resistor. The resistor provides a first current for an integration in response to an analog input. The ADC also includes a DAC configured to generate a second current at an DAC output based on a digital output of the ADC and includes a switch circuit with a first switch circuit terminal coupled with the DAC output and a second switch circuit terminal coupled with the amplifier input. The switch circuit is configured to couple the DAC output with the amplifier input for a summation of the second current with the first current for the integration based on an integration control signal.

The invention discloses a high-speed and high-linearity margin amplifier and an analog-to-digital converter, belongs to the technical field of integrated circuits, and solves the technical problem that an existing source follower cannot meet high-speed and high-linearity indexes. The amplifier comprises a margin amplifier bias and output module, a phase inverter and a linear transconductance unit based on an AB-class super source follower structure, wherein the bias and output module, the linear transconductance unit and the phase inverter are connected in sequence. The linear transconductance unit can generate high-linearity transconductance, so that the linearity of the whole margin amplifier is improved, the symmetry of the positive output end and the negative output end of the margin amplifier under the condition of high-frequency or large-swing input can be ensured, and the high-speed and high-linearity index can be effectively met. In addition, a gain calibration module resistant to temperature and process changes is further introduced, and the influence caused by follow-up system environment temperature changes can be automatically compensated.

The present invention provides a novel semiconductor device. The present invention uses a comparison unit for comparing two current values, a control unit, and a current output type digital-analog conversion unit to convert an analog signal into a digital signal. The control unit has the function of generating a sign bit indicating the magnitude relation between the two current values, the function of converting, by successive approximation, the difference between the two current values into the digital signal, and the function of outputting the sign bit and the digital signal.

A monotonic capacitor digital-to-analog converter (CDAC) is provided. The CDAC includes a converter array comprising a plurality of CDAC units, wherein each CDAC unit comprises a logic unit, a switch, and a capacitor, and wherein each logic unit comprises a first input, a second input, and a third input. The CDAC further includes a first set of control lines, and each of the first set of control lines is connected to the first inputs of the logic units of the CDAC units in a corresponding column of the converter array. The CDAC further includes a second set of control lines, and each of the second set of control lines is connected to the second inputs of the logic units of the CDAC units in a corresponding row of the converter array, but is disconnected from the second input of the logic unit of a CDAC unit in the corresponding row and the last column of the converter array. Each of the second set of control lines is further connected to the third inputs of the logic units of the CDAC units in a row of the converter array adjacent to the corresponding row.

The invention provides a single-ended input successive approximation analog-to-digital converter and an optical module chip. In a sampling stage, upper electrode plates of a plurality of first capacitors are connected with an input voltage Vin, part of lower electrode plates are connected with the input voltage Vin, and part of the lower electrode plates are connected with a reference voltage Vref; the upper electrode plates of the plurality of second capacitors are connected with a reference voltage Vref, part of the lower electrode plates are connected with an input voltage Vin, and part of the lower electrode plates are connected with the reference voltage Vref; in the pre-switching stage, an upper pole plate switch is switched off, and lower pole plate voltages of the multiple first capacitors and the multiple second capacitors are switched according to a preset mode, so that the upper pole plate voltages of the multiple first capacitors are all changed into a first preset voltage Vp, and the upper pole plate voltages of the multiple second capacitors are all changed into a second preset voltage Vn; in the comparison stage, the first preset voltage Vp and the second preset voltage Vn are input into the comparator for first-stage comparison. Through preset switching logic, single-ended analog-to-digital converter input can be converted into differential comparator input.

An analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) configured to change a signal level of a first node based on a first and second input analog signals, a second DAC configured to change a signal level of a second node based on one of the first input analog signal and the second input analog signal, a comparator configured to compare the signal level of the first node and the signal level of the second node, and a controller configured to generate a first digital value for the first DAC and a second digital value for the second DAC based on an output of the comparator during a first conversion phase corresponding to a first sampling phase, input the first digital value into the second DAC before a second sampling phase, and input the second digital value into the first DAC before the second sampling phase.

A capacitive digital-to-analog converter (CDAC) comprising a capacitive structure and a control logic circuit coupled to each other is provided. The control logic circuit comprises switch groups that each comprises first and second switch circuits. The first and second switch circuits each comprise first, second terminals, a first via and a control terminal. The first terminal is configured to receive a source voltage or a ground voltage through a first metal layer of the CDAC. The second terminal is configured to be coupled to the capacitive structure through the first via extending in a vertical direction. The control terminal is configured to receive one of a plurality of turn-on signals through a second metal layer of the CDAC. The capacitive structure is located at least in a third metal layer of the CDAC. The third metal layer is located above the first and second metal layers.

An integrated circuit (IC), comprising: a first gain stage configured to apply a first gain to a first signal to generate a first amplified signal; a first converter configured to convert the first signal to a first output signal; a first output pin for outputting the first output signal; gain update circuitry configured to: output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, subsequently output a first external gain control signal to a second output pin of the IC, wherein output of the first external gain control signal is delayed relative to output of the first internal gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first gain stage and the first output pin.

An apparatus for calibrating a digital filter to replicate a transfer function of a signal processing device comprising a detector with a first input to receive a first signal; a second input to receive a response signal of the signal processing device to the first signal; a signal modification block; a comparison block and a decimation block; wherein the comparison-block compares a phase and amplitude of the first signal after a correction has been applied by the signal modification block and decimation has been applied by the decimation block; and a feedback loop; wherein detector is configured to determine at least a feedback control signal at a first frequency and a second frequency, different to the first frequency and determine calibration information for programming of the transfer function of said digital filter.

The invention discloses a high-precision R-2R voltage type digital-to-analog converter based on a binary weighted code and a thermometer code, the digital-to-analog converter comprises a weighted resistance network, a thermometer decoder circuit and an operational amplifier module with a self-calibration function, the output of the weighted resistance network is connected with the operational amplifier module with the self-calibration function, and the output of the thermometer decoder circuit is connected with the operational amplifier module with the self-calibration function. The output of the thermometer decoder circuit is connected with a thermometer code part of the weighted resistance network, an external clock CLK signal and a common-mode voltage serve as input signals of the operational amplifier module with the self-calibration function, and an output signal of the weighted resistance network passes through the operational amplifier module with the self-calibration function to obtain final analog voltage output. The resistance network adopts a mixture of thermometer codes and an R-2R structure, static indexes of the DAC can be effectively optimized, the impedance matching problem of the resistance network is reduced, a self-calibration operational amplifier technology is further applied, the influence of offset voltage of an operational amplifier on output precision can be eliminated, and the output driving capacity of the DAC is improved.

The utility model provides a magnetic flux sensor signal measuring circuit and a peak holder. The magnetic flux sensor signal measuring circuit comprises a magnetic flux sensor. The signal input end of the amplifying and filtering assembly is connected with the signal output end of the magnetic flux sensor; the signal input end of the buffer conversion assembly is connected with the signal output end of the amplifying and filtering assembly; the signal input end of the control assembly is connected with the signal output end of the amplifying and filtering assembly and the signal output end of the buffering and converting assembly. According to the utility model, peak value tracking is carried out on a voltage signal through the buffer conversion assembly, so that a post-stage circuit has sufficient time for sampling and calculation, a high-precision integral voltage value is obtained, an accurate force value of a measured component is further obtained, and a sampling starting signal is generated through the control assembly, so that the measurement precision is improved. Compared with an existing mode of discretized sampling of the integral voltage signal, the problem that the peak value of the integral voltage signal is insufficient in tracking is solved.

A latch comparator is disclosed. The latch comparator includes a first reservoir capacitor; a preamplifier including first and second transistors respectively connected to first and second inputs, the first and second transistors selectably connectable to a first terminal of the first reservoir capacitor, and third and fourth transistors respectively connected to the first and second inputs, the third and fourth transistors selectably connectable to a second terminal of the first reservoir capacitor; and a latch, including a first portion serially connected between the first and third transistors and connected to a first output, and a second portion serially connected between the second and fourth transistors and connected to a second output.

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a comparator circuit for a successive approximation type ADC (Analog to Digital Converter), which comprises a pre-amplifier stage circuit and a latch stage circuit, the pre-amplifier stage circuit is a cross coupling operational amplifier, and the latch stage circuit is a stroke-arm type latch comparator; a clock signal CLK is respectively input to the power supply ends of the cross coupling operational amplifier and the latch comparator; the positive input end of the cross-coupled operational amplifier is connected with a VIP signal, the negative input end of the cross-coupled operational amplifier is connected with a VIN signal, the negative output end of the cross-coupled operational amplifier is connected with the negative input end of the latch comparator, and the positive output end of the cross-coupled operational amplifier is connected with the positive input end of the latch comparator; a two-stage structure is adopted in the circuit structure, the characteristic that the first-stage operational amplifier is easy to process low voltage is combined with the characteristic that the second-stage latch is easy to process high voltage, and the voltage comparison speed of the comparator is effectively increased.

System and method for adaptively optimizing digital-to-analog converter input range values for improved signal-to-noise ratio for analog-in-memory computing (AIMC) systems. The method includes a step of tuning the input ranges of the digital-to-analog (DAC) converters of a “tile”, comprised of Processing Elements (PEs) in a crossbar arrangement, to minimize the matrix-vector-multiplication (MVM) error under the presence of some residual noise term that is applied to the output of the MVM. Alternatively, the method includes tuning the input ranges of the DAC converters to minimize the accuracy of a predefined task, e.g., a classification task, under the presence of some residual noise term applied to the output of each matrix-vector-multiplication. The DAC input value range is optimized with respect to a metric that depends on a residual noise source present in AIMC systems. In an embodiment, the system minimizes the error introduced by the residual noise and the quantization.

A display device includes a display panel including pixels, a power voltage generator which provides a power voltage to the display panel, a power current sensor which senses a power current of the display panel and generates a power current code by performing analog-to-digital conversion on the sensed power current, and a timing controller which determines an analog-to-digital conversion time of the power current based on a peak white luminance.

Described herein is a computer implemented method for correcting for clock drift of a system clock in a signal sampling device comprising the system clock and configured to sample a signal in real time, the method comprising: obtaining data relating to an environmental parameter of an environment of the signal sampling device; matching the data relating to the environmental parameter to an environmental scenario; selecting, from a model set, a model tagged with the matched environmental scenario; and correcting for clock drift of the system clock using the selected model. Also described herein is a method for preparing a model set for clock drift correction, a sampling device, and a computer implemented method for correcting for clock drift of the system clocks of an array of signal sampling devices.

The invention relates to the technical field of integrated circuits, in particular to a capacitive coupling type current steering digital-to-analog converter for transmitting switch control signals, which comprises a current steering unit and a switch signal control unit. The switching signal control unit comprises two capacitance coupling type level shifters; the current steering unit comprises a current source and transistors M1-M4, source electrodes of the transistors M1-M4 are connected with one end of the current source, and the other end of the current source is grounded; drain electrodes of the transistors M1-M2 are connected to form a positive output signal, and drain electrodes of the transistors M3-M4 are connected to form a negative output signal; the grid electrodes of the transistors M1-M2 are connected with a first capacitive coupling type level shifter, and the transistors M3-M4 are connected with a second capacitive coupling type level shifter; the on and off of the transistors M1-M4 are controlled through the two capacitance coupling type level shifters; the cross coupling unit is introduced to assist in transmitting switch control signals, and the dynamic performance of the digital-to-analog converter is improved.

System and method for adaptively optimizing digital-to-analog converter input range values for improved signal-to-noise ratio for analog-in-memory computing (AIMC) systems. The method includes a step of tuning the input ranges of the digital-to-analog (DAC) converters of a "tile", comprised of Processing Elements (PEs) in a crossbar arrangement, to minimize the matrix-vector- multiplication (MVM) error under the presence of some residual noise term that is applied to the output of the MVM. Alternatively, the method includes tuning the input ranges of the DAC converters to minimize the accuracy of a predefined task, e.g., a classification task, under the presence of some residual noise term applied to the output of each matrix-vector-multiplication. The DAC input value range is optimized with respect to a metric that depends on a residual noise source present in AIMC systems. In an embodiment, the system minimizes the error introduced by the residual noise and the quantization.

An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.

Power consumption is reduced in an analog-to-digital conversion circuit using a TDC. The analog-to-digital conversion circuit includes a comparator, a counter, a time-to-digital converter, and a holding unit. The comparator compares an analog signal with a predetermined reference signal and outputs a comparison result. The counter counts a predetermined count value and outputs a bit string indicating the count value. The time-to-digital converter converts, into a digital signal, a time from when the comparison result is inverted until a least significant bit of the bit string reaches a predetermined value. The holding unit holds the bit string of when the comparison result is inverted.

The present invention relates a multi-shot time-to-digital converter and a time-measurement device. The multi-shot time-to-digital converter includes a time-to-digital conversion circuit and a timing control circuit. The timing control circuit is coupled to the time-to-digital conversion circuit and sending a start signal to the time-to-digital conversion circuit multiple times for measuring a time interval corresponding to the start signal. The time-to-digital conversion circuit obtains a fine phase time based on a plurality of clock signals to measure the time interval and provides a plurality of time-to-digital codes for digital processing. The clock signals have different phases. The time-to-digital codes are further processed to obtain the time-to-digital codes with better resolution.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

The invention discloses an Isin machine which comprises N nodes for simulating spinning, a spinning state register, a processor and an input signal generating circuit. Each node generates a digital signal based on an input analog signal, the probability that the output digital signal is 1 being determined by the input analog signal. And the processor obtains the spinning of the N nodes after the mth iteration. The processor calculates a target input value for each node based on the spin of the N nodes. The processor determines an input signal combination Inm + 1 (In1m + 1, In2m + 1,... Innm + 1) and a corresponding criterion according to the target input value. Each of In1m + 1, In2m + 1, to Innm + 1 is selected from a first candidate input analog signal and a second candidate input analog signal. The input signal combinations are sequentially input to nodes, and the processor obtains n output digital signals from each node. And if the output digital signal output by the node is the same as the judgment standard, the spin of the node after (m + 1) th iteration is judged to be a first value, otherwise, the spin of the node is judged to be a second value. According to the invention, the number of digital-to-analog converters is reduced.