450results about "Analogue/digital conversion" patented technology

The invention provides a single-ended input successive approximation analog-to-digital converter and an optical module chip. In a sampling stage, upper electrode plates of a plurality of first capacitors are connected with an input voltage Vin, part of lower electrode plates are connected with the input voltage Vin, and part of the lower electrode plates are connected with a reference voltage Vref; the upper electrode plates of the plurality of second capacitors are connected with a reference voltage Vref, part of the lower electrode plates are connected with an input voltage Vin, and part of the lower electrode plates are connected with the reference voltage Vref; in the pre-switching stage, an upper pole plate switch is switched off, and lower pole plate voltages of the multiple first capacitors and the multiple second capacitors are switched according to a preset mode, so that the upper pole plate voltages of the multiple first capacitors are all changed into a first preset voltage Vp, and the upper pole plate voltages of the multiple second capacitors are all changed into a second preset voltage Vn; in the comparison stage, the first preset voltage Vp and the second preset voltage Vn are input into the comparator for first-stage comparison. Through preset switching logic, single-ended analog-to-digital converter input can be converted into differential comparator input.

A latch comparator is disclosed. The latch comparator includes a first reservoir capacitor; a preamplifier including first and second transistors respectively connected to first and second inputs, the first and second transistors selectably connectable to a first terminal of the first reservoir capacitor, and third and fourth transistors respectively connected to the first and second inputs, the third and fourth transistors selectably connectable to a second terminal of the first reservoir capacitor; and a latch, including a first portion serially connected between the first and third transistors and connected to a first output, and a second portion serially connected between the second and fourth transistors and connected to a second output.

Described herein is a computer implemented method for correcting for clock drift of a system clock in a signal sampling device comprising the system clock and configured to sample a signal in real time, the method comprising: obtaining data relating to an environmental parameter of an environment of the signal sampling device; matching the data relating to the environmental parameter to an environmental scenario; selecting, from a model set, a model tagged with the matched environmental scenario; and correcting for clock drift of the system clock using the selected model. Also described herein is a method for preparing a model set for clock drift correction, a sampling device, and a computer implemented method for correcting for clock drift of the system clocks of an array of signal sampling devices.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

Signal processing circuitry configured to receive an input signal and to output a processed output signal, wherein the signal processing circuitry is configured to: receive an indication of a temporal location of a transient in the input signal; and provide, in the processed output signal, a masking signal bridging the temporal location of the transient to mask the transient.

The invention belongs to the technical field of photoelectric fusion integrated circuits, and particularly discloses a parallel PWM expansion high-precision programmable DAC structure. The adjusting module is used for adjusting the thermo-optical phase shifter according to the received digital control signal; the DAC structure specifically comprises a pulse width modulation signal generator and a current source array, wherein the pulse width modulation signal generator is used for acquiring a low-order code element from the digital control signal to generate a pulse width modulation signal, and sending the pulse width modulation signal to the current source array; wherein the current source array is used for acquiring a high-order code element from the digital control signal to generate a high-order analog signal; a low-order analog signal is generated based on the pulse width modulation signal; and the processor is also used for weighting and accumulating the low-order analog signal and the high-order analog signal to obtain an analog control signal and outputting the analog control signal. The DAC structure is high in precision and simple in structure.

This application relates to sensing of signals with a common-mode variation. Embodiments describe a switching driver circuit with a modulator configured to control modulation of an output node between different switching voltages and a current sensor configured to sense a voltage drop across a sense resistor connected in series with the output node. The current sensor performs sensing during a first time window that occurs at regular intervals and the modulator avoids any transition in switching voltage at the first output node during the first time window. Embodiments also describe a sensing circuit for sensing a differential voltage with a common-mode variation which has a first sensing portion implemented to provide a floating voltage domain and a second sensing portion implemented to provide a static voltage domain. At least one switched capacitor provides a boundary between the voltage domains and is switched to transfer charge between the voltage domains.

The invention discloses a DAC (Digital-to-Analog Converter) output voltage control method, system and equipment based on stepping delay and a medium. The method comprises the following steps: acquiring the current output voltage of the DAC as an initial voltage value; receiving a target voltage value and a set value of a target slope parameter; the target slope parameter comprises a target step length and a target delay; and controlling the initial voltage value to gradually change from the target slope to the target voltage value through the target slope parameter. The method is realized without depending on a hardware circuit, the DAC can change the output voltage according to the set slope parameter through a software implementation process, and the requirements on the DAC output voltage slope in different scenes can be met. According to the method, the target slope parameter and the target voltage value can be changed at any time in the DAC output voltage adjusting process, the DAC output voltage is controlled to be changed into the new target voltage value according to the new slope parameter, and no error exists in the software running process. The method is easy to modify and migrate and has high universality.

The present description provides for a method of controlling an analog-to-digital converter. In an example method, the most significant bits are determined by successive approximations. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of a first digital-to-analog converter with a third digital-to-analog converter and by applying a second ramp to the output of the second digital-to-analog converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first digital-to-analog converter and second digital-to-analog converter at the end of the successive approximations.

Methods and system for signal sampling using spatial dispersion are disclosed. In an example, a system includes a time-to-wavelength dispersion system configured to generate a wavelength dispersed optical pulse that is modulated according to an input signal, a wavelength-to-space dispersion system configured to spatially disperse the wavelength dispersed optical pulse by wavelength to produce a spatially dispersed optical pulse, a sensor system configured to convert the spatially dispersed optical pulse to electrical signals, the sensor system including a two-dimensional (2D) array of photodetectors, and a processor configured to decode the electrical signals to generate information about the input signal.

Apparatus and associated methods relate to a transformer-less way of demodulating signals generated by a synchro-resolver so as to determine a shaft angle of the synchro-resolver. A first differential output voltage between a first pair of the wye-configured secondary windings is used to generate a first output. A second differential output voltage between a second pair of the wye-configured secondary windings, different from the first pair, is used to generate a second output. The first and second outputs are combined to form a signal quadrature to the first output. The first output and the signal quadrature thereto are used to determine the shaft angle.

The invention belongs to the technical field of gate voltage bootstrapped switches, and discloses a high-performance gate voltage bootstrapped switch for a Sigma-Delta ADC, a PMOS switch circuit is introduced into an NMOS type gate voltage bootstrapped switch circuit to form a complementary switch, and the complementary switch is used for counteracting an output error caused by a clock feed-through effect of an NMOS switch and the PMOS switch; virtual tubes are added to the input and output ends of the NMOS switch and the PMOS switch by using an inverter chain and are used for absorbing channel charges of the switch tubes; the substrate potential of the NMOS switch and the substrate potential of the PMOS switch are connected into the switching circuit, so that the substrate potential of the switching tube is switched between GND and input voltage Vin, and on the premise that sampling / maintaining precision is guaranteed, interference of clock feed-through and charge injection in the switching tube on output signals is restrained, and the linearity of the grid voltage bootstrapped switch is improved.

In an embodiment, a method includes connecting a first subset of a set of stages of a power amplifier to a supply voltage, connecting a second subset of the set of stages to a reference voltage different than the supply voltage, switching a third subset of the set of stages according to a switching frequency, assigning numbers of stages in the first subset, the second subset, and the third subset based on a power requirement of the power amplifier, and amplifying a transmit signal using the first subset, the second subset, and the third subset to generate an amplified transmit signal.

The application belongs to the field of integrated circuits, and particularly relates to a dynamic biasing ring amplifier, a biasing module, a pipeline SAR ADC and a chip. The circuit comprises an amplifier main body, a feedback loop and a biasing unit. The output end of the second stage of the amplifier main body comprises CMOS resistors P3 and N3. The biasing unit is used for synchronously generating a dynamic biasing signal V BL and V BH output to the gate of P3 and N3 according to the reset signal RST and the amplification signal AMP input in the feedback loop. The biasing unit comprises one PMOS tube P5, two NMOS tubes N5 and N6 and one capacitor C0. The source of P5 is connected to a power supply, the gate of P5 and N6 is connected to AMP; the drain of P5 and the source of N6 are connected to the upper plate of C0 and serve as the output port of V BH . The source of N5 is connected to the ground, the gate of N5 is connected to RST, and the drain of N5 and N6 is connected to the lower plate of C0 and serves as the output port of V BL . The application solves the problems of the existing dynamic biasing ring amplifier, such as the difficulty in balancing the noise resistance performance and the circuit power consumption.

Systems and methods for correcting timing information associated with captured nuclear imaging data, and for reconstructing medical images based on the corrected timing information, are disclosed. In some embodiments, an image scanning system scans a subject, detects an event, and generates timing data for the detected event. The timing data includes a first number of bits, and characterizes a time that a crystal of the image scanning system detected the event. The image scanning system shifts the first number of bits by a predetermined amount to generate a second number of bits, where the second number of bits includes at least one bit representing a lower order time value than the least significant bit of the first number of bits of the timing data. Further, the image scanning system generates timing correction data for the event based on the second timing data.

[Problem] To make it possible to suppress processing time while maintaining processing accuracy in analog-to-digital conversion processing. [Solution] The present disclosure provides an information processing device comprising: a cell array that has cells which output a calculated voltage to a signal line on the basis of an input signal and a coefficient to be retained; an analog-to-digital converter that outputs a digital value on the basis of a ramp voltage and the voltage of the signal line; and a voltage control unit that controls the voltage range of the ramp voltage.

The invention discloses a magnetic axis keyboard Hall sensor array reading circuit and a reading method. The device comprises a Hall sensor array, a controllable power supply array, a control module, two 1-out-of-N selectors, an analog comparator, a digital comparator, an analog-to-digital converter and a digital-to-analog converter. The power supply end of each Hall sensor is connected with the output end of the corresponding controllable power supply, and signals input by the high-voltage enabling end and the low-voltage enabling end of each controllable power supply are not high levels at the same time. A mobile threshold register and a trigger threshold register are arranged in the control module, output ends of the N Hall sensors are respectively connected with corresponding input ends of the two one-out-of-N selectors, and the two one-out-of-N selectors are respectively connected with the mobile threshold register and the trigger threshold register through the analog comparator and the digital comparator. According to the invention, adaptive frequency modulation and voltage regulation can be carried out, the working current of the Hall sensor array is greatly reduced, the working time of the magnetic axis keyboard is prolonged, and the key delay is reduced.

This invention discloses a high-precision ramp generator and a two-step single-slope analog-to-digital converter. The ramp generator includes a bandgap reference source circuit, a voltage-to-current conversion circuit, a weighted current DAC current source array, a charge / discharge current regulation circuit, a mode switching circuit, and a bias circuit. In this invention, the quantization process of the ramp generator is decomposed into two stages: coarse quantization and fine quantization, significantly reducing quantization time. Furthermore, a single output stage can combine a DAC-type ramp generator and a capacitor-integrating ramp generator, saving area and power consumption in chip design, improving the compatibility of the ramp generator, solving the linearity and stability problems introduced by stepped ramps in high-speed, high-precision applications, and reducing design complexity.

The invention relates to programming for non-volatile memory. According to an embodiment, a circuit for generating an adaptive set pulse current for a phase change memory (PCM) cell is disclosed. The circuit includes: a first current digital-to-analog converter (IDAC) and a second IDAC, each IDAC configured to generate a bias current having a programmable curve, the programmable curve including: a constant current phase at a predefined set current; a first ramp down phase from a predefined set current to a minimum off current; a second ramp down phase from a minimum off current to zero; and a zero current phase, wherein the constant current phase of each IDAC begins in response to another IDAC starting a second ramp-down phase; and a programming circuit configured to select one of the bias currents from the first IDAC and the second IDAC and generate an adaptive set pulse current.

An isolation interface circuit for a modular energy system is disclosed. A comparator is configured to couple to a switch and a reference voltage and an output. A replica comparator is configured to couple to the switch and the reference voltage. An expander circuit is coupled to the comparator and the replica comparator. An isolator circuit is coupled to the expander circuit. A controller is coupled to the isolator circuit. The controller is configured to compare an output of the comparator to an output of the replica comparator and determine, based on the comparison, to activate or deactivate a surgical instrument coupled to the controller.

A class D amplifier including a pulse width modulation (PWM) control loop, an H-bridge driver, a PWM controller having a PWM pulse generator to generate PWM pulses supplied to the H-bridge driver in response to an ADC value output by an analog-to-digital converter of the PWM control loop, and a comparator. The comparator is configured to trigger a cutoff of a PWM pulse generated by the PWM pulse generator during a respective loop cycle of the PWM control loop and to trigger generation of at least one counter PWM pulse with an opposite polarity in the respective loop cycle such that a net pulse energy of the cutoff PWM pulse and of the at least one generated counter PWM pulse corresponds to a pulse energy representing the ADC value provided by the analog-to-digital converter of the PWM control loop during the respective loop cycle.

An apparatus includes a first D flip-flop including a first data output, a first negative edge-triggered clock input, and a first reset input, and a second D flip-flop including a second data output, a second negative edge-triggered clock input, and a second reset input. The apparatus includes a logic gate having an output and first and second inputs, the first input of the logic gate coupled to the first data output, and the second input of the logic gate coupled to the second data output, in which the output of the logic gate is configured to be a first clock output of the apparatus. A delay circuit of the apparatus includes an output and input, the output of the delay circuit coupled to the first and second reset inputs, and the input of the delay circuit coupled to the output of the logic gate.

The application relates to the technical field of integrated circuits, in particular to a popular C-2C structure multi-section capacitor array and application thereof. The application comprises a capacitor array, a bridging capacitor, a redundant capacitor, an input stage and an output stage, wherein the capacitor array comprises n sections, each section comprises S-bit capacitors arranged in parallel, all the lower plates of the capacitors of the capacitor array are connected with the input stage, the bridging capacitor is arranged between the S-bit capacitors of the n sections of the capacitor array, the first section of the capacitor array is connected with the redundant capacitor, and the nth section is connected with the output stage. The application relieves the conflict between the effective number of bits and the chip area of the high-precision analog-to-digital converter and digital-to-analog converter capacitor array, and simultaneously improves the problem of traditional C-2C structure capacitor matching.

A test and measurement device comprises two or more channels to enable the test and measurement device to connect to a device under test (DUT), each channel comprising an analog-to-digital converter (ADC) and one or more trigger devices, each trigger device determining one or more trigger conditions, a display to enable the test and measurement device to display data from the ADC, a user interface, and one or more processors configured to execute code to cause the one or more processors to acquire data from the two or more channels at a different time than other two or more channels in response to one or more trigger conditions.A test and measuring instrument similar to the one mentioned above, except that in addition to one or more channels with ADCs, it includes at least one channel with an auxiliary input and a threshold detector instead of an ADC.

A ramp generator is provided that allows for an increase in the swing range of the ramp signal. [Solution] The lamp generator 10 has multiple control signals CON <n:0>Based on this, the current value of the reference current IREF applied to the first node ND1 is adjusted, and multiple control signals CON are used. <n:0>The system may include a current control unit 300 that controls the current value of the current applied to the second node ND2 based on some of the control signals, a bias voltage generation unit 500 that generates bias voltages VBIAS1 and VBIAS2 based on currents mirrored according to the first node ND1 and the second node ND2, and a ramp signal generation unit 600 that generates a ramp signal VRAMP based on the bias voltages VBIAS1 and VBIAS2.< / n:0>

A circuit includes a comparator configured to generate a first conversion gain output signal by comparing a first pixel signal corresponding to a first conversion gain with a first ramp signal, and generate a second conversion gain output signal by comparing a second pixel signal corresponding to a second conversion gain with a second ramp signal, and a counter configured to count pulses of the first conversion gain output signal, output a counting result as a first digital signal, and determine whether an output of a second digital signal corresponding to the second conversion gain is required, based on the first digital signal. The first conversion gain is higher than the second conversion gain, and based on determining that the output of the second digital signal is not required, the counter is further configured to control the comparator such that the second conversion gain output signal is not generated.

A successive approximation register (SAR) type analog-to-digital converter (ADC) can be used to generate N bits of first digital data and N bits of second digital data for analog data. If the second digital data and the first digital data contain a first most significant bit (MSB) sequence with the same value, the SAR ADC can be used in partial mode to generate N bits of third digital data for the analog data. In partial mode, the SAR ADC is configured to skip determining the second MSB sequence of the third digital data and determine only the remaining bits of the third digital data. If the second digital data and the first digital data do not contain a first MSB sequence with the same value, the SAR ADC operates in full mode to determine all bits of the N bits of the third digital data.

The application discloses an R-2R digital-analog converter circuit integrated with hysteresis voltage control and relates to the technical field of integrated circuit design, which comprises an operational amplifier, an R2R resistance network and a hysteresis voltage control unit. The operational amplifier comprises a non-inverting input end for receiving a threshold voltage, an inverting input end for receiving a test voltage and an output end for outputting a comparison voltage. The R2R resistance network comprises an output end for outputting the threshold voltage, which is connected with the non-inverting input end of the operational amplifier. The R2R resistance network further comprises a plurality of first resistors connected in series, a plurality of second resistors and a plurality of selection switches. The hysteresis voltage control unit comprises a plurality of third resistors, a plurality of first knife switches and a second knife switch, and further comprises an input end for the comparison voltage. The second knife switch is used for selectively connecting a reference voltage end or a ground end according to the polarity of the comparison voltage. The application has the advantages of simple structure and easy use. The size and direction of the hysteresis voltage can be flexibly adjusted according to the use requirement. No glitch signal is generated in the hysteresis voltage switching process, and the stable and reliable digital-analog conversion function is realized.

A simplified electronics approach to allow cost, size, and power consumption to be reduced while maintaining state of the art accuracy and reliability, key features for wireless medical devices / sy stems and industrial sensors alike. Extreme accuracy is achieved by innovative noise shaping and filtering introduced to the electrochemical sensor, before sampling by the analog to digital converter. Introduction of the noise and bias to the electrochemical sensor provides very low power biasing which is necessary to achieve overall reliable and very accurate bias for the electrochemical reaction cell.

An example apparatus includes: a first switch having a first terminal and a second terminal; analog-to-digital converter (ADC) circuitry having an input and an output, the input of the ADC circuitry coupled to the first terminal of the first switch; digital-to-analog converter (DAC) circuitry having an input and an output, the input of the DAC circuitry coupled to the output of the ADC circuitry; combination circuitry having a first input, a second input, and an output, the first input of the combination circuitry coupled to the second terminal of the first switch, the second input of the combination circuitry coupled to the output of the DAC circuitry; amplifier circuitry having an input and an output, the input of the amplifier circuitry coupled to the output of the combination circuitry; and a second switch having a terminal coupled to the output of the amplifier circuitry.