866results about "Analogue/digital conversion" patented technology

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

The invention provides a single-ended input successive approximation analog-to-digital converter and an optical module chip. In a sampling stage, upper electrode plates of a plurality of first capacitors are connected with an input voltage Vin, part of lower electrode plates are connected with the input voltage Vin, and part of the lower electrode plates are connected with a reference voltage Vref; the upper electrode plates of the plurality of second capacitors are connected with a reference voltage Vref, part of the lower electrode plates are connected with an input voltage Vin, and part of the lower electrode plates are connected with the reference voltage Vref; in the pre-switching stage, an upper pole plate switch is switched off, and lower pole plate voltages of the multiple first capacitors and the multiple second capacitors are switched according to a preset mode, so that the upper pole plate voltages of the multiple first capacitors are all changed into a first preset voltage Vp, and the upper pole plate voltages of the multiple second capacitors are all changed into a second preset voltage Vn; in the comparison stage, the first preset voltage Vp and the second preset voltage Vn are input into the comparator for first-stage comparison. Through preset switching logic, single-ended analog-to-digital converter input can be converted into differential comparator input.

An analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) configured to change a signal level of a first node based on a first and second input analog signals, a second DAC configured to change a signal level of a second node based on one of the first input analog signal and the second input analog signal, a comparator configured to compare the signal level of the first node and the signal level of the second node, and a controller configured to generate a first digital value for the first DAC and a second digital value for the second DAC based on an output of the comparator during a first conversion phase corresponding to a first sampling phase, input the first digital value into the second DAC before a second sampling phase, and input the second digital value into the first DAC before the second sampling phase.

An apparatus for calibrating a digital filter to replicate a transfer function of a signal processing device comprising a detector with a first input to receive a first signal; a second input to receive a response signal of the signal processing device to the first signal; a signal modification block; a comparison block and a decimation block; wherein the comparison-block compares a phase and amplitude of the first signal after a correction has been applied by the signal modification block and decimation has been applied by the decimation block; and a feedback loop; wherein detector is configured to determine at least a feedback control signal at a first frequency and a second frequency, different to the first frequency and determine calibration information for programming of the transfer function of said digital filter.

The invention discloses a high-precision R-2R voltage type digital-to-analog converter based on a binary weighted code and a thermometer code, the digital-to-analog converter comprises a weighted resistance network, a thermometer decoder circuit and an operational amplifier module with a self-calibration function, the output of the weighted resistance network is connected with the operational amplifier module with the self-calibration function, and the output of the thermometer decoder circuit is connected with the operational amplifier module with the self-calibration function. The output of the thermometer decoder circuit is connected with a thermometer code part of the weighted resistance network, an external clock CLK signal and a common-mode voltage serve as input signals of the operational amplifier module with the self-calibration function, and an output signal of the weighted resistance network passes through the operational amplifier module with the self-calibration function to obtain final analog voltage output. The resistance network adopts a mixture of thermometer codes and an R-2R structure, static indexes of the DAC can be effectively optimized, the impedance matching problem of the resistance network is reduced, a self-calibration operational amplifier technology is further applied, the influence of offset voltage of an operational amplifier on output precision can be eliminated, and the output driving capacity of the DAC is improved.

A latch comparator is disclosed. The latch comparator includes a first reservoir capacitor; a preamplifier including first and second transistors respectively connected to first and second inputs, the first and second transistors selectably connectable to a first terminal of the first reservoir capacitor, and third and fourth transistors respectively connected to the first and second inputs, the third and fourth transistors selectably connectable to a second terminal of the first reservoir capacitor; and a latch, including a first portion serially connected between the first and third transistors and connected to a first output, and a second portion serially connected between the second and fourth transistors and connected to a second output.

Described herein is a computer implemented method for correcting for clock drift of a system clock in a signal sampling device comprising the system clock and configured to sample a signal in real time, the method comprising: obtaining data relating to an environmental parameter of an environment of the signal sampling device; matching the data relating to the environmental parameter to an environmental scenario; selecting, from a model set, a model tagged with the matched environmental scenario; and correcting for clock drift of the system clock using the selected model. Also described herein is a method for preparing a model set for clock drift correction, a sampling device, and a computer implemented method for correcting for clock drift of the system clocks of an array of signal sampling devices.

The invention relates to the technical field of integrated circuits, in particular to a capacitive coupling type current steering digital-to-analog converter for transmitting switch control signals, which comprises a current steering unit and a switch signal control unit. The switching signal control unit comprises two capacitance coupling type level shifters; the current steering unit comprises a current source and transistors M1-M4, source electrodes of the transistors M1-M4 are connected with one end of the current source, and the other end of the current source is grounded; drain electrodes of the transistors M1-M2 are connected to form a positive output signal, and drain electrodes of the transistors M3-M4 are connected to form a negative output signal; the grid electrodes of the transistors M1-M2 are connected with a first capacitive coupling type level shifter, and the transistors M3-M4 are connected with a second capacitive coupling type level shifter; the on and off of the transistors M1-M4 are controlled through the two capacitance coupling type level shifters; the cross coupling unit is introduced to assist in transmitting switch control signals, and the dynamic performance of the digital-to-analog converter is improved.

The present invention relates a multi-shot time-to-digital converter and a time-measurement device. The multi-shot time-to-digital converter includes a time-to-digital conversion circuit and a timing control circuit. The timing control circuit is coupled to the time-to-digital conversion circuit and sending a start signal to the time-to-digital conversion circuit multiple times for measuring a time interval corresponding to the start signal. The time-to-digital conversion circuit obtains a fine phase time based on a plurality of clock signals to measure the time interval and provides a plurality of time-to-digital codes for digital processing. The clock signals have different phases. The time-to-digital codes are further processed to obtain the time-to-digital codes with better resolution.

Wireless circuitry may include a transmission line that carries a signal and a power detector that measures the signal. The detector may include a rectifier coupled to a comparator over a differential path. An offset calibrating digital-to-analog converter (OSDAC), a reference generator, and a multiplexer may be disposed on a negative line of the differential path. The OSDAC may produce an offset-compensated voltage by adding different offset voltages to a voltage on the second line over time. The reference generator may generate a set of threshold voltages by adding different reference voltages to the offset-compensated voltage. A temperature sensor may adjust the reference voltages used to generate the threshold voltages based on a temperature of the power detector. The multiplexer may route different threshold voltages to a negative input of the comparator.

Signal processing circuitry configured to receive an input signal and to output a processed output signal, wherein the signal processing circuitry is configured to: receive an indication of a temporal location of a transient in the input signal; and provide, in the processed output signal, a masking signal bridging the temporal location of the transient to mask the transient.

The present disclosure relates to the field of memory technologies and provides a data sampling circuit, comprising a first sampling module configured to respond to a signal from the data signal terminal and a signal from the reference signal terminal and to act on the first node and the second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on the third node and the fourth node; a latch module configured to input a high level to the first output terminal and input a low level to the second output terminal, or to input the low-level signal to the first output terminal and input the high-level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and an offset compensation module connected in parallel to the second sampling module and configured to compensate an offset voltage of the second sampling module. In this data sampling circuit, the second sampling module is additionally provided, and the offset compensation module is connected in parallel to the second sampling module, such that kickback noise is reduced.

The invention belongs to the technical field of photoelectric fusion integrated circuits, and particularly discloses a parallel PWM expansion high-precision programmable DAC structure. The adjusting module is used for adjusting the thermo-optical phase shifter according to the received digital control signal; the DAC structure specifically comprises a pulse width modulation signal generator and a current source array, wherein the pulse width modulation signal generator is used for acquiring a low-order code element from the digital control signal to generate a pulse width modulation signal, and sending the pulse width modulation signal to the current source array; wherein the current source array is used for acquiring a high-order code element from the digital control signal to generate a high-order analog signal; a low-order analog signal is generated based on the pulse width modulation signal; and the processor is also used for weighting and accumulating the low-order analog signal and the high-order analog signal to obtain an analog control signal and outputting the analog control signal. The DAC structure is high in precision and simple in structure.

This application relates to sensing of signals with a common-mode variation. Embodiments describe a switching driver circuit with a modulator configured to control modulation of an output node between different switching voltages and a current sensor configured to sense a voltage drop across a sense resistor connected in series with the output node. The current sensor performs sensing during a first time window that occurs at regular intervals and the modulator avoids any transition in switching voltage at the first output node during the first time window. Embodiments also describe a sensing circuit for sensing a differential voltage with a common-mode variation which has a first sensing portion implemented to provide a floating voltage domain and a second sensing portion implemented to provide a static voltage domain. At least one switched capacitor provides a boundary between the voltage domains and is switched to transfer charge between the voltage domains.

The invention discloses a DAC (Digital-to-Analog Converter) output voltage control method, system and equipment based on stepping delay and a medium. The method comprises the following steps: acquiring the current output voltage of the DAC as an initial voltage value; receiving a target voltage value and a set value of a target slope parameter; the target slope parameter comprises a target step length and a target delay; and controlling the initial voltage value to gradually change from the target slope to the target voltage value through the target slope parameter. The method is realized without depending on a hardware circuit, the DAC can change the output voltage according to the set slope parameter through a software implementation process, and the requirements on the DAC output voltage slope in different scenes can be met. According to the method, the target slope parameter and the target voltage value can be changed at any time in the DAC output voltage adjusting process, the DAC output voltage is controlled to be changed into the new target voltage value according to the new slope parameter, and no error exists in the software running process. The method is easy to modify and migrate and has high universality.

A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

In a microelectromechanical system (MEMS) sensor, movement of a component such as a proof mass due to a force of interest is sensed capacitively. A capacitance-to-voltage (C2V) converter receives a capacitance signal from the sensor and outputs a signal that includes an offset in addition to a signal of interest. The output signal is analyzed to identify the offset portion of the output signal and to modify values one or more variable capacitors coupled to the C2V input reduce the offset portion of the output signal.

The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a high-precision low-power-consumption dynamic comparator circuit suitable for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-precision low-power-consumption dynamic comparator circuit is designed by adopting two-stage pre-amplification and a latch structure, a first-stage pre-amplification circuit A1 is a gain amplification stage, and a second-stage pre-amplification circuit A2 is a gain amplification stage; the effects of simplifying the circuit structure, reducing power consumption and eliminating kickback noise are achieved by adopting a dynamic operational amplifier of a cross-coupled load, the second-stage pre-amplification circuit A2 serves as an extra gain stage, an output signal from the first-stage pre-amplification circuit A1 can be quickly amplified by adopting a cross-coupled load structure, and the kickback noise is eliminated. The third-stage latch circuit A3 improves the speed of the comparator, the latch adopts a dynamic structure and is controlled by a dynamic clock, the latch does not work during resetting, and the static power consumption of the comparator is reduced.

The present description provides for a method of controlling an analog-to-digital converter. In an example method, the most significant bits are determined by successive approximations. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of a first digital-to-analog converter with a third digital-to-analog converter and by applying a second ramp to the output of the second digital-to-analog converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first digital-to-analog converter and second digital-to-analog converter at the end of the successive approximations.

An analog-to-digital converting device includes a capacitive digital-to-analog converter, a comparator, and a controller. The capacitive digital-to-analog converter respectively generates a first and a second sample voltage according to a non-inverting output voltage and an inverting output voltage of a programmable gain amplifier during a sample period. The comparator generates a comparing signal by comparing the first and the second sample voltages during a converting period. The controller controls the capacitive digital-to-analog converter to generate a converting voltage according to the comparing signal during the converting period. The controller controls the capacitive digital-to-analog converter such that the capacitive digital-to-analog converter is pre-charged to a pre-charge voltage during a pre-charge period. The pre-charge voltage is between a maximum value and a minimum value of the non-inverting output voltage and the inverting output voltage of the programmable gain amplifier.

A calibration circuit has a delay loop, a counter and a latch. The delay loop that includes a delay circuit. The counter is clocked by edges in a clock signal generated by the delay loop when an enable signal is in a first signaling state. The latch is configured to capture a multibit output of the counter when the enable signal transitions to a second signaling state. A number of unit delay elements in the delay circuit are enabled based on the multibit output of the counter. In one example, the number of enabled unit delay elements is based on a difference between the multibit output of the counter and a multibit value expected to be generated when the delay circuit is operating nominally.

A comparator includes an input circuit that receives a first input signal and a second input signal, a first sense amplifying circuit that generates a first output signal and a second output signal by amplifying a potential difference between the first input signal and the second input signal, a first clocking transistor circuit that connects the input circuit to the first sense amplifying circuit based on a first clock signal, a second sense amplifying circuit that generates a third output signal and a fourth output signal by amplifying the potential difference between the first input signal and the second input signal, and a second clocking transistor circuit that connects the input circuit to the second sense amplifying circuit based on a second clock signal.

Methods and system for signal sampling using spatial dispersion are disclosed. In an example, a system includes a time-to-wavelength dispersion system configured to generate a wavelength dispersed optical pulse that is modulated according to an input signal, a wavelength-to-space dispersion system configured to spatially disperse the wavelength dispersed optical pulse by wavelength to produce a spatially dispersed optical pulse, a sensor system configured to convert the spatially dispersed optical pulse to electrical signals, the sensor system including a two-dimensional (2D) array of photodetectors, and a processor configured to decode the electrical signals to generate information about the input signal.

Apparatus and associated methods relate to a transformer-less way of demodulating signals generated by a synchro-resolver so as to determine a shaft angle of the synchro-resolver. A first differential output voltage between a first pair of the wye-configured secondary windings is used to generate a first output. A second differential output voltage between a second pair of the wye-configured secondary windings, different from the first pair, is used to generate a second output. The first and second outputs are combined to form a signal quadrature to the first output. The first output and the signal quadrature thereto are used to determine the shaft angle.

A bio-signal detection apparatus includes an analog front end unit includes a plurality of analog front end circuits that process a detected signal; an analog-to-digital conversion unit that converts an output signal of the analog front end unit to a digital code and a multiplexer (MUX) that outputs a processed signal by the analog front end circuits to the analog-to-digital conversion unit; wherein the analog digital conversion unit comprises: a comparator, a successive-approximate analog-to-digital converter (SAR ADC) that converts output signal of the analog front end circuit and form MSB side j-bit of the digital code, and a single slope ADC that converts the output signal of the analog front end circuit to k bit of the digital code.

The disclosure relates to circuitry, systems, and methods for digital-to-analog conversion. In various examples, a corresponding circuitry may comprise a first digital-to-analog conversion circuit to provide a first analog output signal and a second digital-to-analog conversion circuit to provide a second analog output signal. The circuitry may comprise addition circuitry to provide a combined analog output signal from the first analog output signal and the second analog output signal. A first voltage reference circuit, connected with the first digital-to-analog conversion circuit to provide a first reference voltage and a second voltage reference circuit, connected with the second digital-to-analog conversion circuit to provide a second reference voltage may be provided. The first reference voltage and the second reference voltage may differ from each other.

The invention discloses a digital-to-analog conversion circuit and a conversion method, and belongs to the field of circuit design. In order to solve the problems that the output amplitude of an existing digital-to-analog converter is fixed, and the resolution needs to be sacrificed or an additional circuit needs to be added during amplitude adjustment, the invention provides a novel circuit structure. On the basis that the circuit comprises a digital output module, a switch module and a weight circuit module, a high-level adjustable reference source and a low-level adjustable reference source are innovatively introduced. The switch module selectively connects the input node of the weight circuit module to the two adjustable reference sources according to the control signal of the digital output module. Therefore, the amplitude and the direct current bias of the output analog signal are directly determined by the voltage values of the two reference sources. According to the invention, the output signal range can be dynamically and flexibly adjusted on the premise that the resolution is not lost, and the bipolar signal can be conveniently generated, so that the system design is simplified, and the cost is reduced.

A system and method for correcting environmental phase drift between signal and reference branches of a photonic analog-digital converter (pADC) with passive remote sampler (PRS) sends a continuous-wave (CW) laser from a base unit through the PRS in a reverse optical path to measure the phase drift. The CW optical signal is converted to an electrical signal from which a phase-error signal indicative of the phase drift is filtered out and sent to a phase shifter. The pADC sends an optical pulse through the PRS in a forward optical path; the signal pulse is phase-modulated according to a received radio frequency (RF) signal of interest. The phase-modulated optical pulses (e.g., signal and reference) are received at the base unit and the phase drift corrected out of the optical pulses via the phase shifter. The corrected optical pulses are demodulated to provide a digital counterpart to the RF signal of interest.

A digital-to-time converter (DTC) of a fractional-n PLL contains a delay generator and a current-drawing block. The current drawn by the delay generator from the power supply contains: (A) a fixed component having a first current magnitude regardless of magnitude of a second code specifying the desired delay; and (B) a variable component having a magnitude determined only by magnitude of the second code. The current-drawing block draws correction-current from the power supply, whose magnitude is determined only by a complement of the second code.

The invention belongs to the technical field of gate voltage bootstrapped switches, and discloses a high-performance gate voltage bootstrapped switch for a Sigma-Delta ADC, a PMOS switch circuit is introduced into an NMOS type gate voltage bootstrapped switch circuit to form a complementary switch, and the complementary switch is used for counteracting an output error caused by a clock feed-through effect of an NMOS switch and the PMOS switch; virtual tubes are added to the input and output ends of the NMOS switch and the PMOS switch by using an inverter chain and are used for absorbing channel charges of the switch tubes; the substrate potential of the NMOS switch and the substrate potential of the PMOS switch are connected into the switching circuit, so that the substrate potential of the switching tube is switched between GND and input voltage Vin, and on the premise that sampling / maintaining precision is guaranteed, interference of clock feed-through and charge injection in the switching tube on output signals is restrained, and the linearity of the grid voltage bootstrapped switch is improved.