Current comparator usable in DC-DC converter applications

Abstract

A current comparator includes: a first capacitor having a first end coupled to a first input signal; a second capacitor having a first end coupled to a second input signal; a first transistor having a control electrode coupled to the second end of the first capacitor; and a third transistor having a control electrode coupled to the second end of the second capacitor. The first current electrodes of the first and second transistors are coupled, and the second current electrodes of the first and second transistors are coupled to the first and second circuit nodes, respectively. A single-ended cascode amplifier has an input coupled to the second circuit node via a third capacitor. A set of auto-zero switches selectively shorts the control electrode of the first transistor and the second current electrode in response to an auto-zero control signal, and selectively shorts the control electrode of the second transistor and the second current electrode.

Description

Technical Field

[0001] The present disclosure relates generally to integrated circuits and, more particularly, to current comparators that may be used in DC-DC converter applications. Background Art

[0002] Direct current (DC)-to-DC (DC) converters often need to sense the current in a power transistor to avoid exceeding a maximum current rating, or to sense when the inductor current crosses zero to support discontinuous conduction mode (DCM) operation. Therefore, there is a need for improved comparators that can sense such thresholds with improved accuracy while maintaining power conversion efficiency. Summary of the Invention

[0003] The following are various embodiments of the present invention. It should be noted that any of the following aspects can be used in any combination with each other and in combination with any disclosed embodiment.

[0004] In one embodiment, a current comparator includes: a first capacitor having a first terminal coupled to a first input signal; a second capacitor having a first terminal coupled to a second input signal; a first transistor having a first current electrode coupled to a first voltage supply terminal via a first current source, a control electrode coupled to a second terminal of the first capacitor, and a second current electrode coupled to a first circuit node; a second transistor having a first current electrode coupled to the first current electrode of the first transistor, a control electrode coupled to the second terminal of the second capacitor, and a second current electrode coupled to a second circuit node; a third transistor having a first current electrode coupled to the first circuit node, a second current electrode coupled to a second voltage supply terminal, and a second current electrode coupled to the first circuit node. a control electrode; a fourth transistor having a first current electrode coupled to the second circuit node, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to the second voltage supply terminal; a single-ended cascode amplifier having an input coupled to the second circuit node via a third capacitor, and an output; a logic stage coupled to receive the output of the single-ended cascode amplifier and configured to provide an output of the current comparator; and a set of auto-zero switches configured to selectively short the control electrode of the first transistor to the second current electrode of the first transistor and selectively short the control electrode of the second transistor to the second current electrode of the second transistor in response to an auto-zero control signal. In one aspect, the single-ended cascode amplifier includes: a fifth transistor having a control electrode configured as the input of the single-ended cascode amplifier, a first current electrode coupled to the second voltage supply, and a second current electrode; and a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode, and a second current electrode coupled to the output of the single-ended cascode amplifier, wherein the set of auto-zero switches is further configured to selectively short the control electrode of the fifth transistor to the second current electrode of the fifth transistor and selectively short the control electrode of the sixth transistor to the second current electrode of the sixth transistor in response to the auto-zero control signal. In another aspect, the control electrode of the sixth transistor is coupled to the second voltage supply via a fourth capacitor. In yet another aspect, the current comparator is configured to operate in an auto-zero phase and a subsequent comparison phase, wherein, during the auto-zero phase, the set of auto-zero switches is configured to short the control electrode of each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor to the second current electrode, and during the comparison phase, the set of auto-zero switches are each in a high impedance state.In yet another aspect, each of the first and second transistors is a PMOS transistor, and each of the third, fourth, fifth, and sixth transistors is an NMOS transistor. In an even further aspect, each of the set of auto-zero switches is implemented as an NMOS transistor. In another aspect of the embodiment, the current comparator is configured to operate in an auto-zero phase and a subsequent comparison phase, wherein during the auto-zero phase, the set of auto-zero switches is configured to short the control electrode of each of the first and second transistors to the second current electrode, and during the comparison phase, the set of auto-zero switches are each in a high impedance state.

[0005] In another aspect of the embodiment, a DC-DC converter includes the current comparator of the embodiment, and an input signal switch configured to provide auto-zero phase inputs as the first and second input signals of the current comparator during the auto-zero phase, and to provide comparison phase inputs as the first and second input signals of the current capacitor during the comparison phase. In another aspect of the DC-DC converter, the auto-zero phase inputs provided as the first and second input signals during the auto-zero phase are the same signal, and the comparison phase inputs provided as the first and second input signals during the comparison phase are a pair of signals that are compared to provide the output of the current comparator based on the comparison of the pair of signals. In another aspect of the DC-DC converter, the DC-DC converter further includes a power switch having a PMOS transistor connected in series with an NMOS transistor, wherein a first internal circuit node between the PMOS transistor and the NMOS transistor is configured to be coupled to an inductor. In another aspect of the DC-DC converter, during the auto-zero phase, the input signal switch couples a first ground signal to each of the first and second input signals of the current comparator, and during the comparison phase, the input signal switch couples a second internal circuit node of the power switch and a second ground signal to the first and second input signals of the current comparator, wherein the output of the current comparator indicates when the voltage on the second internal circuit node reaches the voltage of the second ground signal. In yet another aspect of the DC-DC converter, the DC-DC converter further includes control circuitry, wherein when the output of the current comparator is asserted to indicate that the voltage on the second internal circuit node has reached the voltage of the second ground signal, the control circuitry disables the NMOS transistor of the power switch. In yet another aspect, the power switch further includes an additional NMOS transistor coupled between the NMOS transistor of the power switch and a third voltage supply configured to provide the second ground signal, the second internal circuit node of the power switch corresponding to a node between the NMOS transistor of the power switch and the additional NMOS transistor, and the first ground signal is provided by one of the second voltage supply or the third voltage supply.In another aspect of the DC-DC converter, during the auto-zero phase, the input signal switch couples a supply voltage to each of the first and second input signals of the current comparator, and during the comparison phase, the input signal switch couples a voltage indicative of a predetermined maximum current through the internal circuit node of the inductor and the power switch to the first and second input signals of the current comparator, wherein the output of the current comparator indicates when the voltage on the internal circuit node reaches the voltage indicative of the predetermined maximum current. In another aspect, the DC-DC further includes a replica circuit configured to provide the voltage indicative of the predetermined maximum current to the input signal switch.

[0006] In another embodiment, a current comparator includes: a first capacitor having a first terminal coupled to a first input signal; a second capacitor having a first terminal coupled to a second input signal; a first transistor having a first current electrode coupled to a first voltage supply terminal via a first current source, a control electrode coupled to a second terminal of the first capacitor, and a second current electrode coupled to a first circuit node; a second transistor having a first current electrode coupled to the first current electrode of the first transistor, a control electrode coupled to the second terminal of the second capacitor, and a second current electrode coupled to a second circuit node; a third transistor having a first current electrode coupled to the first circuit node, a second current electrode coupled to a second voltage supply terminal, and a control electrode coupled to the first circuit node; a fourth transistor having a first current electrode coupled to the second circuit node, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to the second voltage supply terminal; and a single-ended cascode amplifier having an input coupled to the second circuit node via a third capacitor, and an output, wherein the current comparator is configured to operate in an auto-zero phase and a subsequent comparison phase, wherein during the auto-zero phase, the current comparator is configured to short the control electrode of each of the first transistor and the second transistor to the second current electrode, and during the comparison phase, the current comparator is configured not to short the control electrode of each of the first transistor and the second transistor to the second current electrode. In one aspect of the another embodiment, the current comparator further includes a logic stage coupled to receive the output of the single-ended cascode amplifier and configured to provide the output of the current comparator. In another aspect, the single-ended cascode amplifier includes: a fifth transistor having a control electrode configured as the input of the single-ended cascode amplifier, a first current electrode coupled to the second voltage supply terminal, and a second current electrode; and a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode, and a second current electrode coupled to the output of the single-ended cascode amplifier, wherein the current comparator is further configured to: during the auto-zero phase, short the control electrode of the fifth transistor to the second current electrode of the fifth transistor, and short the control electrode of the sixth transistor to the second current electrode of the sixth transistor, and during the comparison phase, not short the control electrode of each of the fifth and sixth transistors to the second current electrode.

[0007] In another aspect, a DC-DC converter includes the current comparator of the other embodiment, and a power switch having a PMOS transistor in series with an NMOS transistor, wherein an internal circuit node between the PMOS transistor and the NMOS transistor is configured to be coupled to an inductor, and wherein, during the auto-zero phase, a first ground signal is provided as each of the first and second input signals of the current comparator, and during the comparison phase, a second internal circuit node and a second ground signal of the power switch are provided to the first and second input signals of the current comparator, wherein the output of the current comparator indicates when the voltage on the second internal circuit node reaches the voltage of the second ground signal.

[0008] In another aspect, a DC-DC converter includes the current comparator of the other embodiment, and a power switch having a PMOS transistor in series with an NMOS transistor, wherein an internal circuit node between the PMOS transistor and the NMOS transistor is configured to be coupled to an inductor, and wherein, during the auto-zero phase, a supply voltage is provided as each of the first and second input signals of the current comparator, and during the comparison phase, a voltage indicative of a predetermined maximum current through the inductor and the internal circuit node is coupled to the first and second input signals of the current comparator, wherein the output of the current comparator indicates when the voltage on the internal circuit node reaches the voltage indicative of the predetermined maximum current. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like reference numerals indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0010] Figure 1 A DC-DC buck converter having an over-current (OC) comparator and a zero-crossing (ZC) comparator according to one embodiment of the present invention is shown.

[0011] Figure 2 It shows that the Figure 1 The OC comparator or the ZC comparator implements a current comparator responsive to an auto-zero (AZ) control signal.

[0012] Figure 3 An embodiment of the present invention is shown as follows Figure 2 The implementation shown can be Figure 1 The ZC comparator uses the front-end input signal to switch the current comparator.

[0013] Figure 4 and 5 FIG. 1 shows the operation of the AZ control signal during different operation phases according to one embodiment of the present invention. Figure 2 and 3 Current comparator.

[0014] Figure 6 An embodiment of the present invention is shown as follows Figure 2 The implementation shown can be Figure 1 The OC comparator uses the front-end input signal to switch the current comparator.

[0015] Figure 7 A schematic diagram of an embodiment of the present invention is shown in FIG. Figure 1 The power stage of the DC-DC step-down converter. DETAILED DESCRIPTION

[0016] In one aspect, a current comparator (also referred to as a threshold comparator) is provided that can implement a ZC comparator to indicate when the inductor current of a DC-DC converter crosses zero. In this way, DCM operation of the DC-DC converter can be supported. The current comparator can also implement an OC comparator to indicate when the inductor current exceeds the maximum current rating. The current comparator includes a first stage (i.e., a differential stage) having an input capacitor configured to store an offset and a power switch to implement auto-zeroing. The current comparator also includes a second stage comprising one or more single-ended cascode amplifiers in a cascade configuration, each having a DC blocking capacitor on the input and a capacitor for storing the gate bias voltage of the cascode transistor and an accompanying power switch to support auto-zeroing. The current comparator may also include an output logic scale to convert the analog output of the final single-ended cascode amplifier into a digital signal.

[0017] Figure 1A DC-DC converter 100 according to one embodiment of the present invention is shown in partial block diagram and partial schematic form, having an overcurrent (OC) comparator 116 (which may also be referred to as an OC detector or OC condition detector) and a zero-crossing (ZC) comparator 114 (which may also be referred to as a ZC detector or ZC condition detector). The DC-DC converter 100 is configured as a buck or step-down DC-DC converter, which reduces voltage while increasing current from its input (Vin) to its output (load). In the illustrated embodiment, the converter 100 is a switching converter having power switches 102 and 104, which are implemented as p-channel metal-oxide semiconductor (PMOS) transistors and n-channel metal-oxide semiconductor (NMOS) transistors, respectively. Compared to linear regulators (which typically do not step up output current), such switching converters generally provide greater power efficiency. (Note that in alternative embodiments, each power switch can be implemented with multiple transistors, where the power switches can collectively be referred to as the power stage of DC-DC converter 100.) In addition to the power stage (e.g., power switches 102 and 104), converter 100 also includes energy storage elements, inductor 110 and capacitor 112. In the illustrated embodiment, a first current electrode of PMOS transistor 102 is coupled to receive input voltage Vin, and a second current electrode is coupled to a first circuit node 124 at a first end of inductor 110. The voltage at circuit node 124 is labeled Vx (corresponding to the voltage at a first internal node of the power stage of converter 100). In one embodiment, Vin can be coupled to a first voltage supply terminal configured to provide a first supply voltage, Vdd. NMOS transistor 104 has a first current electrode coupled to circuit node 124 and a second current electrode of transistor 102, and has a second current electrode coupled to a second voltage supply terminal configured to supply a second supply voltage, Vss, where Vdd is greater than Vss. In one embodiment, Vss is ground, such as a local AC ground. It should be noted that, as used herein, the first and second voltage supply terminals may be referred to simply by the supply voltages provided by those terminals (e.g., Vdd and Vss, respectively). The second terminal of inductor 110 is coupled to the first terminal of capacitor 112 and provides the output voltage Vout of the converter, and the second terminal of capacitor 112 is coupled to Vss. The control electrode of transistor 102 is coupled to the output of first driver 106, and the control electrode of transistor 104 is coupled to the output of second driver 108.

[0018] In the illustrated embodiment, the inputs of driver 106 and driver 108 are each coupled to receive a digital input signal, such as a pulse width modulated (PWM) signal that controls transistors 102 and 104 (also referred to as switches or power switches) to be in an on state (where transistor 102 is on and transistor 104 is off) or an off state (where transistor 102 is off and transistor 104 is on). That is, the PWM signal causes transistors 102 and 104 to alternately switch on and off. It should be noted that in alternative embodiments, different digital signals can be used for drivers 106 and 108 to control the on and off states of each of transistors 106 and 108 and, therefore, the generation of Vx. In one embodiment, PWM can be provided by control circuitry 126. Alternatively, it can be provided by circuitry external to converter 100.

[0019] In continuous conduction mode (CCM) operation, the current through the inductor 110 (denoted by I L ) is controlled by power switches 102 and 104, as is known in the art, wherein Vx at node 124 forms a square wave between a high voltage and a low voltage, wherein the high voltage is between Vdd and the low voltage, and the low voltage is typically slightly lower than Vss (alternatively, it may be slightly lower than Vss before the converter allows I L For example, when in the on state (during the low phase of the PWM signal causing transistor 102 to be on but 104 to be off), Vx is at a high voltage, where I L As the inductor 110 charges, Vx increases, and when in the off state (during the high phase of the PWM signal causing transistors 102 to be off and 104 to be on), Vx is at a low voltage, where I L Decreases as inductor 110 discharges. In this way, Vout is provided as an average level of Vx between the high and low voltages of Vx, with the LC filter formed by inductor 110 and capacitor 112 operating to flatten Vout.

[0020] When in the on state, if the inductor 110 is saturated, then I L can increase to a level that exceeds the maximum current rating of the inductor (called I max If this occurs, the buck converter may not operate properly and could result in reliability issues for the buck converter or any load driven by the buck converter. Therefore, as will be described below, OC comparator 116 is coupled to circuit node 124 to monitor the current through transistor 102, which corresponds to I through inductor 110. L (Because transistor 104 is off during the on state). L Exceeding the maximum current Imax OC is asserted at the output of the OC comparator 116. OC may be provided to the control circuitry 126, which responds to the assertion of OC (i.e., responds to the OC indication I L The control circuit 126 may disable (ie, turn off) the transistor 102 as long as the OC condition exists. Figure 2 The OC comparator 116 is implemented using the current comparator described above.

[0021] When the converter 100 operates in continuous conduction mode, one of the two power switches is always on, so I L Always rising or falling. However, in some cases, it may be preferable to disable both power switches at some times. For example, if the power required by the load is very small, then in each cycle I L Operating in CCM, which swings between positive and negative currents, may be less efficient than operating in DCM. In DCM, the first transistor 102 turns on to increase I L , then transistor 102 is turned off and transistor 104 is turned on so that I L decreases, and when I L When it reaches zero, transistor 104 turns off, causing node Vx 124 to become high impedance (Z) and follow the voltage on Vout. L In DCM, the RMS current will be lower than in CCM and will often make the converter 100 more efficient. As a second example, the converter 100 may have optimal efficiency at a particular output current in CCM. If this optimal current exists, then when the load current is below the optimal current, the converter 100 may instead drive a current burst at the optimal output current and make I L It may be most efficient to idle at zero so that the converter's output current matches the current drawn by the load. In both examples, to avoid dissipating the energy stored in inductor 110, transistor 102 remains on until I L decreases to zero, and then when I L It is deactivated immediately when it reaches zero. Therefore, in either case, it is necessary to monitor I L To accurately determine I L When reaches zero. In one embodiment, ZC comparator 114 is coupled to node 124 to monitor I L And when I L ZC is asserted when ZC reaches zero. ZC may also be provided to the control circuitry 126, which responds to the assertion of ZC (ie, responds to the ZC indication I LThe zero-crossing condition of the transistor 104 is disabled (ie, turned off). The transistor 104 can therefore remain off until the next on state. Figure 2 The ZC comparator 114 is implemented using the current comparator described above.

[0022] Figure 2 A current comparator 200 according to one embodiment of the present invention is shown in partial block diagram and partial schematic form, and may be used to implement each of the ZC comparator 114 and the OC comparator 116. The comparator 200 includes a first input Vip and a second input Vin, wherein Vip and Vin are coupled as inputs to a differential stage (corresponding to Figure 2 Stage 1 of comparator 200. The differential stage of comparator 200 includes an input capacitor C0 202 (hereinafter referred to as C0) having a first end coupled to receive Vip and a second input capacitor C1 204 (hereinafter referred to as C1) having a first end coupled to receive Vin. The differential stage also includes a differential amplifier 260, wherein the second end of C0 is coupled to the non-inverting (+) input of differential amplifier 260 and the second end of C1 is coupled to the inverting (-) input of differential amplifier 260. Differential amplifier 260 includes a current source 206, PMOS transistors P0 208 and P1 210, and NMOS transistors N0 212 and N1 214. It should be noted that these PMOS and NMOS transistors may be referred to as P0, P1, N0, and N1, respectively. The differential amplifier 260 (implemented as a common source amplifier in the illustrated embodiment) further includes NMOS transistors 216 and 218, each having a control electrode coupled to receive an auto-zero (AZ) control signal (which may be referred to simply as AZ). The comparator 200 further includes a cascode amplifier 262 (corresponding to AZ) coupled to the output of the differential amplifier 260. Figure 2 2), and an inverter 234 having an input coupled to the output of the cascode amplifier 262 and an output coupled to provide an output Vo. In the embodiment shown, Vo is provided by the inverter 234 as a digital logic signal.

[0023] In differential amplifier 260, current source 206 is coupled between Vdd and circuit node 236. A first current electrode (e.g., source) of P0 is coupled to circuit node 236, a control electrode of P0 is coupled to the second terminal of C0, and a second current electrode (e.g., drain) of P0 is coupled to circuit node 238. A first current electrode (e.g., source) of P1 is coupled to node 236, a control electrode of P1 is coupled to the second terminal of C1, and a second current electrode (e.g., drain) of P1 is coupled to circuit node 242. A first current electrode (e.g., drain) of N0 and a control electrode of N0 are coupled to node 238, and a second current electrode (e.g., source) of N0 is coupled to Vss. A first current electrode (e.g., drain) of N1 is coupled to node 242, a control electrode of N1 is coupled to the control electrode of N0, and a second current electrode (e.g., source) of N1 is coupled to Vss.

[0024] The control switch of differential amplifier 260 (e.g., transistors 216 and 218) is coupled between the gate and drain of P0 and P1 to selectively short the gate to the drain based on the value of AZ. Transistor 216 has a first current electrode coupled to P0's control electrode at circuit node 240, a second current electrode coupled to P0's second current electrode (e.g., drain) at node 238, and a control electrode coupled to receive AZ. Transistor 218 has a first current electrode coupled to P1's control electrode at circuit node 244, a second current electrode coupled to P1's second current electrode at node 242, and a control electrode coupled to receive AZ. Thus, when AZ is asserted to a logic level one, the gates of P0 and P1 are each shorted to their respective drains. When AZ is negated to a logic level zero, transistors 216 and 218 are turned off, with the gates of P0 and P1 no longer shorted to their respective drains.

[0025] Cascode amplifier 262 includes a current source 232, capacitors 230 and 220, and NMOS transistors N2 222 and N3 224 (which may be referred to as N2 and N3, respectively). Cascode amplifier 262 also includes NMOS transistors 226 and 228, each having a control electrode coupled to receive AZ. Current source 232 is coupled between Vdd and circuit node 250, which corresponds to the output of cascode amplifier 262. A first current terminal (e.g., drain) of N3 is coupled to node 250, a control electrode of N3 is coupled to a first terminal of capacitor 230 at circuit node 246, and a second current electrode of N3 is coupled to circuit node 248. Capacitor 230 has a first terminal coupled to node 246 and a second terminal coupled to Vss. A first current electrode (e.g., drain) of N2 is coupled to a second current electrode of N3 at node 248, and a second current electrode (e.g., source) of N2 is coupled to Vss. A first end of capacitor 220 is coupled to node 242 (corresponding to the output of differential amplifier 260 ), and a second end of capacitor 220 is coupled to the control electrode of N2 .

[0026] The control switches of cascode amplifier 262 (e.g., transistors 226 and 228) are coupled between the gates and drains of N3 and N2 to selectively short the gates to the drains based on the value of AZ. Transistor 226 has a first current electrode coupled to the control electrode of N3 at circuit node 246, a second current electrode coupled to the first current electrode (e.g., drain) of N3 at node 250, and a control electrode coupled to receive AZ. Transistor 228 has a first current electrode coupled to the control electrode of N2 at circuit node 252, a second current electrode coupled to the first current electrode of N2 at node 248, and a control electrode coupled to receive AZ. Thus, when AZ is asserted to a logic level one, the gates of N3 and N2 are each shorted to their respective drains. When AZ is negated to a logic level zero, transistors 226 and 230 are turned off, with the gates of N3 and N2 no longer shorted to their respective drains.

[0027] Inverter 234 has an input coupled to node 250, which corresponds to the output of cascode amplifier 262. Inverter 234 has an output coupled to provide Vo. It should be noted that although shown as a single inverter, inverter 234 can be implemented in a series of inverters (e.g., a series of an odd number of inverters) to apply more gain and further digitize (e.g., sharpen) the signal at Vo. It should be noted that inverter 234 can also be referred to as a logic stage.

[0028] In operation, the control circuitry 126 controls AZ to operate in two phases Figure 2Comparator 200: an auto-zero phase (where AZ is asserted to a logic level one) and a comparison phase (where AZ is negated to a logic level zero). In one embodiment, as will be described below Figures 3 to 5 As described, the comparator 200 can be used in the ZC comparator 114, wherein when I L When Vo (corresponding to ZC) has dropped to zero, it is asserted. In another embodiment, as will be seen below Figure 6 As described, the comparator 200 can be used in the OC comparator 116, wherein when I L The maximum current I has been reached max (You can also Figure 6 The replica circuit 118 shown in FIG. 1 provides ) when Vo (corresponding to OC) is asserted.

[0029] Figure 3 A more detailed view of the ZC comparator 114 is shown in partial schematic and partial block diagram form, including a front-end input signal switch 300 and, for example, Figure 2 The comparator 200 includes input capacitors C0 302 and C1 304 (which are similar to C0 and C1 of comparator 200, respectively), a differential amplifier 360 (which can be Figure 2 stage 1) with a differential amplifier 260 implemented as a common-source common-gate amplifier 362 (which can be Figure 2 stage 2 of the differential amplifier 262 (implemented by the embodiment of FIG. 1 ), and the inverter 334 (which is similar to Figure 2 Inverter 234). Therefore, for Figure 2 The description provided for comparator 200 applies to Figure 3 The input signal switch 300 is coupled to provide appropriate inputs to Vip and Vin, respectively, for the auto-zero phase and the comparison phase. When AZ is asserted to a logic level one, indicating the auto-zero phase, switches 308 and 306 of the input switch 300 are set to their first positions to provide Vip_az to Vip and Vin_az to Vin, and when AZ is asserted to a logic level zero, indicating the comparison phase, switches 308 and 306 of the input switch 300 are set to their second positions to provide Vip_cmp to Vip and Vin_cmp to Vin. For the ZC comparator 114, each of Vip_az, Vin_az, and Vin_cmp is coupled to Vss, and Vip_cmp is coupled to Vx (at Figure 1 at node 124 of converter 100).

[0030] In operation, during the AZ phase of the ZC comparator 114, switches 308 and 306 are set to their first positions, where both Vin and Vip are coupled to Vss (which may be provided by the local AC ground). Figure 3 Vo can be expressed as "Vo = A[(Vip_cmp - Vin_cmp) - (Vip_az - Vin_az)]" when operating with respect to the two phases, where A refers to the gain of the comparator and is typically large enough so that Vo will saturate under its positive or negative supply. In the case of the ZC comparator 114, in addition to any offset naturally present in the circuit, during the auto-zero phase, Vip_az = Vin_az, which causes these terms to drop out of the equation. Figure 2 The elements of the comparator 200 describe the operation of the ZC comparator 114 .

[0031] During the auto-zero phase (where AZ=1), switches 216, 218, 226, and 230 (also referred to as auto-zero switches) are all turned on, shorting the corresponding gates and drains. Figure 2 The resulting circuit of the comparator 200 components is Figure 4 As shown in Figure 4 As shown in FIG, the gate of P0 is shorted to node 238 and the gate of P1 is shorted to node 242. With Vin and Vip each coupled to ground, the voltage on C0 (V(C0)) can be expressed as V(C0)=V TN0 , where V TN0 is the threshold voltage (Vt) of N0 (ie, the voltage at node 238). Similarly, the voltage across C1 (V(C1)) can be expressed as V(C1)=V TN0 +V TP0 -V TP1 , where V TP0 and V TP1 The offset between C0 and C1 can be expressed as V(C0)-V(C1)=V TP1 -V TP0 (Because V TN0 cancel each other), and the natural offset of the amplifier is V TP0 -V TP1 In the cascode amplifier 262, as Figure 4 As shown, the gate of N3 is shorted to node 250 , and the gate of N2 is shorted to node 248 .

[0032] The offset between C0 and C1 is stored on capacitors C0 and C1 at the input of stage 1, and capacitor 220 acts as a DC block to keep stage 2 biased in a high gain state. Capacitor 230 also serves a similar purpose to maintain the bias conditions established during the auto-zero phase. It should be noted that during the auto-zero phase, the voltage at node 250 can be expressed as "V TN2 +V TN3 ”(V TN2 and VTN3 The voltage at node 250 (approximately two Vt) is close to the switching threshold of inverter 234. That is, the capacitor of comparator 200 operates to store a voltage at the input of inverter 234 that is close to its switching threshold. This allows for improved accuracy when receiving smaller input voltages or input voltages with smaller voltage differences therebetween by eliminating any offset in the amplifier.

[0033] During the comparison phase (where AZ=0), switches 216, 218, 226, and 230 are open and therefore placed in a high-Z state. Figure 2 The resulting circuit of the comparator 200 components is Figure 5 During the comparison phase, stage 1 behaves as a differential amplifier and stage 2 behaves as a single-ended cascode amplifier. Figure 2 (where switches 308 and 306 are set to their second positions for the comparison phase), the "+" input to differential amplifier 360 is labeled Vip_ac, where Vip_ac = Vx + V(C0), and the "-" input is labeled Vin_ac, where Vin_ac = 0 + V(C1). In this case, Vip_ac - Vin_ac = Vx + V(C0) - V(C1). Thus, it can be seen that the offset in the comparison phase (V(C0) - V(C1)) is canceled by the offset stored in the auto-zero phase. Also, with the input to inverter 234 set close to its switching threshold in the auto-zero phase, the zero crossing (ZC) to Vx can be quickly and accurately detected (resulting in ZC being asserted to a logic level one).

[0034] As noted above, a comparator such as comparator 200 may also be used in OC comparator 116. Thus, Figure 6 A more detailed view of the OC comparator 116 is shown in partial schematic and partial block diagram form, comprising a front-end input signal switch 600 (similar to the input signal switch 300) and, for example, Figure 2 The comparator 200 includes input capacitors C0 602 and C1 604 (which are similar to C0 and C1 of comparator 200, respectively), a differential amplifier 660 (which can be Figure 2 stage 1) with a common-source common-gate amplifier 662 (which can be implemented as a differential amplifier 260) Figure 2 stage 2 of the differential amplifier 262 (implemented by the embodiment of FIG. 1 ), and the inverter 634 (which is similar to Figure 2 Inverter 234). Therefore, for Figure 2 The description provided for comparator 200 also applies to Figure 6The input signal switch 600 is coupled to provide appropriate inputs to Vip and Vin, respectively, for the auto-zero phase and the comparison phase. When AZ is asserted to a logic level one, indicating the auto-zero phase, switches 608 and 606 of the input switch 600 are set to their first positions to provide Vip_az to Vip and Vin_az to Vin, and when AZ is asserted to a logic level zero, indicating the comparison phase, switches 608 and 606 of the input switch 600 are set to their second positions to provide Vip_cmp to Vip and Vin_cmp to Vin. For the OC comparator 116, each of Vip_az and Vin_az is coupled to Vdd, and Vin_cmp is coupled to receive VR Imax (which corresponds to the voltage input from a reference circuit that generates a maximum current I for the current rating of the inductor 110 max ), and Vin_cmp is coupled to Vx( Figure 1 Node 124 of converter 100).

[0035] Return Reference Figure 1 It should be noted that replica circuit 118 (expected to be replica transistor 102 and Vx) includes a PMOS transistor 120 having a first current electrode coupled to Vdd, a control electrode coupled to Vss, and a second current electrode coupled to a first terminal of a current source 122. A second terminal of current source 122 is coupled to Vss. Current source 122 can be set to, for example, I max / M, where M represents the size of transistor 102 relative to transistor 120. The second current electrode of transistor 120 drives the voltage VR Imax is provided to the OC comparator 116. In the embodiment shown, it should be noted that because transistor 120 is a scaled replica of transistor 102, when I L Reach I max When VR Imax The voltage at I will be equal to Vx, so this comparison can be used to detect an OC condition (similar to how the comparison between zero and Vx can be used to detect a ZC condition). It should be noted that alternative embodiments may use other types of circuitry, such as other replica circuits, to compare I max An indication of OC is provided to the OC comparator 116 .

[0036] Therefore, during the auto-zero phase of the OC comparator 116, instead of setting both Vin and Vip to Vss, both are set to Vdd. However, since Vip_az=Vin_az in this case as well, these terms also drop out of the equation. In the case where AZ=1 during the auto-zero phase (where switches 606 and 608 are in their first positions), the comparator 200 is as described above with respect to Figure 4 In the described configuration (where the auto-zero switches are all on), this results in the offset V(C0)-V(C1) being stored again at the input capacitors C1 and C0. In the case of AZ=0 during the comparison phase (where switches 606 and 608 are in their second positions), the comparator 200 is as described above with respect to Figure 5 The configuration described (where the auto-zero switch is open). However, in this case, instead of comparing Vx (Vip=Vx) to 0 (Vin=0) to determine the ZC condition, VR is compared. Imax (Vip=VR Imax ) and Vx (Vin=Vx) to determine the OC condition.

[0037] It should be noted that the above description with respect to the operation of the comparator 200 when used in the ZC comparator 114 is not specific to the embodiment of the present invention. Figure 4 and 5 The description provided is similar to the operation of comparator 200 when used in OC comparator 116. Converter 100 may include ZC comparator 114 or OC comparator 116 or may include both (e.g., Figure 1 In the illustrated embodiment of FIG. 1 , in embodiments where converter 100 includes both a ZC comparator and an OC comparator, two different instances of current comparator 200 are required, one for the ZC comparator and one for the OC comparator. Each of the outputs ZC and OC is provided to control circuitry 126 so that control circuitry 126 can disable transistor 104 in response to the occurrence of a ZC condition (i.e., in response to assertion of ZC) and can disable transistor 102 in response to the occurrence of an OC condition (i.e., in response to assertion of OC). It should be noted that comparator 200 can also be used in other embodiments, such as in different types of DC-DC converters.

[0038] about Figure 2 It should be noted that the use of the comparator 200 can reduce or overcome the Miller effect. As is known in the art, the Miller effect refers to the increase in the equivalent input capacitance of an inverting voltage amplifier due to the amplification of the capacitance effect between the input and output terminals. For example, for an inverting amplifier, Vout = -Av*Vin, where -Av is the voltage gain of the inverting amplifier and the feedback capacitance (C) exists between Vin and Vout. However, the increased input capacitance due to the Miller effect can be expressed as C M=C(1+Av). However, with the use of comparator 200, the large virtual capacitance that would appear at the input to differential amplifier 260 due to the Miller effect can be mitigated or overcome. For example, since the inputs of the first stage (Vin and Vip) are coupled to low impedance power switches (e.g., transistors 102 and 104), a faster RC time constant can be achieved, thereby reducing C M And, by having a lower voltage gain, the M In comparator 200, cascode amplifier 262 of stage 2 helps achieve a lower voltage gain for the comparator from node 252 to node 248, thereby mitigating the Miller effect.

[0039] For example, refer to Figure 1 For comparator 200, assuming complete offset cancellation at input capacitors 202 and 204, if (Vin>Vip) is initially applied, the output of stage 1 (at node 242) will initially be low, the output of stage 2 will initially be high, and Vo will initially be low. In this configuration, the transistors of stage 2 remain saturated, and thus amplifier 262 behaves as a cascode amplifier (reducing the Miller effect), with the current for the falling edge set by the transconductance of the common-source transistors. On the other hand, if (Vip>Vin) is initially applied, the output of stage 2 (at node 250) will be low, the pull-up current will be limited by the bias current, and the amplifier transistors will be in triode mode, which increases their channel capacitance, so the circuit will respond significantly more slowly.

[0040] Unlike other auto-zero comparators in analog-to-digital converters (ADCs), an auto-zero comparator in a DC-DC converter for current sensing thresholds will naturally have its input steer in one regulated direction in each cycle. For example, in a high-side PMOS power switch (e.g., transistor 102) in a buck converter, the inductor current I L The voltage at the drain (e.g., Vx) will increase, and the drain voltage (e.g., Vx) will gradually become lower than the supply voltage. Similarly, for the low-side NMOS power switch (e.g., transistor 104) in a buck converter, the drain voltage (e.g., Vx) will consistently become more positive. Because the direction of the input voltage turn is predetermined, the converter circuit can be optimized for its response time to a given input turn.

[0041] Also, it should be noted that comparator 200 performs an early conversion from differential to single-ended signals (via differential amplifier 260, before stage 2). This allows the bias current of some stages to be reduced (e.g., halved) compared to other comparator designs where more stages are each kept fully differential. It should also be noted that, due to issues with single-ended first stages caused by variations in ground potential, having at least stage 1 receive differential inputs allows for a lower voltage converter than using a single-ended stage 1.

[0042] In an alternative embodiment, comparator 200 can instead use an NMOS differential pair instead of P0 and P1. Also, additional gain stages other than those shown (e.g., in addition to cascode amplifier 262) can be used. However, if so, they should alternate between NMOS and PMOS cascode amplifiers to achieve the desired high-speed operation. Also, in an alternative embodiment, the auto-zero switches (e.g., switches 216, 218, 226, and 230) can instead be implemented as PMOS switches, or can be implemented using different combinations of circuit systems. Alternative embodiments can also use power switch topologies different from the single transistor switches shown for switches 104 and 102 and the corresponding simple replica switch 120. For example, Figure 7 An embodiment of a power stage of a converter 100 is shown that implements the low-side switch as two NMOS transistors connected in series between a PMOS transistor 102 and a second voltage supply (e.g., transistor 104 connected in series with an NMOS transistor 702). In this example, the front-end input signal switches 300 and 600 can instead be coupled to the second internal node 704 of the power stage located between the two series-connected NMOS transistors 104 and 702 for use during the comparison phase of the ZC 114 or OC 116, rather than directly using the first internal node Vx. It should also be noted that different switch topologies can be used to implement the functionality of the front-end input signal switches (e.g., switches 300 and 600). For example, multiple switches or devices can be used to implement each of the input switches (e.g., 308, 306, 608, 606). Also, while inverter 234 forms the output inverter for comparator 200, as described above, inverter 234 (also referred to as logic stage 234) may be implemented in a variety of different ways, such as including more than one inverter or using more complex logic circuits, such as having NAND or NOR gates, or other combinations of gates, to block leakage current during the auto-zero phase or to give a defined state when disabled.

[0043] It should be noted that the DC-DC comparator 100 can be implemented using a split ground, where different voltage supplies (e.g., grounds) can be used to provide ground voltages for different parts of the DC-DC comparator 100 (where, in one embodiment, the grounds can be connected or shorted to each other at a printed circuit board (PCB). In one embodiment, the second voltage supply (e.g., ground) configured to provide Vss (e.g., a ground signal) to the power stage can be a different ground for the ZC comparator 114 or the OC comparator 116. For example, the ground for the comparator can be a third voltage supply configured to provide a second ground signal, but this second ground signal can be different from the ground signal provided to the power stage by the second voltage supply. That is, the supplied Vss voltage can be different between the power stage and the comparator (but all still less than Vdd). In addition, depending on the embodiment, different ground signals can be used for the AZ phase relative to the comparison phase for each comparator. For example, in ZC comparator 114, front-end switch 300 can connect the third voltage supply to the Vip and Vin inputs of stage 1, but connect the second voltage supply to the Vin input for the comparison phase. Similarly, it should be noted that different voltage supplies can be used to provide supply voltages for different parts of DC-DC comparator 100. For example, the fourth voltage supply can be used to provide Vdd to ZC comparator 114 or OC comparator 116, where this Vdd can be lower than the Vdd provided by the first voltage supply to the power stage. For example, the Vdd for the power stage can be 3.3V, while the Vdd for the comparator can be 1.8V. This can help protect lower-voltage devices within the comparator. It should also be noted that for the OC comparator 116, since it is preferred that the Vdd used as input during the AZ phase is similar to the Vdd used during the comparison phase, even if the Vdd used for the comparator is lower compared to the power stage (e.g., 1.8V instead of 3.3V), the Vdd used as input during the AZ phase and the Vdd used during the comparison phase can all be the Vdd applied to the power stage (e.g., the higher 3.3V).

[0044] Thus, it can now be appreciated that a current comparator configuration has been provided that can be used in various threshold current comparators, such as a ZC comparator or an OC comparator. In one embodiment, the current comparator includes a first stage having a differential amplifier and a second stage having a cascode amplifier, and the current comparator operates in an auto-zero phase and a subsequent comparison phase. During the auto-zero phase, an auto-zero switch is used to connect the gates and drains of various transistors in each of the first and second stages to store an offset in an input capacitor during the auto-zero phase. During the comparison phase, the auto-zero switch is opened to allow the differential amplifier and the cascode amplifier to operate normally. The initially stored offset cancels out the offset during the comparison phase, which compares the first input voltage to the second input voltage. The output of the comparator indicates when the first input voltage has reached the second input voltage. This current comparator can be used, for example, as a ZC comparator or an OC comparator in a DC-DC buck converter. For example, for a ZC comparator in a buck converter, the output of the current comparator indicates when Vx (representing the current through the buck converter's inductor) at the first input voltage has reached zero at the second input voltage. For an OC comparator in a buck converter, the output of the current comparator indicates when Vx at the first input voltage has reached zero at the second input voltage. RImax (a voltage representing the maximum current allowed through the inductor) when Vx at the second input voltage has been reached.

[0045] The terms "assertion" or "setting" and "negation" (or "de-assertion" or "clearing") are used herein in reference to causing a signal, status bit, or the like to assume its logically true or logically false state, respectively. If the logically true state is a logic level one, then the logically false state is a logic level zero. And if the logically true state is a logic level zero, then the logically false state is a logic level one.

[0046] Each signal described herein can be designed as either positive logic or negative logic, where negative logic can be indicated by a dash on the signal name or an asterisk (*) after the name. In the case of a negative logic signal, the signal is active low, where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high, where the logically true state corresponds to a logic level one. It should be noted that any signal described herein can be designed as either a negative logic signal or a positive logic signal. Therefore, in alternative embodiments, those signals described as positive logic signals can be implemented as negative logic signals, and those signals described as negative logic signals can be implemented as positive logic signals.

[0047] Since the devices implementing the present invention are largely composed of electronic components and circuits known to those skilled in the art, in order to understand and appreciate the basic concepts of the present invention and in order not to confuse or deviate from the teachings of the present invention, the circuit details will not be set forth in any greater degree than is deemed necessary in the above illustrations.

[0048] Although the present invention has been described with respect to a particular conductivity type or polarity of potential, one skilled in the art will appreciate that the conductivity type or polarity of potential can be reversed.

[0049] Where appropriate, some of the above embodiments may be implemented using a variety of different applications. For example, although Figure 1 The present invention and its discussion describe exemplary configurations of DC-DC converters, but such exemplary configurations are presented only to provide useful references when discussing various aspects of the present invention. Therefore, for the purposes of discussion, the description of the architecture has been simplified, and it is only one of many different types of converters and configurations that can be used according to the present invention. Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative, and alternative embodiments may merge logic blocks or circuit elements, or impose alternative decompositions of functionality on various logic blocks or circuit elements. Therefore, it should be understood that the configurations depicted herein are merely exemplary, and in fact, many other configurations that achieve the same functionality may be implemented.

[0050] Also, for example, in one embodiment, the illustrated components of converter 10 are circuitry located on a single integrated circuit or within the same device, where, for example, converter 10 may be implemented in a system on a chip (SoC). Alternatively, converter 10 may be used in a system including any number of separate integrated circuits or separate devices interconnected with one another.

[0051] Furthermore, those skilled in the art will recognize that the boundaries between the functionality of the operations described above are merely illustrative. The functionality of multiple operations may be combined into a single operation, and / or the functionality of a single operation may be distributed among other operations. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of the operations may vary in various other embodiments.

[0052] Although the present invention is described herein with reference to specific embodiments, various modifications and variations may be made without departing from the scope of the invention as set forth in the appended claims. For example, the current comparator can be used in other applications, such as other types of threshold comparators or other types of DC-DC converters. Therefore, the description and drawings should be regarded as illustrative and not restrictive, and all such modifications are intended to be included within the scope of the present invention. It is not intended that any benefit, advantage, or solution to the problem described herein with respect to a specific embodiment be understood as a key, essential, or requisite feature or element of any or all claims.

[0053] As used herein, the term "coupled" is not intended to be limited to a direct coupling or a mechanical coupling.

[0054] In addition, as used herein, the terms "a" and "an" are defined as one or more than one. Moreover, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted as implying that another claim element introduced by the indefinite article "a" limits any particular claim containing the introduced claim element to inventions containing only one of the element, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a". The same applies to the use of definite articles.

[0055] Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements these terms describe. Therefore, these terms are not necessarily intended to indicate a temporal or other prioritization of such elements.

Claims

1. A current comparator, characterized in that: include: a first capacitor having a first terminal coupled to a first input signal; a second capacitor having a first terminal coupled to a second input signal; a first transistor having a first current electrode coupled to a first voltage supply terminal via a first current source, a control electrode coupled to a second terminal of the first capacitor, and a second current electrode coupled to a first circuit node; a second transistor having a first current electrode coupled to the first current electrode of the first transistor, a control electrode coupled to the second end of the second capacitor, and a second current electrode coupled to a second circuit node; a third transistor having a first current electrode coupled to the first circuit node, a second current electrode coupled to a second voltage supply, and a control electrode coupled to the first circuit node; a fourth transistor having a first current electrode coupled to the second circuit node, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to the second voltage supply; a single-ended cascode amplifier having an input coupled to the second circuit node via a third capacitor, and an output; a logic stage coupled to receive the output of the single-ended cascode amplifier and configured to provide an output of the current comparator; as well as A set of auto-zero switches is configured to selectively short the control electrode of the first transistor to the second current electrode of the first transistor and selectively short the control electrode of the second transistor to the second current electrode of the second transistor in response to an auto-zero control signal.

2. The current comparator according to claim 1, wherein: The current comparator is configured to operate in an auto-zero phase and a subsequent comparison phase, wherein during the auto-zero phase, the set of auto-zero switches is configured to short the control electrode of each of the first transistor and the second transistor to the second current electrode, and during the comparison phase, the set of auto-zero switches are each in a high impedance state.

3. A DC-DC converter, characterized in that: include: The current comparator according to claim 1; An input signal switch is configured to provide auto-zero phase inputs as the first input signal and the second input signal of the current comparator during the auto-zero phase, and to provide comparison phase inputs as the first input signal and the second input signal of the current capacitor during the comparison phase.

4. The DC-DC converter according to claim 3, wherein: Further including: A power switch has a PMOS transistor in series with an NMOS transistor, wherein a first internal circuit node between the PMOS transistor and the NMOS transistor is configured to be coupled to an inductor.

5. The DC-DC converter according to claim 4, wherein: During the auto-zero phase, the input signal switch couples a first ground signal to each of the first input signal and the second input signal of the current comparator, and During the comparison phase, the input signal switch couples a second internal circuit node of the power switch and a second ground signal to the first input signal and the second input signal of the current comparator, wherein the output of the current comparator indicates when the voltage on the second internal circuit node reaches the voltage of the second ground signal.

6. The DC-DC converter according to claim 4, wherein: During the auto-zero phase, the input signal switch couples a supply voltage to each of the first and second input signals of the current comparator, and During the comparison phase, the input signal switch couples a voltage indicative of a predetermined maximum current through the internal circuit node of the inductor and the power switch to the first and second input signals of the current comparator, wherein the output of the current comparator indicates when the voltage on the internal circuit node reaches the voltage indicative of the predetermined maximum current.

7. A current comparator, characterized in that: include: a first capacitor having a first terminal coupled to a first input signal; a second capacitor having a first terminal coupled to a second input signal; a first transistor having a first current electrode coupled to a first voltage supply terminal via a first current source, a control electrode coupled to a second terminal of the first capacitor, and a second current electrode coupled to a first circuit node; a second transistor having a first current electrode coupled to the first current electrode of the first transistor, a control electrode coupled to the second end of the second capacitor, and a second current electrode coupled to a second circuit node; a third transistor having a first current electrode coupled to the first circuit node, a second current electrode coupled to a second voltage supply, and a control electrode coupled to the first circuit node; a fourth transistor having a first current electrode coupled to the second circuit node, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to the second voltage supply; as well as a single-ended cascode amplifier having an input coupled to the second circuit node via a third capacitor, and an output, wherein the current comparator is configured to operate in an auto-zero phase and a subsequent comparison phase, wherein, during the auto-zero phase, the current comparator is configured to short the control electrode of each of the first transistor and the second transistor to the second current electrode, and during the comparison phase, the current comparator is configured not to short the control electrode of each of the first transistor and the second transistor to the second current electrode.

8. The current comparator according to claim 7, wherein: The single-ended cascode amplifier comprises: a fifth transistor having a control electrode configured as the input of the single-ended cascode amplifier, a first current electrode coupled to the second voltage supply terminal, and a second current electrode; and a sixth transistor having a first current electrode coupled to the second current electrode of the fifth transistor, a control electrode, and a second current electrode coupled to the output of the single-ended cascode amplifier, The current comparator is further configured to: During the auto-zero phase, the control electrode of the fifth transistor is shorted to the second current electrode of the fifth transistor, and the control electrode of the sixth transistor is shorted to the second current electrode of the sixth transistor, and During the comparison phase, the control electrode of each of the fifth transistor and the sixth transistor is not shorted to the second current electrode.

9. A DC-DC converter, characterized in that: include: The current comparator according to claim 7; a power switch having a PMOS transistor in series with an NMOS transistor, wherein an internal circuit node between the PMOS transistor and the NMOS transistor is configured to be coupled to an inductor, in: providing a first ground signal as each of the first input signal and the second input signal of the current comparator during the auto-zero phase, and During the comparison phase, a second internal circuit node of the power switch and a second ground signal are provided to the first and second input signals of the current comparator, wherein the output of the current comparator indicates when the voltage on the second internal circuit node reaches the voltage of the second ground signal.

10. A DC-DC converter, characterized in that: include: The current comparator according to claim 7; a power switch having a PMOS transistor in series with an NMOS transistor, wherein an internal circuit node between the PMOS transistor and the NMOS transistor is configured to be coupled to an inductor, in: providing a supply voltage as each of the first and second input signals of the current comparator during the auto-zero phase, and During the comparison phase, a voltage indicative of a predetermined maximum current through the inductor and the internal circuit node is coupled to the first and second input signals of the current comparator, wherein the output of the current comparator indicates when the voltage on the internal circuit node reaches the voltage indicative of the predetermined maximum current.

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