2770results about "Electric signal transmission systems" patented technology

The invention discloses an electronic jacquard machine control method and system based on multi-channel collaboration, and the method comprises the steps: calculating a delay compensation value of each channel in real time according to the hardware performance difference and signal transmission delay data of each channel, and dynamically adjusting the time sequence offset of a control instruction of an electronic jacquard machine by using the delay compensation value, generating a multi-channel cooperative control signal; according to input fabric pattern data, decomposing the fabric pattern data to generate a layered instruction set, and binding the layered instruction set to a multi-channel cooperative control signal to form a time-space synchronization instruction set; according to channel operation state data acquired in real time, identifying an abnormal channel and a fault type thereof, and generating a reconstruction instruction set after fault immunization; and dynamically allocating computing resources and storage bandwidth according to the reconstruction instruction set, generating an optimization execution instruction set, and issuing the optimization execution instruction set to each channel for execution in real time. By utilizing the embodiment of the invention, the control capability of the electronic jacquard machine and the fabric production efficiency can be improved, and the intelligent development of the textile industry is promoted.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

The invention relates to a high-precision temperature sensor based on complementary dynamic element matching and a zoom analog-to-digital converter and a working method, and belongs to the technical field of sensor improvement, and the sensor comprises an analog front end, an analog-to-digital converter, a digital rear end and a control logic. An improved chopping technology is adopted, and one clock signal is adopted to control two sub operational amplifiers, so that the output stability and precision of the analog front end are improved. A complementary dynamic element matching technology is utilized, errors caused by voltage drop at the two ends of a switch are reduced, the influence of channel charge injection is counteracted, a scaling type analog-to-digital converter design is provided for an analog-to-digital conversion part, and balance among power consumption, speed and precision is achieved. According to the method, a 10-bit successive approximation register analog-to-digital converter is used for measuring a numerical value and a change trend, and the numerical value and the change trend are analyzed, so that the expression effects of a current mirror structure, a transistor, a filter and the like are evaluated, the aging of the transistor is found in advance, and a clear direction is provided for future design improvement.

The invention discloses a multi-channel analog-to-digital converter for multi-channel frequency division multiplexing and a conversion circuit and method thereof, and the frequency division multiplexing multi-channel analog-to-digital conversion circuit comprises an analog frequency conversion module which is used for receiving N paths of modulation clock signals, and generating N paths of modulation clock signals according to the modulation clock signals, n paths of input signals are modulated to preset frequencies of the input signals respectively, and N paths of modulation signals are obtained; wherein N is greater than or equal to 2, and N is a positive integer; the frequency bands where the N paths of modulation signals are located are not overlapped; the analog adder is used for combining the N paths of modulation signals to obtain one path of analog signal; the input end of the analog-digital conversion module is connected with the analog-digital conversion module; the digital logic control module is used for receiving the N paths of modulation clock signals and separating the digital signals into N paths of digital signals which are output in parallel. Multi-channel analog-to-digital conversion can be realized by adopting one analog-to-digital converter, the hardware volume, cost and power consumption can be reduced, and the analog-to-digital conversion rate and precision can be improved.

A method of operating a time-interleaved analog-to-digital converter (TIADC). The TIADC converts an input signal to generate a digital output signal and includes multiple asynchronous sub-ADCs. The asynchronous sub-ADCs each convert the input signal at a different time point to generate a digital output code, and each of the asynchronous sub-ADCs generates a completion signal upon completion of an analog-to-digital conversion operation. The method includes the following steps: generating an indication signal according to the completion signals, wherein the indication signal indicates multiple candidate sub-ADCs; selecting one of the candidate sub-ADCs as a target sub-ADC according to the indication signal; and correcting the digital output code of the target sub-ADC to generate the digital output signal.

The various implementations described herein include techniques and apparatuses for multi-channel biopotential signal acquisition, biopotential signal pre-processing, and adaptive signal conditioning. In one aspect, an analog frontend circuit includes an instrumentation amplifier (INA) and an analog-to-digital circuit (ADC) in a forward signal path. A digital circuit receives input from the ADC. An adaptive baseline tracking and compensation circuit tracks and compensates moving motion artifact driven changes. A power line interference (PLI) detection and compensation circuit tracks a desired number of PLI harmonics, and magnitude, phase and frequency for the PLI harmonics in real time. A digital-to-analog converter (DAC) circuit combines output of the adaptive baseline tracking and compensation circuit and the PLI detection and compensation circuit to output an analog output. A passive filter receives the analog output and drives an analog compensation signal at an input of the INA.

The invention discloses a PUF (Physical Unclonable Function) structure based on delay difference quantization, and the structure comprises a PUF circuit which comprises two time delay circuits which are connected in parallel; a plurality of layers of differential tapped circuits TDC, and decoders connected with each layer of differential tapped circuit TDC; the delay data quantization unit is connected with the multi-layer decoder, and the delay data quantization unit is connected with the LFSR confusion structure; the two delay circuits are connected with the multi-layer differential tap circuit TDC through the signal selection structure, the signal selection structure inputs delay signals which respond first and then respond in the two delay circuits into a start end and a stop end of each layer of differential tap circuit TDC, the decoder determines delay time of the two delay circuits under corresponding delay resolution, and the decoder outputs the delay time to the multi-layer differential tap circuit TDC. The delay data quantization unit is used for averaging the delay time under different time delay resolutions to serve as final delay data, and the final response R is output after the final delay data is confused by the LFSR confusion structure. Signals of the two symmetrical delay paths are respectively input into a framework of a multi-layer TDC quantization circuit, so that delay difference digital code quantization is realized.

A high-linearity grid voltage bootstrap circuit relates to the technical field of analog-to-digital conversion and comprises a first charge pump boosting unit, a second charge pump boosting unit and a grid voltage bootstrap unit, working states of a sampling switch are divided into a sampling state and a holding state, an input voltage VIN is boosted to a VG through the grid voltage bootstrap unit in a sampling stage, and the sampling switch is switched on; and the holding stage sampling switch is cut off, and charges are injected to the upper polar plates of the capacitors C3 and C4 of the gate voltage bootstrap unit through the first charge pump boosting unit and the second charge pump boosting unit respectively. According to the invention, the problem that the actual gate-source voltage is reduced due to the grid parasitic capacitance of the sampling switch is solved, and the layout area occupation is greatly reduced while the bootstrap voltage is improved; the proportion of the capacitor C3 and the capacitor C4 can be flexibly set to obtain the required bootstrap voltage; and the problem that the on-resistance of the sampling switch is increased due to the reduction of the gate-source voltage can be solved, and the linearity of the sampling switch is improved.

Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and / or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

Method for detecting a state of a connection between an electrically driven motor vehicle (1) and a corresponding charging station, wherein the motor vehicle (1) has a “Control Pilot (CP)” function with a vehicle-side “Control Pilot (CP)” line (3), characterized in that a length of a “Control Pilot” line between the motor vehicle and the charging station is measured by means of a “Power Line Communication” (PLC) chip (4), wherein the length of the “Control Pilot” line between the vehicle and the charging station using signal reflection and signal attenuation or -runtime is measured, wherein the PLC chip (4) sends a signal along the CP line between the motor vehicle and the charging station and receives the signal reflected at the end of the CP line between the motor vehicle and the charging station and running back to the PLC chip (4), wherein the length of the path traversed by the signal is determined based on the signal runtime, wherein the length of the CP line between the motor vehicle and the charging station is clearly determined from the distance traveled by the signal and a specific cable type is determined based on the length of the CP line between the motor vehicle and the charging station.

Certain aspects of the present disclosure generally relate to a digital-to-analog converter (DAC) circuit implemented with a dynamic stacked transistor architecture. The DAC circuit generally includes a first current-steering transistor and a second current-steering transistor. The DAC circuit may also include: a first stacked transistor coupled between the first current-steering transistor and a first output of the DAC circuit; a first switch coupled between a gate of the first stacked transistor and a bias voltage node; a second switch coupled between the gate of the first stacked transistor and a voltage rail; a second stacked transistor coupled between the second current-steering transistor and a second output of the DAC circuit; a third switch coupled between a gate of the second stacked transistor and the bias voltage node; and a fourth switch coupled between the gate of the second stacked transistor and the voltage rail.

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

The invention discloses a high-precision analog domain gain error shaping analog-to-digital converter and an implementation method thereof, and relates to the field of integrated circuit design. The high-precision analog domain gain error shaping analog-to-digital converter adopts a fully differential structure; comprising a first-stage sub analog-to-digital converter, a residual error amplifier and a second-stage sub analog-to-digital converter which are connected in sequence. A first-stage sub analog-to-digital converter is designed into a coarse-fine quantization architecture of an NS SAR ADC and a DAC, an input signal is sampled and quantized through the coarsely quantized NS SAR ADC to generate a first-stage digital code, and then the first-stage digital code is read to the finely quantized DAC. And the finely quantized DAC performs DAC array switching according to the first-stage digital code, and directly obtains the shaped first-stage quantization noise to realize gain error shaping. The method does not need to predict the first-stage quantization noise any more, solves the problem that the truncation error is not matched with the gain, and achieves a better gain error shaping effect.

The invention discloses a dual-mode TDC implementation method and system based on an FPGA, and relates to the technical field of electronic circuits, and the technical key points are as follows: after a dual-mode signal generation circuit receives each STOP pulse, a logic sequence opposite to the last time is immediately output as an effective delay signal, the reset of the last time signal in a time delay chain (TDL) is not required, and the time delay time is shortened; when the logic signal propagated last time does not completely fade, the new reverse logic signal can be independently propagated in the TDL, and the new reverse logic signal and the new reverse logic signal do not interfere with each other; meanwhile, the rising edge of the system clock only updates the state of the main trigger to serve as the logic reference of the next trigger, and an additional reset process is not needed, so that the dead zone time of single measurement is strictly controlled to be a single period corresponding to the system clock, and compared with a double-period dead zone in an existing scheme, the dead zone time is remarkably shortened, and the measurement rate is synchronously doubled; in a high-frequency pulse measurement scene, pulse loss caused by an overlong dead zone can be effectively avoided, and the measurement efficiency is remarkably improved.

According to an aspect of the present disclosure, a display device includes: a stretchable touch panel having a plurality of touch electrodes; a stretchable display panel configured to display an image; and a touch driver configured to operate the stretchable touch panel, in which the touch driver recognizes a stretchable area of the stretchable touch panel and corrects a touch data value of the stretchable area of the stretchable touch panel, thereby improving touch performance of the stretchable touch panel.

A sigma-delta analog-to-digital converter is provided that includes an initial continuous-time integration stage having a variable input resistor and an integration capacitor. A switched-capacitor circuit charges and discharges a replica capacitor to a reference voltage to generate a bias current. A SAR-based tuning circuit includes a variable tuning resistor that generates a tuning voltage while conducting a mirrored version of the bias current. A resistance of the variable input resistor is adjusted responsive to a tuning code from the SAR-based tuning circuit.

The invention discloses a multipath load control acquisition device and system and a load control acquisition method, the device adopts an architecture in which a master device and a slave device cooperate, the master device comprises a master controller, a master communication module, a user display interface and a master interface unit, and the slave device comprises a slave interface unit, a slave controller, an acquisition unit and a slave communication module. Flexible marshalling management is achieved by distributing electronic identity numbers to the breakers, load parameters and the states of the breakers are synchronously collected through the collection unit, a two-way data transmission channel is constructed by means of the master-slave communication module, a control signal is generated based on preset logic and real-time data through the master controller, and the state of the breakers is controlled. And the slave controller issues an instruction to drive the circuit breaker electric operation mechanism to realize millisecond-level rapid switching-on and switching-off operation. According to the invention, the problems of insufficient number of loops, lack of state monitoring, slow response and the like of an existing load control system are solved, and accurate, rapid and intelligent management of multi-path loads on a client side is realized.

The invention discloses a wireless electric energy and data synchronous transmission system which comprises a direct-current carrier separation circuit, an electric energy transmitting circuit, an electric energy receiving circuit, a communication circuit and a direct-current carrier synthesis circuit. The communication circuit comprises a first data transceiving circuit, a first transceiving coil, a second transceiving coil and a second data transceiving circuit; the direct-current carrier separation circuit is respectively connected with the electric energy transmitting circuit and the first data transceiving circuit, and is used for performing electric energy and communication signal separation on the received direct-current carrier signal; and the direct current carrier synthesis circuit is connected with the electric energy receiving circuit and the second data transceiving circuit, and is used for coupling the received electric energy and the communication signal to form a direct current carrier signal. According to the invention, synchronous transmission of wireless electric energy and data can be realized, the stability, safety and expandability of an underground equipment system are improved, the operation cost of the system is reduced, and the operation efficiency is improved.

The invention belongs to the technical field of coal mine shaft maintenance emergency communication, and particularly discloses a shaft maintenance communication device and method based on an electromagnetic coupling principle. The device comprises an elevator controller, a car room main controller, a signal transmission medium and two pairs of electromagnetic coupling coils. The elevator controller is arranged in an elevator cage, and the car room main controller is arranged in a ground winch control room; a pair of electromagnetic coupling coils is respectively arranged at the top of a skip bucket of the elevator and below a guide wheel through a lasso structure and is respectively used for sending and receiving signals. A closed-loop lifting link where a steel wire rope of the elevator is located is used as a signal transmission medium, and bidirectional long-distance transmission of signals is achieved between an elevator controller and a car room main controller based on the electromagnetic coupling communication principle. A maintainer can actively lock the hoister through the hoister controller, accidental starting of the hoister caused by misoperation of a winch control room is avoided, and after locking is released, a winch driver can be informed of starting and stopping the hoister through voice and dotting control signals.

The present application provides an all-digital multi-phase DC-DC controller. The digital DC-DC controller includes time-based analog-to-digital converters (ADCs) for converting analog voltage signals into digital-domain signals so as to benefit from gate length scaling without limited by the low voltage swing. Also, the DC-DC controller further includes a digital control circuit and a time-based modulator. The digital control circuit can control the time-based modulator in a digital domain, thereby reducing the affection caused by process, voltage and temperature (PVT) variation. Also, the time-based modulator can adjust the timing of the PWM signals and avoid the performance degradation caused by circuit mismatch. Since the digital control circuit can be fully synthesizable, it allows implementations in all kinds of digital CMOS processes with a small chip area.

According to an aspect of the present disclosure, a display device includes: a stretchable touch panel having a plurality of touch electrodes; a stretchable display panel configured to display an image; and a touch driver configured to operate the stretchable touch panel, in which the touch driver recognizes a stretchable area of the stretchable touch panel and corrects a touch data value of the stretchable area of the stretchable touch panel, thereby improving touch performance of the stretchable touch panel.

The invention discloses a multi-channel high-speed low-power-consumption successive approximation analog-to-digital converter, system and method, and relates to the technical field of analog integrated circuit design, the analog-to-digital converter comprises an M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer and a digital error correction circuit, an M-bit non-binary digital code is obtained through quantization of the auxiliary ADC, and the N-bit non-binary digital code is obtained through quantization of the N-bit main ADCs. A group of N-M-bit non-binary digital codes are obtained through quantization of multiple paths of main ADCs respectively, then combination and binary conversion are carried out on M-bit non-binary digital codes and each group of N-M-bit non-binary digital codes through a digital error correction circuit, n groups of binary digital codes are obtained and output, and multi-channel sampling, quantization, conversion and output are achieved. The device has the characteristics of low power consumption, high conversion speed and high precision, and the conversion speed and precision can be improved while the characteristic of low power consumption is maintained.

A method for quantizing data representative of a radio signal received by a radio antenna of a mobile network. The method includes: demodulating the radio signal received by the antenna, providing a demodulated signal; scalar quantizing each value of the demodulated signal using a quantization table selected according to a channel coding level used to transmit the radio signal, providing a quantized demodulated signal; and transmitting the quantized demodulated signal to a channel decoding module.

The invention discloses a high-speed and high-linearity margin amplifier and an analog-to-digital converter, belongs to the technical field of integrated circuits, and solves the technical problem that an existing source follower cannot meet high-speed and high-linearity indexes. The amplifier comprises a margin amplifier bias and output module, a phase inverter and a linear transconductance unit based on an AB-class super source follower structure, wherein the bias and output module, the linear transconductance unit and the phase inverter are connected in sequence. The linear transconductance unit can generate high-linearity transconductance, so that the linearity of the whole margin amplifier is improved, the symmetry of the positive output end and the negative output end of the margin amplifier under the condition of high-frequency or large-swing input can be ensured, and the high-speed and high-linearity index can be effectively met. In addition, a gain calibration module resistant to temperature and process changes is further introduced, and the influence caused by follow-up system environment temperature changes can be automatically compensated.

The invention relates to a full-dynamic exponential increment type low-delay high-precision analog-to-digital converter, which comprises a loop integrator used for receiving an ith-round input signal, and sequentially performing addition processing and integration processing on the ith-round input signal and a feedback signal calibrated by an (i-1) th round to obtain an ith-round integration signal; the first-order exponential increment error feedback noise shaping SAR quantizer is used for carrying out addition processing and multi-bit quantization on the ith round integral signal and the double (i-1) th round residual signal to obtain an ith round quantization signal; the digital-to-analog conversion module is used for sequentially performing format conversion, mismatch calibration and digital-to-analog conversion on the (i-1) th round of quantized signals in the process of processing the ith round of input signals to obtain feedback signals after the (i-1) th round of calibration; and the digital decimation filter module is used for carrying out digital filtering and down-sampling processing on the ith-round quantized signal to obtain an ith-round Nyquist rate output signal. The system can realize higher significant digits in shorter conversion time.

The present invention provides a novel semiconductor device. The present invention uses a comparison unit for comparing two current values, a control unit, and a current output type digital-analog conversion unit to convert an analog signal into a digital signal. The control unit has the function of generating a sign bit indicating the magnitude relation between the two current values, the function of converting, by successive approximation, the difference between the two current values into the digital signal, and the function of outputting the sign bit and the digital signal.

The invention relates to the technical field of integrated circuit design, in particular to a noise shaping assembly line successive approximation type analog-to-digital converter and a control method. Comprising a first stage including an auxiliary successive approximation analog-to-digital converter and a first stage voltage processing module; the second stage comprises a dual-channel noise shaping successive approximation type analog-to-digital converter and a loop filter; the input end of the residual amplifier is connected with the first-stage voltage processing module, and the output end of the residual amplifier is connected with the noise shaping successive approximation type analog-to-digital converter; the first input end of the digital code aligner is connected with the output end of the comparator of the auxiliary analog-to-digital converter, and the second input end of the digital code aligner is connected with the output end of the second-stage comparator. According to the invention, the analog-to-digital conversion speed can be accelerated, the influence of a zero point on a residual voltage amplification coefficient is reduced, the conversion time is shortened, and the input and output common-mode voltages of the time domain converter are stabilized.

A monotonic capacitor digital-to-analog converter (CDAC) is provided. The CDAC includes a converter array comprising a plurality of CDAC units, wherein each CDAC unit comprises a logic unit, a switch, and a capacitor, and wherein each logic unit comprises a first input, a second input, and a third input. The CDAC further includes a first set of control lines, and each of the first set of control lines is connected to the first inputs of the logic units of the CDAC units in a corresponding column of the converter array. The CDAC further includes a second set of control lines, and each of the second set of control lines is connected to the second inputs of the logic units of the CDAC units in a corresponding row of the converter array, but is disconnected from the second input of the logic unit of a CDAC unit in the corresponding row and the last column of the converter array. Each of the second set of control lines is further connected to the third inputs of the logic units of the CDAC units in a row of the converter array adjacent to the corresponding row.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention provides a multi-mode analog signal digitization method and system based on adaptive sampling, and the method comprises the steps: collecting a multi-mode analog signal, and carrying out the preprocessing of the multi-mode analog signal; obtaining a corresponding signal type based on the processed analog signal, and adaptively adjusting the sampling frequency according to the signal type; and adaptive quantization and quantization error compensation are carried out on the adjusted analog signal, and a final digital signal is output after enhancement processing is carried out on the digitized signal. The invention provides an improved analog signal and digital signal conversion method, namely a multi-modal analog signal high-precision digitalization method based on adaptive sampling and deep learning, and aims to improve conversion precision, reduce noise interference, optimize power consumption and response time and expand a dynamic range.