883 results about "Chipset" patented technology

The invention provides a chip assembly and a consumable box set, and relates to the technical field of printing imaging. The consumable box set is used for being in contact with contact pins of printing equipment and receiving printing signals, the printing equipment is provided with at least one first contact pin set and at least one second contact pin set, the first contact pin set and the second contact pin set are not overlapped, a first consumable box of the consumable box set is matched with the first contact pin set, the first consumable box is provided with a first electronic module, and the second consumable box is provided with a second electronic module. The first electronic module is electrically connected with at least one first contact part, and the first contact part is in contact with the first contact pin group to receive a first electric signal; the second consumable box is matched with the second contact pin group and is provided with a second electronic module, the second electronic module is electrically connected with the first electronic module, and the second electronic module receives the first electric signal through the first contact part. According to the invention, the risk of short circuit can be reduced, and normal use of the chip assembly is ensured.

A wafer-level assembly of chiplets comprising a plurality of groups of chiplets including a first group of chiplets and a second group of chiplets, wherein the first group of chiplets is organized as a first fully-connected configuration, wherein the second group of chiplets is organized as a second fully-connected configuration. The wafer-level assembly of chiplets further comprises a plurality of interconnects including a first interconnect and a second interconnect, wherein the first interconnect couples a first chiplet of the first group of chiplets with a first chiplet of the second group of chiplets, wherein the second interconnect couples a second chiplet of the first group of chiplets with a second chiplet of the second group of chiplets, and wherein the plurality of interconnects is arranged in a mesh configuration.

To provide a communication method, user equipment, a mobile communication system, a program, and a chip set for allowing the user equipment in an RRC inactive state to perform multicast reception, in a mobile communication system providing a multicast / broadcast service (MBS).SOLUTION: User equipment UE 100, which is in a ratio resource control (RRC) inactive state and participates in a multicast session, receives a paging message for notifying the start of the multicast session from a network node gNB 200, and determines whether to make a transition from the RRC inactive state to an RRC connected state. The paging message includes session information on the multicast session, and identification information for specifying one or more pieces of user equipment UE 100 to be transitioned to the RRC connected state.SELECTED DRAWING: Figure 9

The invention relates to the technical field of lasers, in particular to a multi-chip vertical external cavity surface emitting laser which comprises a chip set, a first prism, a second prism and an output coupling mirror which are sequentially arranged along a preset central axis. The chipset comprises N gain chips, and the N gain chips output N sub light beams; the N sub-beams pass through the first prism, the sub-beams emitted from the first prism converge towards a preset central axis, the sub-beams are incident to the second prism before convergence and are combined into a resonant beam through the second prism, the resonant beam resonates in a resonant cavity formed by the output coupling mirror and the chip set, and the output coupling mirror and the chip set form a resonant cavity; the output laser is emitted from the output coupling mirror; wherein N is greater than 1. The invention is beneficial for solving the problems that the power of a single chip is limited, the beam combining efficiency is low, only incoherent beam combining can be realized, and a multi-chip beam combining structure is complex.

Provided are an apparatus and method for operation of an apparatus in a wireless communication system. The apparatus may be a UE, a chipset, or a base station. The UE receives an FD configuration message notifying a full duplex symbol from among a plurality of symbols, receives a cell-specific common TDD configuration message, and receives a UE-specific dedicated TDD configuration message. Here, only for the full duplex symbol from among the plurality of symbols, second direction information notified by the dedicated TDD configuration message overrides first direction information notified by the common TDD configuration message.

The invention relates to the technical field of photoelectric couplers, in particular to a novel isolation method of a multichannel ceramic packaging photoelectric coupler, which comprises the following steps: S1, manufacturing a tube shell base and a cover plate; s2, installing a light emitting chip and a light receiving chip; step S3, injecting glue; s4, sealing a cover plate; and S5, mounting the packaging panel. According to the invention, the isolation wall structure is transferred to the cover plate from the tube shell base, on one hand, the problems of deformation, cracking and even collapse of the isolation wall due to stress concentration in the sintering process of the tube shell base are avoided, the manufacturing cost of the tube shell base is greatly reduced, and the yield of manufacturing the tube shell base is improved. And on the other hand, in the chip assembling process, due to the fact that the interior of the tube shell base is not hindered by the isolation wall, the operation space is remarkably enlarged, operations such as chip installation and welding become more convenient, the assembling difficulty and time cost are effectively reduced, and the production efficiency is improved.

The invention provides a double-sided plastic package structure of a vertical routing lead PIN, which can lead out more functional signals, reduce the front-end design pressure and improve the package integration level. The present invention comprises: a substrate; a front chip assembly and a device assembly; a back surface FC chip; a front plastic package body; a back surface plastic package body; a plurality of vertical welding wires; and a plurality of bumps; the substrate is a double-sided substrate, a front chip assembly and a device assembly are respectively bonded on the front surface of the substrate and are packaged through a front plastic package body, the height of the front plastic package body completely covers the height of the front chip assembly and the height of the device assembly, a back FC chip is bonded on the back surface of the substrate, and the height of the back FC chip is larger than that of the front plastic package body. A vertical welding wire is welded to each PIN pad on the back face of the substrate, a protruding block is welded to the tail end of the lower portion of each vertical welding wire, the back face plastic package body is packaged on the back face of the substrate, and the protruding blocks protrude out of the lower surface of the back face plastic package body.

A three-dimensional integrated circuit device can include a group of die, a device layer and a thermal interface material formed above the substrate. A heat spreader can be located above the die, the device layer and the thermal interface material. The heat spreader can include a heat pipe comprising a rectangular-shaped heat pipe or disk-shaped heat pipe. A heat sink can be located above the heat spreader. The heat sink can include the heat pipe comprising the rectangular-shaped heat pipe or the disk-shaped heat pipe.

An operation method of a device in a wireless communication system, and the device are provided. The device can be a terminal, a chipset or a base station. The terminal determines available slots from among a plurality of slots, and repeatedly performs uplink transmission in the available slots. A specific slot is excluded from counting of the available slots if a nonuplink subband resource of the specific slot overlaps with the uplink resource for uplink transmission when the specific slot of the plurality of slots is a subband-full duplex (SB-FD) slot including both of the uplink subband resource and the non-uplink subband resource in the frequency domain.

A data reading / writing method includes a processor that sends a read / write request to the storage. The read / write request is used to request to perform data reading / writing in the storage, and the read / write request carries a logical address of data. After receiving the read / write request, the storage maps the logical address to target positions in banks of N storage chips in the storage, and performs data reading / writing at the target positions in the banks of the N storage chips. The target positions in the banks of the N storage chips are distributed in different areas.

Embodiments of the present invention provide a trackable device system comprising a modular housing integrated with personal or enterprise assets. The system includes a chipset with wireless communication modules (e.g., BLE, UWB, GPS, or cellular), a processor, location modules, memory, and power management components. The processor supports proximity detection, geofencing, motion-triggered alerts, lost-mode activation, and SOS signaling to emergency contacts. Integration with mobile platforms enables real-time tracking, augmented reality overlays, and compatibility with networks like Apple Find My™ and Google Find My Device. Security features include encrypted memory, tamper detection, secure pairing, and a secure enclave for sensitive data. In enterprise settings, the system supports blockchain-based inventory logging, role-based access, and RFID / NFC inventory control. The device adapts to diverse form factors and deployment scenarios, ensuring reliable location tracking, anti-tamper protection, and secure asset management for consumer, industrial, and institutional applications.

The invention relates to the field of agricultural lighting equipment, and discloses a plant light quality regulation and control integrated LED light source with a uniform spectral space and a method of the plant light quality regulation and control integrated LED light source. The multispectral LED chip group is arranged on the lamp bead substrate in a die bonding manner; the plurality of groups of independent bonding pads are arranged on the lamp bead substrate and are electrically isolated from one another; and the transparent optical lens adhesive layer covers the chip group. And different spectrum chip groups in the multi-spectrum LED chip group are electrically connected with the corresponding independent bonding pads respectively. Driving current is provided for the multiple groups of independent bonding pads through an external driving circuit, and the luminous intensity of different spectral components is independently adjusted by independently adjusting the magnitude of the current input to different bonding pad groups, so that the output composite spectrum is changed. According to the invention, the multispectral chip is integrated in a single packaging body, the problem of non-uniform spectral space is solved from the physical source, the accurate regulation and control of the spectral ratio are realized through multichannel independent control, and the design and manufacturing cost of the lamp is reduced at the same time.

The utility model discloses a three-dimensional stacked packaging structure. The three-dimensional stacked packaging structure comprises a bottom chip; the core chip group is positioned on the first active surface of the bottom chip; the top chip set is located on the top surface of the core chip set, the core chip set comprises a plurality of hybrid bonding units which are sequentially stacked in the direction perpendicular to the first active face of the bottom chip, and each hybrid bonding unit comprises two core chips with the active faces opposite to each other and bonded together in a hybrid mode; the bottom chip is mixed and bonded with one core chip of the mixed bonding unit at the bottommost layer in the core chip set, and the top chip set comprises two top chips of which the active surfaces are oppositely mixed and bonded together; one top chip in the top chip set and one core chip of the hybrid bonding unit on the topmost layer in the core chip set are bonded together in a hybrid mode, the interconnection distance between the chips is greatly reduced through the hybrid bonding mode, and therefore more layers of chips can be stacked.

The invention provides a modular packaging structure, and the technical scheme is as follows: the modular packaging structure comprises an electronic component carrying sheet, and the top layer of the electronic component carrying sheet is configured to be in coupling connection with a chip or an electronic component; the bottom layer of the supporting plate is configured to be in coupling connection with the printed circuit board; wherein the electronic component carrying sheet and the supporting plate are mutually coupled, so that the modular packaging structure is formed; the supporting plate is made of a high-rigidity material, the thermal expansion coefficient of the high-rigidity material is lower than that of the electronic element carrying sheet, and the thermal expansion coefficient of the chip or the electronic element is lower than that of the electronic element carrying sheet; according to the invention, by adopting the supporting plate, the electronic component carrying sheet and the chip combined structure with the thermal expansion coefficient decreasing in a gradient manner, the problem of thermal stress mismatch in a high-temperature process is effectively relieved, so that the deformation of the packaging structure is inhibited, and the production yield and the product reliability are improved.

Overhang architectures for high bandwidth memory (HBM) multi-die assemblies and methods for making same. The overhang architecture places the DRAM (HBM) underneath the top IC die. The signal interconnects between the top IC die and the DRAM die are direct signal interconnects without lateral routing on a package substrate or on a motherboard.

The invention relates to the technical field of biology, and provides a chip assembly and a preparation method thereof. The chip assembly comprises a substrate, a circuit layer, a culture piece and a microelectrode array. The microelectrode array is located in the culture tank of the culture piece, the culture tank can be used for containing the to-be-monitored organ, and the to-be-monitored organ can make contact with the substrate and make contact with the microelectrode array when located in the culture tank. The substrate and the microelectrode array are both flexible structural members, so that the substrate and the microelectrode array can deform. Therefore, when the organoid is in the culture tank and the organoid is in contact with the microelectrode array, the microelectrode array deforms to be matched with the appearance of the organoid, so that the organoid is in more sufficient contact with the microelectrode array, the signals, collected by the microelectrode array, of the organoid are more accurate, and the damage of the microelectrode array to the organoid can be reduced. The base is also a flexible structural member, and the microelectrode array arranged on the base can move correspondingly by deforming the base so as to adjust the position of the microelectrode array.

Testing a semiconductor can be time-consuming as the chip architecture becomes more complex. Testing the possible scenarios becomes increasingly difficult. Chip quality characteristics relating to the chips on a wafer can be used to estimate a probability or rating relating to bypassing system-level testing (SLT). A chip can bypass SLT if there is a high likelihood of passing SLT. Thousands of chip characteristics can be received from wafer testing, chip probe testing, environmental parameters, factory parameters, and other parameters. A chip quality model can use chip quality characteristics as input to generate chip group and SLT parameters. The chip quality model can be a machine learning model or other types of machine learning systems. The chip group parameter or the SLT parameter can be used to direct the testing path of a chip where some chips can bypass SLT thereby saving production time.

Embodiments herein relate to testing chiplets during the manufacturing process. In one aspect, an on-chiplet interface is provided which allows testing of inter-chiplet communications of a chiplet on a package substrate without requiring the use of another chiplet. The interface communicates with an external Field-Programmable Gate Array (FPGA) on the package substrate at a reduced frequency compared to a frequency of the inter-chiplet communications. The FPGA can in turn communicate with a workstation to receive instructions and provide test results. The FPGA sends test pattern signals to, and evaluates corresponding responses from, circuitry of the chiplet which implements an inter-chiplet communication standard such as the Universal Chiplet Interconnect Express (UCIe) standard. In another aspect, the physical layer (PHY) circuits of two chiplet are tested with respective FPGAs.

The invention discloses a semiconductor chip packaging method, and relates to the technical field of semiconductor packaging, and the method comprises the steps: carrying out the salient point preparation of a semiconductor chip, carrying out the data collection, obtaining a salient point shape data set, carrying out the cleaning after the preparation of a substrate, obtaining the surface data of the substrate, fusing the surface data of the substrate with the salient point shape data set, generating a shape quality data set, and carrying out the processing of the shape quality data set. The method comprises the following steps: establishing a chip prediction model, outputting a welding spot failure probability and optimized process parameters, overturning a chip, performing alignment operation to obtain a chip and a substrate assembly which are subjected to alignment, performing welding parameter optimization through a reflow soldering furnace, forming a uniform intermetallic compound, and obtaining a welded chip and substrate assembly. And according to the welded chip and substrate assembly, a dispensing machine and a molding press are used for processing, and a packaged chip assembly is obtained. According to the method, the chip prediction model is established, so that the failure rate of the welding spots is remarkably reduced, the adaptability of process parameters is improved, and missing detection of the failed welding spots is avoided.

The invention provides an on-chip integrated laser light source and an optical coupling integration method thereof.The on-chip integrated laser light source comprises a silicon optical substrate and a light source chip assembly integrated on the silicon optical substrate, and the silicon optical substrate comprises an optical signal transmission waveguide; the light source chip assembly comprises a surface-emitting distributed feedback laser chip so as to generate laser beams emitted in the direction perpendicular to the surface of the chip. The on-chip integrated laser light source further comprises a grating coupling structure arranged between the surface emission distributed feedback laser chip and the optical signal transmission waveguide. The light-emitting surface of the surface-emitting distributed feedback laser chip is arranged towards the silicon light substrate, and a laser beam generated by the surface-emitting distributed feedback laser chip is directly projected and coupled into the light signal transmission waveguide through the grating coupling structure; the surface-emitting distributed feedback laser chip is fixedly combined on the silicon optical substrate through a flip chip technology, so that the high-precision end face alignment requirement of the heterogeneous integrated waveguide is converted into high-efficiency grating coupling based on a surface light emitting mode. In this way, harsh end face coupling is converted into efficient grating coupling.

A communication method performed by a user equipment in a mobile communication system that provides a multicast / broadcast service (MBS) includes receiving a multicast session from a network in a radio resource control (RRC) connected state using a first multicast radio bearer (MRB) for the RRC connected state, receiving, from the network, an RRC release message for causing the user equipment to transition to an RRC inactive state, the RRC release message including configuration information indicating a configuration of a second MRB used for reception of the multicast session in the RRC inactive state, and establishing the second MRB by applying the configuration information before suspending the first MRB in response to the reception of the RRC release message.

The invention discloses a flip-chip bonding integrated structure of a pluggable CPO optical engine. The flip-chip bonding integrated structure comprises a CPO optical engine chip assembly, a pluggable optical fiber array assembly, an optical fiber array plugging adapter, a CPO optical engine cover plate structural member and a CPO optical engine PCBA. The CPO optical engine chip assembly is arranged at one end of the interior of the CPO optical engine cover plate structural member, the optical fiber array plugging adapter is arranged at the other end of the interior of the CPO optical engine cover plate structural member, and the pluggable optical fiber array assembly is connected to one side of the optical fiber array plugging adapter through a clamping assembly. A pressure-bearing retaining assembly is arranged between the other side of the pluggable optical fiber array assembly and the inner wall of the CPO optical engine cover plate structural member. The invention aims at providing the flip-chip bonding integrated structure of the pluggable CPO optical engine to overcome the existing defects, and the problem that precise optical coupling adjustment is inconvenient to carry out after the optical engine chip assembly is directly bonded to the CPO optical engine PCBA is solved.

The utility model provides an LED device and a lamp, and relates to the technical field of semiconductors, the LED device comprises a support, and a first chipset, a second chipset and a third chipset which are arranged in the support, a containing groove is arranged in the support, and the first chipset, the second chipset and the third chipset are arranged in the containing groove. Two parallel partition plates are arranged in the containing groove to divide the containing groove into three independent sub-containing grooves, and the first chip set, the second chip set and the third chip set are arranged at the bottoms of the sub-containing grooves respectively. A plurality of fluorescent colloids sequentially cover the first chip set, the second chip set and the third chip set, and all the fluorescent colloids at least partially protrude out of the sub-containing grooves to form lens parts. The LED device provided by the utility model solves the problem that the LED treatment effect of spectrum rehabilitation treatment in the prior art is poor.

A communication method used in a mobile communication system for providing a multicast / broadcast service (MBS) includes: providing, by a base station, two types of multicast control channels (MCCHs) being a first MCCH for a broadcast communication service and a second MCCH for a multicast communication service; and transmitting, by the base station to a user equipment, mapping information indicating a correspondence relationship between an MBS session identifier of an MBS session and a type of the MCCH for transmitting a Point-to-Multipoint (PTM) configuration corresponding to the MBS session.

The invention discloses a chip packaging structure and a manufacturing method of the chip packaging structure, and relates to the technical field of chip packaging. The chip packaging structure comprises a substrate, a first chip assembly and a second chip assembly, the substrate comprises a first surface, a second surface and a first side face, the first surface and the second surface are oppositely arranged, the first side face is connected between the first surface and the second surface, a first rewiring layer is arranged in the substrate, and the first rewiring layer is exposed out of the first surface and the first side face; the first chip assembly is located on the first side face and comprises a first chip and a first pin located on the side, close to the first side face, of the first chip, and the first pin is electrically connected with the first rewiring layer; the second chip assembly is located on the first surface and comprises a second chip and a second pin located on the side, close to the substrate, of the second chip, and the second pin is electrically connected with the first rewiring layer. On the premise that the reliability of the chip packaging structure is not affected, the integration level of the chip packaging structure can be improved.

The invention provides a multi-modal data real-time analysis and feedback method and system, and the method comprises the steps: collecting a video frame and an audio frame, reading a count value of the same monotonic timer when the collection of the video frame and the audio frame is completed, and generating an audio and video sequence; calculating the behavior popularity of each region in each time slice based on the sequence, and generating a region set for multi-modal event analysis in combination with a preset threshold and a quantity upper limit; scheduling the corresponding video sub-blocks to a visual computing power unit for target positioning and action classification, and executing voice activity detection and keyword category judgment on the time-aligned audio clips at the same time; visual and audio results are fused, and a structured event sequence is generated according to time slice and region compression; and constructing a classroom teaching chain through the sequence, identifying a key event, and finally generating a teaching event description. According to the invention, under the condition of domestic chip combination, cost, time delay, multi-modal consistency and data security controllability are considered, and real-time perception and feedback of teaching behaviors are effectively supported.

To provide a semiconductor device and a method of manufacturing the same, capable of suppressing generation of abnormal etch pits, improving mechanical strength after chip assembly, and securing reliability of a product.SOLUTION: The semiconductor device includes a semiconductor substrate 1 of a first conductivity type, an element structure provided on the semiconductor substrate 1, and a main electrode 16 provided on the element structure. The main electrode 16 is an Al alloy film, and an area where the orientation of Al of the Al alloy film is (111) is 99% or more. The average particle diameter of the Al alloy film is 5.5 μm or more and 10 μm or less. The Al alloy film is an Al film, an Al-Si film, or an Al-Si-Cu film.SELECTED DRAWING: Figure 1

Disclosed are techniques for wireless communication. In an aspect, a User Equipment (UE) may partially disable transmissions on a transmission port based on a temperature condition (e.g., chipset temperature or skin temperature exceeding threshold). In a further aspect, the UE may enable the partially disabled transmissions on the transmission port in response to cessation of the temperature condition. In a further aspect, the UE may transmit a capability indication to a base station that indicates that the UE is capable of supporting a transition from a multi-layer (rank-2) communication mode to a single-layer (rank-1) communication mode.

The utility model discloses an anti-static device and a flat knitting machine, the anti-static device is applied to the flat knitting machine, and the anti-static device comprises a switch plate arranged on the flat knitting machine; the chip assembly is arranged on the switch board; the sensing piece is connected with an operating rod of the flat knitting machine and used for triggering the chip assembly to control the working state of the flat knitting machine; wherein a metal layer is arranged on the side, close to the induction piece, of the switch board, the distance between the metal layer and the induction piece is smaller than the distance between the chip assembly and the induction piece, and the metal layer is connected with a power source positive electrode or a power source negative electrode of the switch board or electrically and used for discharging static electricity on the induction piece when the operating rod is operated. Through the mode, the structure is simplified, the cost is reduced, the problem of static electricity prevention failure caused by neglected loading or long-term aging of the metal wire connected with the electrical ground is avoided, and the reliability of the static electricity prevention function is improved.