1652 results about "Chipset" patented technology

The invention relates to the technical field of computer programming languages, and particularly discloses a coal-fired power plant safety monitoring system and method. The system comprises a multi-modal data fusion platform, a federal learning agent network and a digital twinborn simulation engine. The edge computing node carries out unified acquisition and feature extraction on multi-source heterogeneous data through multi-protocol conversion, quantum noise suppression and a preprocessing chipset; the multi-modal data fusion platform realizes semantic mapping based on a knowledge graph, and fuses time-space correlation characteristics of data such as an infrared image and gas concentration by adopting a time-space encoder and a cross-modal attention mechanism. According to the method, the problems of early warning delay and high false alarm rate caused by low multi-source data decentralized processing efficiency and insufficient nonlinear correlation analysis in a traditional scheme are solved, efficient data fusion, complex risk accurate prediction and automatic safety response are realized, and the real-time performance and reliability of a coal-fired power plant monitoring system are remarkably improved.

The invention discloses a multichannel electrophysiological signal acquisition system and an acquisition method thereof, and the multichannel electrophysiological signal acquisition system comprises a power supply module electrically connected with a controller, an analog front-end chipset, a filter module and an analog-to-digital conversion module; the analog front-end chip set is used for acquiring an analog signal and preprocessing the analog signal; the pre-processed analog signal is converted into a digital signal through a filter module and an analog-to-digital conversion module, and the digital signal is transmitted to a controller; the filter module is used for filtering and denoising; the timer module connected with the controller generates a sampling frequency, transmits the sampling frequency to the analog-to-digital conversion module, and provides a time sequence signal for the analog-to-digital conversion module. The invention discloses a multi-channel electrophysiological signal acquisition system, which solves the problem of synchronous sampling time sequence control of a high-density electrode array and eliminates signal phase deviation caused by clock jitter among multiple channels under the constraint of maintaining the total power consumption of the system. And real-time power frequency interference suppression is realized.

The invention discloses an implementation method of a multi-chip high-density connection photoetching technology, an implementation method of a photoetching technology for multi-chip interconnection, a chip-level chip interconnection method, a manufacturing method of a mask plate line and photoetching equipment. The implementation method of the multi-chip high-density connection photoetching technology comprises the following steps: selecting a first mask plate to align and expose with a first original pattern unit in a first M * N chipset through a second alignment mark, and transferring a pattern of the first mask plate to an exposure area covering the first original pattern unit; longitudinally moving the substrate by M times of the longitudinal size of the original pattern or transversely moving the substrate by N times of the transverse size of the original pattern to execute alignment exposure, and completing exposure of corresponding areas of other M * N chip groups; and other masks are selected to repeatedly perform exposure on other corresponding pattern units of the first M * N chip set, and longitudinal movement or transverse movement is repeatedly performed to complete exposure of corresponding areas of the corresponding pattern units in other M * N chip sets. According to the scheme, high-density interconnection of multiple chips is realized.

A method of configuring a robot of a fleet of robots for use of an AI chipset includes receiving a request for a robotic fleet to perform a job. The method includes defining a set of tasks that are to be performed by the robotic fleet in performance of the job. The method includes assigning at least one task of the set of tasks to a robot. The method includes determining a configuration for the robot based on the assigned task and a components inventory that indicates different components that can be provisioned to the robot including at least one AI chipset, and for each component, a set of extended capabilities and a status of the component. The method includes configuring the robot based on the determined configuration to use the at least one AI chipset. The method includes deploying the robotic fleet to perform the job.

A method or system for implementing a machine learning pipeline on a chipset comprising a plurality of hardware compute elements. The system accesses a hardware-agnostic functional description of the machine learning pipeline, wherein the description specifies a plurality of functional modules, including at least one machine learning model. Hardware specifications of the chipset are accessed to identify the available hardware compute elements. Based on the hardware specifications, the functional modules are synthesized into a plurality of interconnected executable components configured to execute on at least two different hardware compute elements. An implementation package is generated, comprising the executable components and metadata describing interconnections between them. The implementation package is then deployed to the chipset, where the executable components are executed by the identified hardware compute elements.

The utility model discloses a liquid drop preparation instrument and an antibody screening device, and the liquid drop preparation instrument comprises a chip assembly which comprises a liquid drop generation chip and a liquid drop sorting chip, and the liquid drop sorting chip comprises a sorting electrode; the sample table is used for placing at least one of the liquid drop generating chip and the liquid drop sorting chip; the optical module is optically coupled with the sample table and is used for providing incident light to the sample table and collecting an optical signal generated by the biological sample or the liquid drop in response to the incident light; the liquid path system is in operable conduction with the chip assembly and is used for pumping a solution to the liquid drop generating chip or the liquid drop sorting chip; the control circuit can selectively call a first group of control parameters or a second group of control parameters, the first group of control parameters comprises a first control instruction, and the second group of control parameters comprises a second control instruction; the control circuit comprises a feedback control sub-circuit used for controlling the sorting electrodes. According to the liquid drop preparation instrument, liquid drop preparation can be carried out, and needed liquid drops can be rapidly sorted out.

The invention discloses a photoetching technology implementation method for multi-chip high-density connection, a chip-level chip interconnection method, a mask plate line manufacturing method and photoetching equipment, and the photoetching technology implementation method comprises the following steps: selecting a first mask plate, and aligning and exposing the first mask plate and a first original pattern unit through a second alignment mark, transferring the first mask pattern to a first exposure area; longitudinally moving the substrate by M times of the longitudinal size of the original pattern for alignment exposure, and transversely moving by 1 time of the transverse size of the original pattern for alignment exposure to complete exposure of other M * 1 chipset exposure areas; a second mask is selected to be aligned with the first original pattern unit for exposure through a second alignment mark, and a second mask pattern is transferred to a second exposure area; and transversely moving the substrate by N times of the transverse size of the original pattern for alignment exposure, and longitudinally moving by 1 time of the longitudinal size of the original pattern for alignment exposure, thereby completing exposure of other 1 * N chipset exposure areas. According to the scheme, high-density interconnection of multiple chips is realized.

The invention relates to the technical field of integrated circuit board finished product detection, in particular to a computing processing module finished product monitoring method and system, and the method comprises the steps: scanning a plurality of computing processing module finished products passing through a finished product conveying belt in real time through a linear array laser scanner disposed above the finished product conveying belt, and carrying out the real-time monitoring of the plurality of computing processing module finished products; further obtaining a spectrum pattern corresponding to each calculation processing module finished product; identifying local spectrum patterns corresponding to the plurality of chip assemblies in the spectrum pattern; and sequentially detecting whether each local spectrum pattern has a plane flaw, if so, evaluating the damaged surface of the plane flaw, and evaluating the damage degree of the damaged chip assembly based on the proportion of the damaged surface. According to the monitoring method, the spectral pattern representing the height information is generated in real time through the linear array laser scanner, the local areas of the multiple chip assemblies are accurately recognized in combination with the RGB color threshold value and the image feature extraction algorithm, interference caused by dense arrangement of the multiple assemblies is effectively avoided, and the positioning precision and the anti-noise capacity of plane defect detection are improved.

An operating method of a device in a wireless communication system, and the device are provided. The device can be a terminal, a chipset, or a base station. The terminal receives first PUCCH resource configuration information and second PUCCH resource configuration information, which are independent of each other, and applies the first PUCCH resource configuration information or the second PUCCH resource configuration information to each of a plurality of slots so as to transmit a PUCCH through the plurality of slots. The first PUCCH resource configuration information or the second PUCCH resource configuration information is applied to the specific slot on the basis of whether a specific slot from among the plurality of slots is a half duplex slot or a full duplex slot.

The invention discloses an orthogonally stacked double-sided cooling power module and a preparation method thereof. The orthogonally stacked double-sided cooling power module comprises a decoupling capacitor, a copper-clad ceramic substrate, a power chip and a metal cushion block, the metal cushion blocks and the power chips are stacked and connected layer by layer in a metal cushion block-power chip-metal cushion block mode to form a series chipset, and the copper-clad ceramic substrate is connected with the two sides of the metal cushion blocks in the series chipset and is perpendicular to the power chips. According to the invention, through the cooperative effect of orthogonal stacking packaging and double-face cooling of the double copper cushion blocks, the electrical and thermal performance of the cooling power module is cooperatively optimized, the parasitic inductance of the power module is significantly reduced, the transient over-current supporting capability is significantly improved, and the packaging technology has good flexibility and is suitable for large-scale production. The method is suitable for power modules of different packaging types.

Multi-die bridge assemblies and methods for three-dimensional packaging. The architectures assemble a bridge component with two or more integrated circuit die to thereby create a multi-die (MD) bridge assembly. The means for attaching the bridge component to the dies can be hybrid bonding, solder bumps, thermal compression bonding, or a combination thereof. The created MD bridge assembly can be subjected to performance testing prior to attachment to a substrate. Attaching the MD bridge assembly to the substrate can include fitting the bridge component portion into a cavity in the substrate and attaching the bridge component to a cavity floor with another plurality of attachment options.

The invention provides a chip assembly and a consumable box set, and relates to the technical field of printing imaging. The consumable box set is used for being in contact with contact pins of printing equipment and receiving printing signals, the printing equipment is provided with at least one first contact pin set and at least one second contact pin set, the first contact pin set and the second contact pin set are not overlapped, a first consumable box of the consumable box set is matched with the first contact pin set, the first consumable box is provided with a first electronic module, and the second consumable box is provided with a second electronic module. The first electronic module is electrically connected with at least one first contact part, and the first contact part is in contact with the first contact pin group to receive a first electric signal; the second consumable box is matched with the second contact pin group and is provided with a second electronic module, the second electronic module is electrically connected with the first electronic module, and the second electronic module receives the first electric signal through the first contact part. According to the invention, the risk of short circuit can be reduced, and normal use of the chip assembly is ensured.

Systems, devices, and methods for disaggregating networking components are provided. An example networking chassis includes a first disaggregated server device supported by the networking chassis that includes a first central processing unit (CPU) and a first graphics processing unit (GPU) coupled with the first CPU. The networking chassis further includes a first insertable switch module communicably coupled with the first disaggregated server device that includes first switching chipsets and a first fabric management controller coupled with the first switching chipsets. The first insertable switch module at least partially controls data transmission associated with the first disaggregated server device. The first GPU of the first disaggregated server device is isolated on the first disaggregated server device, supported on the first disaggregated server device in the absence of other GPUs, or is otherwise the only GPU on the first disaggregated server device so as to provide modularity in networking applications.

A data access method, comprising: receiving a first data access instruction from an upper-level chip; determining a new access address on the basis of an access address in the first data access instruction and address space information of a current chip; and updating the access address in the first data access instruction to the new access address, and then sending to the next-level chip the first data access instruction after update so as to access target data. According to the data access method, cross-chip data access in a multi-chip cascading mode can be realized, and a cascade chip group having a larger addressable range can be flexibly constructed according to requirements, so as to meet different product or application requirements. Further disclosed are a multi-chip cascading method and system, a device, and a storage medium.

The invention provides an arbitrary waveform generator multi-chip DAC synchronization system, a delay adjustment module comprises an FPGA chip, an integrated clock management chip and a plurality of DAC chips, and the FPGA chip provides digital signals needing to be converted into analog waveforms for the DAC chips and sends parameter configuration signals to the integrated clock management chip and the DAC chips; the integrated clock management chip generates a reference clock, generates a sampling clock based on the reference clock, distributes the sampling clock to the DAC chip and the FPGA chip, and distributes a synchronization signal to the DAC chip; the multiple DAC chips are all configured to be slave chips to form multiple paths of arbitrary waveform generator output channels, digital signals are synchronously converted into analog signals, the analog signals are processed by a conditioning circuit and then output, the circuit structure of the system is remarkably simplified, synchronization of the multiple DAC chips can be achieved only through one integrated clock management chip, and the system is simple in structure, convenient to use and high in practicability. In addition, delay adjustment between DAC chips can be flexibly achieved, calibration or alignment of circuits and devices is not needed, and good application effects are achieved.

One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets include a graphics processing cluster including a plurality of processing resources. The plurality of processing resources including a matrix accelerator having circuitry to perform operations for a neural network in which model topology and weights of the neural network are encrypted. The matrix accelerator configured to execute commands of a command buffer, the commands generated based on a decomposition of the model topology of the neural network and access encrypted weights in memory of the graphics processor via circuitry configured to decrypt the encrypted weights via a key that is programmed to the hardware of the circuitry.

The invention discloses a financial auditing system based on artificial intelligence, which belongs to the technical field of artificial intelligence and comprises a heterogeneous data dynamic adaptation device, a trusted data pipeline system and a central auditing processing unit. The heterogeneous data dynamic adaptation device comprises a multi-protocol PHY chip set, an FPGA programmable logic array, a protocol sensing antenna array and an AI coprocessor. The protocol sensing antenna array is annularly arranged on the inner wall of the device shell and comprises at least 12 miniature receiving and transmitting modules with adjustable directions; a protocol reverse learning model is arranged in the AI coprocessor, and a protocol analysis scheme is dynamically generated by analyzing electromagnetic radiation characteristics of an interface. According to the financial auditing system based on artificial intelligence, real-time dynamic data adaptation and credible traceability of a cross-heterogeneous financial system can be achieved, the problems of format conflict, semantic ambiguity and transmission delay of multi-source heterogeneous data in the auditing process are solved, and meanwhile verifiability and non-tampering performance of the data extraction process are ensured.

The invention discloses a fusion quantum secure communication method of an NAT gateway, and relates to the technical field of communication network information security and quantum information. Comprising the steps of 1, creating a fusion quantum security communication system of an NAT gateway, 2, adopting a quantum hybrid encryption architecture through a quantum security module, and internally arranging a quantum key distribution unit and an anti-quantum computing acceleration chipset, 3, expanding a quintuple mapping structure of NAT through a dynamic address mapping and quantum encryption module, newly adding a quantum security dimension field QSV, and carrying out quantum encryption on the quantum key distribution unit and the anti-quantum computing acceleration chipset. And 4, developing a protocol non-inductive conversion engine through a hybrid protocol stack cooperation module, supporting an IPv4 / IPv6 dual-stack quantum tunnel and a quantum key inheritance protocol to realize cross-protocol family encryption parameter migration, dynamically adjusting a quantum encapsulation mode in an address conversion process, and dynamically associating an internal network address port with a quantum key parameter and a channel fingerprint feature. And 5, constructing a quantum perception type session state machine through an anti-quantum attack session management module, and performing a joint decision-making mechanism through quantum entanglement state monitoring and classical traffic feature analysis.

The invention discloses a microwave and millimeter wave low-cost compact radio frequency digital integrated front-end module, and relates to the technical field of microwave and millimeter wave devices. The front-end module comprises a substrate layer, a preceding-stage compound bare chip and a silicon-based chip group are arranged on the upper surface of the substrate layer, a first group of BGA solder balls located on the lower surface of the substrate layer are connected with a first metal cushion block on one side of the preceding-stage compound bare chip through a first quasi-coaxial structure penetrating through the substrate layer up and down, and a second group of BGA solder balls located on the lower surface of the substrate layer are connected with a second metal cushion block on one side of the preceding-stage compound bare chip through a second quasi-coaxial structure penetrating through the substrate layer up and down. The second metal cushion block is connected with a BGA solder ball on one side of the BGA packaging chip through a second similar coaxial structure vertically penetrating through the substrate layer, and the BGA packaging chip is connected with a third metal cushion block on one side of the silicon-based chip set through a third similar coaxial structure vertically penetrating through the substrate layer. And the fourth metal cushion block is connected with a second group of BGA solder balls positioned on the lower surface of the substrate layer through a fourth quasi-coaxial structure which vertically penetrates through the substrate layer. The front-end module can realize extremely low-loss transmission, and the interconnection flexibility is higher.

The invention relates to a register access signal conversion and transmission method, a chip and a system on chip. The method comprises the following steps: receiving a register access request time sequence signal from an APB interface of a local chip; generating a UCIe sideband register access request data packet according to the register access request time sequence signal; and sending the UCIe sideband register access request data packet to a target layer. The chip comprises a conversion module which is located in a protocol layer of the chip and used for receiving a register access request time sequence signal from an APB interface; generating a UCIe sideband register access request data packet according to the register access request time sequence signal; and sending the UCIe sideband register access request data packet. According to the invention, the integration of the system-on-chip is facilitated, the compatibility of the system-on-chip composed of small chips is improved, so that the system-on-chip can conveniently access the local small chips and cross-chip registers, and the function specified by a UCIe protocol sideband is realized.

A method, an end device, and a non-transitory computer-readable storage medium are described in relation to a learning-based network optimization service. The learning-based network optimization service may include an AI / ML model pairing between an end device and a network device based on AI / ML model identifiers that may include or correlate to a radio frequency (RF) modem or chipset identifier of the end device. The AI / ML models may support entity-specific optimizations, use and sub-use cases, and network-side and end device-side key performance indicators.

A wafer-level assembly of chiplets comprising a plurality of groups of chiplets including a first group of chiplets and a second group of chiplets, wherein the first group of chiplets is organized as a first fully-connected configuration, wherein the second group of chiplets is organized as a second fully-connected configuration. The wafer-level assembly of chiplets further comprises a plurality of interconnects including a first interconnect and a second interconnect, wherein the first interconnect couples a first chiplet of the first group of chiplets with a first chiplet of the second group of chiplets, wherein the second interconnect couples a second chiplet of the first group of chiplets with a second chiplet of the second group of chiplets, and wherein the plurality of interconnects is arranged in a mesh configuration.

To provide a communication method, user equipment, a mobile communication system, a program, and a chip set for allowing the user equipment in an RRC inactive state to perform multicast reception, in a mobile communication system providing a multicast / broadcast service (MBS).SOLUTION: User equipment UE 100, which is in a ratio resource control (RRC) inactive state and participates in a multicast session, receives a paging message for notifying the start of the multicast session from a network node gNB 200, and determines whether to make a transition from the RRC inactive state to an RRC connected state. The paging message includes session information on the multicast session, and identification information for specifying one or more pieces of user equipment UE 100 to be transitioned to the RRC connected state.SELECTED DRAWING: Figure 9

This disclosure provides systems, methods, and devices for enhancing data communication and computation efficiency in Systems on a Chip (SoC). In one aspect, a system is provided that uses a network on a chip (NOC) to route communications between chip components using a plurality of network interfaces linked by shared data connections. The system may be configured to route communications via multiple virtual channels along the shared connections, with credit restrictions for the channels. Additionally, the system may support mechanisms for maintaining both private and shared credit balances for these virtual channels. Additional aspects are also discussed.

The invention relates to the technical field of lasers, in particular to a multi-chip vertical external cavity surface emitting laser which comprises a chip set, a first prism, a second prism and an output coupling mirror which are sequentially arranged along a preset central axis. The chipset comprises N gain chips, and the N gain chips output N sub light beams; the N sub-beams pass through the first prism, the sub-beams emitted from the first prism converge towards a preset central axis, the sub-beams are incident to the second prism before convergence and are combined into a resonant beam through the second prism, the resonant beam resonates in a resonant cavity formed by the output coupling mirror and the chip set, and the output coupling mirror and the chip set form a resonant cavity; the output laser is emitted from the output coupling mirror; wherein N is greater than 1. The invention is beneficial for solving the problems that the power of a single chip is limited, the beam combining efficiency is low, only incoherent beam combining can be realized, and a multi-chip beam combining structure is complex.

Provided are an apparatus and method for operation of an apparatus in a wireless communication system. The apparatus may be a UE, a chipset, or a base station. The UE receives an FD configuration message notifying a full duplex symbol from among a plurality of symbols, receives a cell-specific common TDD configuration message, and receives a UE-specific dedicated TDD configuration message. Here, only for the full duplex symbol from among the plurality of symbols, second direction information notified by the dedicated TDD configuration message overrides first direction information notified by the common TDD configuration message.

The utility model discloses a cooling system for a stage lamp. The cooling system comprises a chip assembly. The radiator is connected with the chip assembly through a cooling pipeline, and a power source is arranged on the cooling pipeline; one end of the wavelength conversion assembly is connected with the chip assembly through a first backflow pipeline, and the other end of the wavelength conversion assembly is connected with the radiator through a second backflow pipeline. The radiator, the chip and the wavelength conversion assembly are connected into a circulating heat dissipation system through the cooling pipeline and the backflow pipeline, so that the chip and the wavelength conversion assembly can be cooled at the same time through one radiator, the usage amount of the radiator is reduced, and the heat dissipation efficiency is improved.

The invention provides a multi-chip stacking packaging structure, which reduces the overall packaging thickness, realizes unlimited intersystem spacing and multi-chip stacking, reduces the loss of electric signal transmission, and is low in production cost. The packaging structure comprises a first plastic package layer assembly which comprises a first plastic package layer, a plurality of thin first chip sets and at least one second chip, and the thickness of the second chip is relatively larger than that of each chip set in the first chip sets; the second plastic package layer assembly comprises a second plastic package layer, at least one third chip and a plurality of groups of giant metal convex columns; a high-sealing metal wiring layer; and a low-density metal wiring layer.

A processing unit can include a plurality of chiplets coupled in a cascade topology by a plurality of interfaces. A set of the plurality of cascade coupled chiplets can be configured to execute a plurality of layers or blocks of layers of an artificial intelligence model. The set of cascade coupled chiplets can also be configured with parameter data of corresponding ones of the plurality of layers or blocks of layers of the artificial intelligence model.

The invention relates to the field of electrical engineering, and discloses a high-luminous-efficiency LED street lamp based on multi-chip combination and a luminous flux improving method thereof, and the method comprises the steps: obtaining photoelectric parameter data, carrying out the classification modeling of chips, and constructing a light source feature database; self-adaptive parameter extraction is carried out on the light source feature database, a cooperative work model is constructed, the chip load state is adjusted through a current sharing control strategy, and the chip heat distribution change condition is monitored in real time; whether the working state is stable or not is judged based on the heat distribution change condition, and if the working state is stable, stage change data of luminous flux output is recorded, and a chip driving strategy is corrected; according to the corrected chip driving strategy, spatial distribution regulation and control and energy efficiency optimization are carried out on output luminous flux, regulation factors are extracted, a light emitting path and heat dissipation intensity are adjusted, and luminous efficiency balance improvement is carried out; and evaluating the luminous flux output effect based on the luminous efficiency balance improvement result, and generating a working state evaluation report and a luminous flux improvement suggestion.