2431 results about "Chipset" patented technology

The invention relates to the technical field of computer programming languages, and particularly discloses a coal-fired power plant safety monitoring system and method. The system comprises a multi-modal data fusion platform, a federal learning agent network and a digital twinborn simulation engine. The edge computing node carries out unified acquisition and feature extraction on multi-source heterogeneous data through multi-protocol conversion, quantum noise suppression and a preprocessing chipset; the multi-modal data fusion platform realizes semantic mapping based on a knowledge graph, and fuses time-space correlation characteristics of data such as an infrared image and gas concentration by adopting a time-space encoder and a cross-modal attention mechanism. According to the method, the problems of early warning delay and high false alarm rate caused by low multi-source data decentralized processing efficiency and insufficient nonlinear correlation analysis in a traditional scheme are solved, efficient data fusion, complex risk accurate prediction and automatic safety response are realized, and the real-time performance and reliability of a coal-fired power plant monitoring system are remarkably improved.

The invention relates to the technical field of chip testing, in particular to a chip testing method and a chip testing system. The method comprises the following steps: acquiring a thermal imaging image of a working state of a chip; global color temperature offset optimization is carried out on the thermal imaging image of the working state of the chip, and spatial heat distribution mining is carried out, so that a chip heat distribution diagram is constructed; performing multi-moment heat distribution tracking processing on the chip heat distribution diagram, performing dynamic heat distribution evolution fitting, and constructing a dynamic heat distribution trend evolution diagram; acquiring a high-definition image of a to-be-tested chip; performing chip assembly visual monitoring on the high-definition image of the to-be-tested chip, performing heat distribution trend rendering based on the dynamic heat distribution trend evolution graph, and constructing a chip assembly heat distribution trend rendering model. According to the invention, through limit working condition test analysis, the evaluation efficiency and accuracy of the chip performance are improved.

A device and a method for operating a device in a wireless communication system are provided. The device may be a terminal, a chipset, or a base station. The base station may inform the terminal of a first time resource operating in half duplex and a second time resource operating in full duplex. In addition, a first bandwidth part (BWP) set in which the terminal operates in the first time resource and a second BWP set in which the terminal operates in the second time resource may also be informed. When switching between the first time resource and the second time resource occurs, the terminal can operate in the corresponding BWP without additional signaling indicating a BWP change.

A device and a method for operation of a device in a wireless communication system are provided. The device may be a terminal, a chipset, or a base station. A terminal receives, from a base station, a CSI-RS configuration message indicating CSIRS frequency resources in which a CSI-RS is transmitted, and a full duplex configuration message indicating an FD time resource operating in full duplex and at least one of a DL frequency resource used in downlink in the FD time resource and a UL frequency resource used in uplink, and then determines whether to measure the CSI-RS, on the basis of the CSI-RS configuration message and the full duplex configuration message.

The invention discloses a multichannel electrophysiological signal acquisition system and an acquisition method thereof, and the multichannel electrophysiological signal acquisition system comprises a power supply module electrically connected with a controller, an analog front-end chipset, a filter module and an analog-to-digital conversion module; the analog front-end chip set is used for acquiring an analog signal and preprocessing the analog signal; the pre-processed analog signal is converted into a digital signal through a filter module and an analog-to-digital conversion module, and the digital signal is transmitted to a controller; the filter module is used for filtering and denoising; the timer module connected with the controller generates a sampling frequency, transmits the sampling frequency to the analog-to-digital conversion module, and provides a time sequence signal for the analog-to-digital conversion module. The invention discloses a multi-channel electrophysiological signal acquisition system, which solves the problem of synchronous sampling time sequence control of a high-density electrode array and eliminates signal phase deviation caused by clock jitter among multiple channels under the constraint of maintaining the total power consumption of the system. And real-time power frequency interference suppression is realized.

Provided are a device operation method and a device in a wireless communication system. device may be a terminal, a chipset, or a base station. The terminal receives a CSI-RS configuration message, notifying CSI-RS frequency resources on which a CSI-RS is transmitted, and a full duplex configuration message, notifying an FD time resource operating at full duplex and at least one of a DL frequency resource used for downlink and a UL frequency resource used for uplink in the FD time resource, from the base station, and then receives and measures the CSI-RS. The terminal receives / measures the CSI-RS on the basis of a corresponding method at the FD time resource and a time resource other than the FD time resource.

The invention discloses an implementation method of a multi-chip high-density connection photoetching technology, an implementation method of a photoetching technology for multi-chip interconnection, a chip-level chip interconnection method, a manufacturing method of a mask plate line and photoetching equipment. The implementation method of the multi-chip high-density connection photoetching technology comprises the following steps: selecting a first mask plate to align and expose with a first original pattern unit in a first M * N chipset through a second alignment mark, and transferring a pattern of the first mask plate to an exposure area covering the first original pattern unit; longitudinally moving the substrate by M times of the longitudinal size of the original pattern or transversely moving the substrate by N times of the transverse size of the original pattern to execute alignment exposure, and completing exposure of corresponding areas of other M * N chip groups; and other masks are selected to repeatedly perform exposure on other corresponding pattern units of the first M * N chip set, and longitudinal movement or transverse movement is repeatedly performed to complete exposure of corresponding areas of the corresponding pattern units in other M * N chip sets. According to the scheme, high-density interconnection of multiple chips is realized.

The invention discloses a model processing method, a chip assembly and equipment. The method comprises the following steps: an in-memory computing element performs first operation processing on input data to obtain first processing data; wherein the first operation processing comprises fixed weight calculation of an operand; the near memory computing element performs second operation processing on the first processing data to obtain second processing data; wherein the second operation processing at least comprises attention calculation of operand change. Thus, heterogeneous deployment of model parameters of the model can be realized based on cooperation of the in-memory computing element and the near-memory computing element, the in-memory computing element can realize weight calculation of fixed operands, and the near-memory computing element can realize attention calculation of operand changes. The characteristics of high computing power efficiency and low power consumption of the in-memory computing element can be utilized to the greatest extent, the erasing operation on the in-memory computing element can be reduced by means of the near-memory computing element, and the application performance of a model deployed on the equipment side can be effectively improved.

The invention relates to the technical field of semiconductors, particularly provides an IGBT and silicon carbide MOSFET hybrid parallel power module, a motor controller and a vehicle, and aims to solve the problems of high cost and low yield of a power module manufactured by a full silicon carbide MOSFET chip. In order to achieve the purpose, the IGBT and silicon carbide MOSFET hybrid parallel power module comprises a mounting base, semiconductor modules distributed in an array mode are arranged on the mounting base, each semiconductor module comprises an upper bridge arm mechanism, a lower bridge arm mechanism and a substrate, and the upper bridge arm mechanisms and the lower bridge arm mechanisms are connected in series to form a half-bridge structure; the upper bridge arm mechanism comprises an IGBT chipset, a silicon carbide MOSFET chipset and an upper bridge gate signal terminal; a gate of the silicon carbide MOSFET chip of the upper bridge arm mechanism and a gate of the IGBT chip are connected with the upper bridge gate signal terminal; the lower bridge arm mechanism comprises an IGBT chip set, a silicon carbide MOSFET chip set and a lower bridge grid signal terminal. A grid of the silicon carbide MOSFET chip of the lower bridge arm mechanism and a grid of the IGBT chip are connected with the lower bridge grid signal terminal.

A method of configuring a robot of a fleet of robots for use of an AI chipset includes receiving a request for a robotic fleet to perform a job. The method includes defining a set of tasks that are to be performed by the robotic fleet in performance of the job. The method includes assigning at least one task of the set of tasks to a robot. The method includes determining a configuration for the robot based on the assigned task and a components inventory that indicates different components that can be provisioned to the robot including at least one AI chipset, and for each component, a set of extended capabilities and a status of the component. The method includes configuring the robot based on the determined configuration to use the at least one AI chipset. The method includes deploying the robotic fleet to perform the job.

A method or system for implementing a machine learning pipeline on a chipset comprising a plurality of hardware compute elements. The system accesses a hardware-agnostic functional description of the machine learning pipeline, wherein the description specifies a plurality of functional modules, including at least one machine learning model. Hardware specifications of the chipset are accessed to identify the available hardware compute elements. Based on the hardware specifications, the functional modules are synthesized into a plurality of interconnected executable components configured to execute on at least two different hardware compute elements. An implementation package is generated, comprising the executable components and metadata describing interconnections between them. The implementation package is then deployed to the chipset, where the executable components are executed by the identified hardware compute elements.

The utility model discloses a liquid drop preparation instrument and an antibody screening device, and the liquid drop preparation instrument comprises a chip assembly which comprises a liquid drop generation chip and a liquid drop sorting chip, and the liquid drop sorting chip comprises a sorting electrode; the sample table is used for placing at least one of the liquid drop generating chip and the liquid drop sorting chip; the optical module is optically coupled with the sample table and is used for providing incident light to the sample table and collecting an optical signal generated by the biological sample or the liquid drop in response to the incident light; the liquid path system is in operable conduction with the chip assembly and is used for pumping a solution to the liquid drop generating chip or the liquid drop sorting chip; the control circuit can selectively call a first group of control parameters or a second group of control parameters, the first group of control parameters comprises a first control instruction, and the second group of control parameters comprises a second control instruction; the control circuit comprises a feedback control sub-circuit used for controlling the sorting electrodes. According to the liquid drop preparation instrument, liquid drop preparation can be carried out, and needed liquid drops can be rapidly sorted out.

The invention discloses a modified maleimide prepolymer, a resin composition and application thereof, the modified maleimide prepolymer is an amine compound modified maleimide prepolymer and is generated by a prepolymerization reaction of maleimide resin and an amine compound, and the weight ratio of the maleimide resin to the amine compound is 100: (1-120); according to the invention, the maleimide resin is modified by a compound containing a special aliphatic ring and aromatic amine structure, and due to the existence of the aliphatic ring or olefin structure, the dielectric property, the water absorption rate and the like of bismaleimide can be reduced; the structure has an excellent thermal expansion coefficient and can meet the requirement of high-order packaging; according to the present invention, the product has characteristics of high temperature resistance, no volatile low molecular substance generation during the reaction process, stable molecular structure and high thermal decomposition temperature, can completely meet the multi-chip assembly manufacturing process requirements in the large-scale integrated circuit, and can obtain the cured product with characteristics of high heat resistance, high toughness, low CTE, low dielectric property and low water absorption rate, and the obtained cured product has characteristics of high heat resistance, high toughness, low CTE, low dielectric property and low water absorption.

The invention discloses a photoetching technology implementation method for multi-chip high-density connection, a chip-level chip interconnection method, a mask plate line manufacturing method and photoetching equipment, and the photoetching technology implementation method comprises the following steps: selecting a first mask plate, and aligning and exposing the first mask plate and a first original pattern unit through a second alignment mark, transferring the first mask pattern to a first exposure area; longitudinally moving the substrate by M times of the longitudinal size of the original pattern for alignment exposure, and transversely moving by 1 time of the transverse size of the original pattern for alignment exposure to complete exposure of other M * 1 chipset exposure areas; a second mask is selected to be aligned with the first original pattern unit for exposure through a second alignment mark, and a second mask pattern is transferred to a second exposure area; and transversely moving the substrate by N times of the transverse size of the original pattern for alignment exposure, and longitudinally moving by 1 time of the longitudinal size of the original pattern for alignment exposure, thereby completing exposure of other 1 * N chipset exposure areas. According to the scheme, high-density interconnection of multiple chips is realized.

The invention relates to the technical field of integrated circuit board finished product detection, in particular to a computing processing module finished product monitoring method and system, and the method comprises the steps: scanning a plurality of computing processing module finished products passing through a finished product conveying belt in real time through a linear array laser scanner disposed above the finished product conveying belt, and carrying out the real-time monitoring of the plurality of computing processing module finished products; further obtaining a spectrum pattern corresponding to each calculation processing module finished product; identifying local spectrum patterns corresponding to the plurality of chip assemblies in the spectrum pattern; and sequentially detecting whether each local spectrum pattern has a plane flaw, if so, evaluating the damaged surface of the plane flaw, and evaluating the damage degree of the damaged chip assembly based on the proportion of the damaged surface. According to the monitoring method, the spectral pattern representing the height information is generated in real time through the linear array laser scanner, the local areas of the multiple chip assemblies are accurately recognized in combination with the RGB color threshold value and the image feature extraction algorithm, interference caused by dense arrangement of the multiple assemblies is effectively avoided, and the positioning precision and the anti-noise capacity of plane defect detection are improved.

An operating method of a device in a wireless communication system, and the device are provided. The device can be a terminal, a chipset, or a base station. The terminal receives first PUCCH resource configuration information and second PUCCH resource configuration information, which are independent of each other, and applies the first PUCCH resource configuration information or the second PUCCH resource configuration information to each of a plurality of slots so as to transmit a PUCCH through the plurality of slots. The first PUCCH resource configuration information or the second PUCCH resource configuration information is applied to the specific slot on the basis of whether a specific slot from among the plurality of slots is a half duplex slot or a full duplex slot.

The invention provides a PTC heater output power closed-loop control method and device, the method is applied to an MCU assembly of a PTC heater output power closed-loop control system, and the PTC heater output power closed-loop control system comprises a driving chip, an IGBT assembly, a PTC heater and a sampling circuit. According to the embodiment of the invention, when the updated power difference value is greater than the second preset power value, the power difference value is updated; and performing preset processing based on the updated power difference value and a closed-loop control algorithm to obtain a first duty ratio adjustment parameter, controlling the IGBT assembly to start the PTC heater according to the first duty ratio adjustment parameter by the driving chip so as to adjust the output power value of the PTC heater in real time, and returning to execute acquisition of a plurality of sampling values acquired by the sampling circuit. And performing preset calculation processing on the plurality of sampling values to obtain a sampling power value until the sampling power value reaches a target power value, thereby realizing a power closed loop and ensuring the stability of an output power value.

The invention discloses an orthogonally stacked double-sided cooling power module and a preparation method thereof. The orthogonally stacked double-sided cooling power module comprises a decoupling capacitor, a copper-clad ceramic substrate, a power chip and a metal cushion block, the metal cushion blocks and the power chips are stacked and connected layer by layer in a metal cushion block-power chip-metal cushion block mode to form a series chipset, and the copper-clad ceramic substrate is connected with the two sides of the metal cushion blocks in the series chipset and is perpendicular to the power chips. According to the invention, through the cooperative effect of orthogonal stacking packaging and double-face cooling of the double copper cushion blocks, the electrical and thermal performance of the cooling power module is cooperatively optimized, the parasitic inductance of the power module is significantly reduced, the transient over-current supporting capability is significantly improved, and the packaging technology has good flexibility and is suitable for large-scale production. The method is suitable for power modules of different packaging types.

The invention provides a dual-pressure-point terahertz chip, a dual-pressure-point terahertz assembly and a preparation method. The double-pressure-point structure of the double-pressure-point terahertz chip comprises a substrate, a signal bonding pad and two ground bonding pads symmetrically arranged on the two sides of the signal bonding pad. The signal bonding pad comprises a first signal bonding pad and a second signal bonding pad, the first signal bonding pad is close to the edge of the dual-pressure-point terahertz chip, and the second signal bonding pad is close to the interior of the dual-pressure-point terahertz chip; the width of the second signal bonding pad is smaller than that of the first signal bonding pad; the two ground bonding pads are special-shaped bonding pads, each of the two ground bonding pads comprises a first part and a second part which are connected with each other, the first part is close to the edge of the dual-pressure-point terahertz chip, one end of the second part is connected with the first part, and the other end of the second part is gradually close to the second signal bonding pad; the minimum distance between the second portions of the two ground bonding pads and the transverse central axis of the second signal bonding pad is smaller than the probe distance, and the maximum distance is larger than the probe distance. According to the invention, the parasitic inductance of the terahertz chip can be reduced.

The invention provides a millimeter wave regular modular sparse active phased-array antenna which comprises a comprehensive mother board which is provided with a radio frequency power synthesis / distribution network, a component control network and a component power supply network. The plurality of sparse antenna modules are arranged above the comprehensive mother board; the chip assembly is arranged below the comprehensive mother board; the digital and power supply unit is arranged on the side, away from the comprehensive mother board, of the chip assembly and comprises a phased array wave control module and a power supply module, and the phased array wave control module is connected with the system master control and assembly control network; the power supply module is connected with a system power supply and a power supply network; the sparse antenna module and the comprehensive mother board are vertically stacked, and vertical interconnection is realized through a plurality of layers of PCBs; the integrated mother board is vertically connected with the digital and power supply unit through a plug-in low-frequency connector. According to the invention, decoupling of the integrated antenna can be realized; the sparse antenna module adopts sparse active feed, so that the number of array active channels and the heat flux density can be effectively reduced, and the system cost is effectively reduced.

The invention relates to the technical field of chip testing equipment, in particular to automatic unmanned linear testing equipment which comprises a workbench, a two-axis transfer machine is arranged on the upper side of the workbench, a material moving mechanism is arranged on the side face of the two-axis transfer machine, and a detection mechanism is arranged at the position, corresponding to the material moving mechanism, of the upper side of the workbench. A conveying line is arranged in the workbench, a lifting push rod is arranged on the side face of the conveying line, a lower visual detector is arranged on the side face of the two-axis transfer machine, loading mechanisms are arranged on the upper side of the conveying line at equal intervals, and chip assemblies are arranged in the loading mechanisms. The chip type and the installation direction are determined through cooperation of suction and clamping, and after confirmation, close contact testing can be carried out on different chips in a cooperation mode, so that part of small-batch chips do not need to be used in a matched mode by replacing different material plates, the material plates can store materials completely during testing each time, a testing circuit board does not need to be replaced, and the detection efficiency and speed are improved.

Multi-die bridge assemblies and methods for three-dimensional packaging. The architectures assemble a bridge component with two or more integrated circuit die to thereby create a multi-die (MD) bridge assembly. The means for attaching the bridge component to the dies can be hybrid bonding, solder bumps, thermal compression bonding, or a combination thereof. The created MD bridge assembly can be subjected to performance testing prior to attachment to a substrate. Attaching the MD bridge assembly to the substrate can include fitting the bridge component portion into a cavity in the substrate and attaching the bridge component to a cavity floor with another plurality of attachment options.

A semiconductor package includes a package substrate, a first group of semiconductor chips disposed on the package substrate and including at least two lower semiconductor chips that are sequentially stacked and are offset in a first horizontal direction, a second group of semiconductor chips stacked on the first group of semiconductor chips and including at least two upper semiconductor chips that are sequentially stacked and are offset in a direction opposite to the first horizontal direction, first bonding wires electrically connecting the chip pads of the first group of semiconductor chips to first substrate pads of the package substrate, second bonding wires electrically connecting the chip pads of the second group of semiconductor chips to second substrate pads of the package substrate and a molding member covering the first group of semiconductor chips and the second group of semiconductor chips on the package substrate.

The invention provides a chip assembly and a consumable box set, and relates to the technical field of printing imaging. The consumable box set is used for being in contact with contact pins of printing equipment and receiving printing signals, the printing equipment is provided with at least one first contact pin set and at least one second contact pin set, the first contact pin set and the second contact pin set are not overlapped, a first consumable box of the consumable box set is matched with the first contact pin set, the first consumable box is provided with a first electronic module, and the second consumable box is provided with a second electronic module. The first electronic module is electrically connected with at least one first contact part, and the first contact part is in contact with the first contact pin group to receive a first electric signal; the second consumable box is matched with the second contact pin group and is provided with a second electronic module, the second electronic module is electrically connected with the first electronic module, and the second electronic module receives the first electric signal through the first contact part. According to the invention, the risk of short circuit can be reduced, and normal use of the chip assembly is ensured.

Systems, devices, and methods for disaggregating networking components are provided. An example networking chassis includes a first disaggregated server device supported by the networking chassis that includes a first central processing unit (CPU) and a first graphics processing unit (GPU) coupled with the first CPU. The networking chassis further includes a first insertable switch module communicably coupled with the first disaggregated server device that includes first switching chipsets and a first fabric management controller coupled with the first switching chipsets. The first insertable switch module at least partially controls data transmission associated with the first disaggregated server device. The first GPU of the first disaggregated server device is isolated on the first disaggregated server device, supported on the first disaggregated server device in the absence of other GPUs, or is otherwise the only GPU on the first disaggregated server device so as to provide modularity in networking applications.

The invention belongs to the technical field of mechanical measurement and automatic control, and particularly relates to an underground drilling tool vibration monitoring and restraining system based on a multi-chip assembly. The system comprises a data acquisition part, a data analysis part and a vibration suppression part, the data acquisition part is used for arranging a plurality of vibration sensors on a drill rod so as to obtain vibration signals at different positions and at different moments on the drill rod, preprocessing the vibration signals and evaluating local energy of each position at the same time; the data analysis part is used for describing drilling tool vibration propagation by adopting a one-dimensional rod piece vibration model to obtain error feedback; according to error feedback, decomposing space vibration into a plurality of independent vibration modes; and the vibration suppression part is used for reducing the overall vibration level by applying a suppression control force so as to ensure that each vibration mode is effectively suppressed. The real-time performance and the data precision of vibration monitoring are improved, and equipment abrasion and safety risks caused by vibration are effectively reduced.

A data access method, comprising: receiving a first data access instruction from an upper-level chip; determining a new access address on the basis of an access address in the first data access instruction and address space information of a current chip; and updating the access address in the first data access instruction to the new access address, and then sending to the next-level chip the first data access instruction after update so as to access target data. According to the data access method, cross-chip data access in a multi-chip cascading mode can be realized, and a cascade chip group having a larger addressable range can be flexibly constructed according to requirements, so as to meet different product or application requirements. Further disclosed are a multi-chip cascading method and system, a device, and a storage medium.

The embodiment of the invention provides a light-emitting diode chip set, a backlight module of a display and an illumination module, and relates to the technical field of semiconductors, the light-emitting diode chip set generates white light and comprises at least one multi-wavelength chip, the multi-wavelength chip comprises an N-type semiconductor layer, a P-type semiconductor layer, a first light-emitting layer and a second light-emitting layer, wherein the first light-emitting layer and the second light-emitting layer are arranged between the N-type semiconductor layer and the P-type semiconductor layer and are stacked. The first light-emitting layer generates light of a first wave band through electroluminescence and excites the second light-emitting layer to generate light of a second wave band, the number of wavelengths contained in the light of the first wave band and the number of wavelengths contained in the light of the second wave band are both larger than or equal to 1 and smaller than or equal to 10, and a hole isolation area exists between the first light-emitting layer and the second light-emitting layer. The multi-wavelength chip has higher external quantum efficiency, the limitation of a traditional white light scheme (blue chip + yellow fluorescent powder or blue chip + green fluorescent powder + red fluorescent powder) can be broken through, the reliability is improved, and the service life is prolonged.

The invention discloses a 3D multi-core chip dual-channel heat dissipation device based on TSV adapter plate flip-chip bonding. The 3D multi-core chip dual-channel heat dissipation device comprises a manifold micro-channel module, a multi-chip assembly, heat-conducting glue and a shell. The manifold micro-channel module comprises an upper cover plate, a manifold substrate and a micro-channel plate from top to bottom; the multi-chip assembly is packaged by flip-chip bonding and comprises a multi-core chip with a plurality of hot spot areas, a TSV adapter plate and a uniform heat source chip. According to the invention, the manifold micro-channel module with a mixed structure is adopted, the flow path and the pump work can be reduced, the multi-core chip with a plurality of hot spot areas can be effectively cooled, meanwhile, the micro-channels are directly etched on the TSV adapter plate, the contact thermal resistance is reduced, the embedded cooling is realized, the heat dissipation efficiency of the vertical interconnection chip is greatly improved, and the service life of the vertical interconnection chip is prolonged. The double heat dissipation channels solve the problem that the heat dissipation of the 3D multi-core chip packaged by flip chip bonding based on the TSV adapter plate is difficult.

The invention provides a high-reliability high-density three-dimensional integrated multichannel millimeter wave transceiving integrated radio frequency micro module, which adopts three-dimensional ceramic packaging as a packaging body and comprises an amplitude-phase unit and a transceiving unit, and the two units and a cover plate realize electrical vertical interconnection and airtight packaging through three-dimensional stacking. The micro module receives an input signal, the input signal enters a receiving channel after being selected by a switch, an amplitude-limiting low-noise chipset in the micro module carries out amplitude-limiting amplification on the received signal, then the received signal is output to an amplitude-phase multifunctional chip, and the received signal is synthesized and output after amplitude-phase adjustment and amplification. A transmitting input signal is input to the amplitude-phase multifunctional chip after being subjected to power division, is subjected to power amplification after being subjected to amplitude-phase adjustment and amplification, is selected by the transmitting-receiving switch, and is radiated and output through the antenna. A negative electricity protection circuit and a pulse modulation circuit are integrated in the micro module, and pulse control of transmitting and receiving work of the micro module is achieved. The micro module adopts a stepped heat dissipation technology of the chip, the substrate, the functional unit and the micro module, and has very strong practicability.