1502 results about "Interposer" patented technology

The invention provides a 2.5 D substrate manufacturing method and a packaging structure. The 2.5 D substrate manufacturing method comprises the following steps: providing a first carrier on which a metal part and an intermediate layer are mounted; a metal column is arranged in the intermediate layer; forming a protective layer covering the metal component and the interposer on the first carrier; a first recess is formed on the metal feature. The interposer and the protective layer are ground such that the interposer and protective layer surfaces are lower than the surface of the metal feature. Forming a first dielectric layer with a first opening on the surfaces of the intermediate layer and the protective layer; the first opening exposes the metal column. Forming a seed layer in the first opening; the seed layer extends to the surface of the metal part and fills the first groove. A wiring layer is formed on the seed layer. The bonding force of the seed layer and the first dielectric layer can be improved, the corrosion to the side wall of the interposer in the etching process is prevented, and the packaging quality and precision are improved.

A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

An apparatus includes an optical interposer including a first surface, a first mating protrusion extending outwardly from the first surface, and two or more alignment protrusions extending outwardly from the first surface. The first mating protrusion is to be partially disposed within a first recess formed in a second surface of a photonic integrated circuit (PIC) die when the first surface of the optical interposer opposes the second surface of the PIC die and respective distal surfaces of the two or more alignment protrusions contact the second surface of the PIC die. A first portion of an outer surface of the first mating protrusion is to contact a first side wall of the first recess and a second portion of the outer surface of the first mating protrusion is to oppose a second side wall of the first recess such that a second space is to be defined therebetween.

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

The invention relates to an optical engine and a forming method thereof, the optical engine comprises an adapter plate, an electric chip, an optical chip and a packaging substrate, the adapter plate comprises a first surface, a second surface opposite to the first surface, and a first through hole penetrating through the first surface and the second surface, the first surface of the adapter plate and the front surface of the electric chip are mounted on the optical chip and are electrically connected with the optical chip, and the second surface of the adapter plate is mounted on the packaging substrate and is electrically connected with the packaging substrate. According to the 3D fan-out type packaging optical engine integrated with the TSV adapter plate, the problems that an existing 3D fan-out type packaging optical engine is large in module size and cannot support the extremely high number of channels can be solved at the same time, and the problems that an existing 3D integrated optical engine with the TSV is high in cost and chip incoming materials are fixed can be solved at the same time.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

The invention discloses a preparation method and structure of an interposer embedded with a silicon bridge and a high-density silicon capacitor, and belongs to the field of advanced packaging of integrated circuits. The method can be used for 2.5 D advanced packaging high-density interconnection; the interposer structure comprises an interposer back RDL rewiring layer, an intermediate layer which is formed by embedding a silicon bridge and a high-density silicon capacitor by using a high-molecular epoxy resin material EMC, and an RDL rewiring layer on the front side of the interposer. High-density vertical interconnection between the upper RDL layer and the lower RDL layer is achieved through an electroplating ultrahigh copper column penetrating through the resin material, micron-level and submicron-level ultrahigh-density interconnection can be achieved through a silicon bridge embedded in the EMC resin, and high-performance packaging-level power supply decoupling can be achieved through a high-density silicon capacitor embedded in the resin. The preparation method of the structure is easy to implement, the cost is greatly reduced compared with that of the TSV silicon adapter plate interposer, and the method can be used for large-scale mass production of 2.5 D interposers.

The invention describes an apparatus that implements efficient coupling between a photonic integrated circuit (PIC) and a second optical element such as a fiber or laser, while at the same time allowing for efficient polarization management and / or optical isolation. It enables the packaging of PICs with large single mode fiber counts and in- and out-coupling of light with arbitrary polarization. The apparatus comprises a glass interposer that contains at least one polarization selective element together with a pair of lenses transforming a beam profile between the 2nd optical element and a polarization selective coupler on the PIC. The invention also comprises a method for fabricating the apparatus based on a subassembly of building blocks that are manufactured using wafer-scale high-precision glass-molding and surface treatment(s) such as thin-film coating.

A plurality of processor dies may be attached to an interposer structure including interposer dielectric material layers having formed therein interposer metal interconnect structures, A dielectric matrix may be formed around the plurality of processor dies over the interposer structure. A router die may be attached to the plurality of processor dies. The router die includes router dielectric material layers having formed therein router metal interconnect structures and a router substrate having formed therein router through-substrate via structures therein. A backside of the router substrate may be thinned to expose end surfaces of the router through-substrate via structures. Memory dies may be attached to the router substrate after thinning the backside of the router substrate. Bonding pads of the memory dies are electrically connected to the router through-substrate via structures.

The invention provides an interposer and a preparation method thereof, and a photoelectric co-packaging structure, and the interposer comprises a substrate which comprises a glass substrate or a quartz substrate; the functional layer is arranged on the substrate, the refractive index of the functional layer is higher than that of the substrate, and the optical structure arranged on the functional layer at least comprises a micro-nano optical structure. The interposer realizes integration of an optical structure through the preset functional layer, and solves the problems of difficult micro-nano processing, difficult alignment, low integration level and the like of a glass material.

The invention relates to firmware partitioning for a GPU via a virtual SOC. One embodiment provides a graphics processor, the graphics processor comprising: an interpolator comprising a plurality of core grain sockets; a plurality of core particles coupled with the plurality of core particle sockets; and circuitry configured to provide a firmware super supervisor for causing the processing resources of the plurality of core particles to be dynamically divided into a plurality of partitions.

Embodiments herein relate to a semiconductor device which includes one or more voltage regulator (VR) chiplets coupled to a package interposer, where the package interposer includes coaxial magnetic composite core inductors to provide power to one or more load die. In one possible configuration, the one or more VR chiplets are coupled to the bottom side of the package interposer, the bottom side of the package interposer is coupled to the top side of a motherboard, and the one or more load die are coupled to the top side of the package interposer. In another possible configuration, the one or more VR chiplets are coupled to the bottom side of the package interposer, the top side of the package interposer is coupled to the bottom side of a motherboard and the one or more load die are coupled to the top side of the motherboard.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes an optical interposer having optical waveguides; a plurality of chip stacks disposed over the optical interposer, each of the plurality of chip stacks including a first photonic IC chip and a memory chip over the first photonic IC chip; and a plurality of first laser source chips disposed adjacent to the plurality of chip stacks, respectively, wherein the optical waveguides in the optical interposer are configured as an optical interconnect structure to couple with the memory chip through the first photonic IC chip.

Embodiments described herein may be related to apparatuses, processes, and techniques related to via structures and / or planar structures within a glass core of a substrate to facilitate high-speed signaling with a die coupled with the substrate. In embodiments, the substrate may be coupled with an interposer to enable high-speed signaling between a compute die (or tile) and a storage die (or tile) that may be remote to the substrate. Other embodiments may be described and / or claimed.

An electrical connector system includes a pluggable module having a module circuit board held by a module body, which includes guide lugs. The electrical connector system includes a circuit card assembly having a cage mounted to a host circuit board, a socket connector received in the cage, and an interposer received in the cage in a circuit stack. The cage has shielding walls forming a module channel. The cage includes guide rails interacting with the guide lugs to guide the pluggable module in the module loading direction. The guide rails include drop pockets configured to receive the guide lugs allowing the pluggable module to move in a contact mating direction transverse to the module loading direction when the guide lugs are received in the drop pockets to mate with the socket connector.

One embodiment provides a graphics processor comprising an interposer including a plurality of chiplet sockets, a plurality of chiplets coupled with the plurality of chiplet sockets, and circuitry configured to provide a firmware hypervisor to enable dynamic partitioning of processing resources of the plurality of chiplets into a plurality of partitions.

An information handling system main printed circuit board having a CPU couples to a graphics printed circuit board having a GPU with an interposer that includes contacts and wirelines that communicate signals between the separate boards. For example, an interposer couples to an upper and lower side of the main and graphics printed circuit boards to align spring contacts with contact pads of the main and graphics printed circuit so that signals are transferred through the interposer, which also provides a physical structure to define a motherboard with the assembly of the main and graphics printed circuit boards into a single piece.

In an embodiment, a semiconductor device may include an interposer. The semiconductor device may also include a plurality of chiplets directly bonded to the interposer. The device may furthermore include a plurality of interposer dies directly bonded to the interposer adjacent to the plurality of chiplets, the plurality of interposer dies having through-substrate vias. The device may additionally include a memory package over and bonded to at least one of the plurality of interposer dies.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

A chip and chiller assembly includes an active or passive interposer (114) having a front side and a back side. An integrated circuit chip (102, 112) is mounted on the rear side of the interposer (114). Each of the chips (102, 112) has a front side attached to the interposer (114) and a rear side facing away from the interposer (114). A gap (108) separates the chips (102, 112). The assembly also includes a frame (300) that is fitted into the gap (108) between the chips (102, 112). The frame (300) is CTE matched to the chips (102, 112). The frame (300) and the chip (102, 112) define a back side surface. A cooler module (200) is attached to the rear side surface. The cooler module (200) is in CTE match with the chips (102, 112). The chiller module (200) includes a microchannel chiller (202) disposed directly against a rear side of the chip and a manifold (204, 206) attached to the microchannel chiller (202) opposite the chip (102, 112). The manifolds (204, 206) are matched to the microchannel cooler (202) CTE.

The invention provides a 2.5 D interposer copper exposing process and a packaging structure. The 2.5 D interposer copper exposure process includes providing an interposer having conductive pillars; the interposer comprises a first surface and a second surface which are oppositely arranged; the edge of the first surface and the edge of the second surface are provided with a first groove and a second groove respectively, the depth of the first groove is H1, the depth of the second groove is H2, and the distance between the groove bottoms of the first groove and the second groove is H3. The groove bottom of the second groove is flush with the second end face. Grinding the second surface to expose the second end face; the grinding thickness is H2. The interposer is thinned from the second surface such that the protruding height of the conductive pillar is H3. And forming an electric connection part electrically connected with the conductive column. Therefore, the grinding thickness and the thinning thickness can be conveniently controlled, the consistency of the protruding heights of all the conductive columns is ensured, the subsequent wiring precision is favorably improved, and the packaging efficiency and the packaging quality are improved.

An integrated circuit (IC) layer stack is disclosed that integrates bypass chiplets in the IC layer stack without requiring fabrication of through-silicon vias (TSV) in a digital device for signals and power to a memory stack located above the digital device. Not requiring adding TSVs to an existing design high-performance digital device significantly reduces and / or eliminates digital device modification costs and time to manufacture new products consisting of three-dimensional stacked memory and digital device organizations. The bypass chiplets may be passive with just through conductors in silicon, or active with logic circuits therein. Flexibility of placement of the bypass chiplets in the IC layer stack in combination with an active interposer provides for many possible configurations of IC layer stacks. The digital device may be a microcontroller, a microprocessor, a PLA, an ASIC, a DSP, a GPU, a FPGA, neural processing unit, tensor processing unit, or any combination thereof.

A plurality of processor dies may be attached to an interposer structure including interposer dielectric material layers in which interposer metal interconnect structures are formed. A dielectric matrix may be formed around the plurality of processor dies over the interposer structure. A router die may be attached to the plurality of processor dies. The router die includes router dielectric material layers in which router metal interconnect structures are formed and a router substrate in which router substrate via structures are formed. A backside of the router substrate may be thinned to expose end surfaces of the router substrate via structures. Memory dies may be attached to the router substrate after thinning the backside of the router substrate. The bonding pads of the memory dies are electrically connected to the router substrate via structures.

An electrical connector structure, adapted for connecting an optoelectronic transceiver module on a mainboard, includes an interposer module and a fixing structure. The interposer module includes a first board and a second board assembled with each other, and at least a terminal module. A first terminal arm of the terminal module extends out of the first board, and a second terminal arm extends out of the second board. The fixing structure includes a pair of fixing walls, a plurality of first limiting members, and a second limiting member. The interposer module and the optoelectronic transceiver module are detachably arranged on the fixing structure and located on the mainboard, and the first limiting members press the second board, and the second limiting member presses the optoelectronic transceiver module, which in turn shortens a signal transmission path.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and an integrated circuit die, including a plurality of transistors, on the interposer. A carrier die is coupled to a top surface of the integrated circuit die. The integrated circuit die includes a plurality of top metal structures at a top surface of the integrated circuit die. The carrier die includes a plurality of dummy contact pads. The carrier die is bonded to the integrated circuit die by a bonding layer such that each dummy contact is positioned directly over one or more of the top metal structures with the bonding layer between them.

Provided are a package structure and a method of forming the same. The package structure includes an interposer at least including a first die sandwiched between a first redistribution layer (RDL) structure and a second RDL structure. The first die includes: a device layer disposed on a substrate; an inductor device disposed on the device layer; an internal RDL structure disposed on the inductor device; a plurality of conductive connectors disposed on the internal RDL structure; and an inductor contact disposed aside the inductor device and electrically connecting the internal RDL structure and inductor device. The internal RDL structure is configured to redistribute an electrical signal from the inductor contact to the plurality of conductive connectors, thereby preventing the electromigration (EM) failure.

An interposer is provided. The interposer includes a first redistribution structure; a device die on the first redistribution structure, the device die having a first surface facing the first redistribution structure and a second surface which is opposite to the first surface; a plurality of first connection members on the second surface of the device die; an insulating member disposed on the second surface of the device die and covering first portions of side surfaces of the plurality of first connection members; a plurality of second connection members on the first redistribution structure; a molding material disposed on the first redistribution structure and covering each of the device die, second portions of the side surfaces of the plurality of first connection members, the insulating member, and the plurality of second connection members; and a second redistribution structure on the molding material.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and an integrated circuit die on the interposer, the integrated circuit die including a plurality of transistors. The carrier die is coupled to a top surface of the integrated circuit die. The integrated circuit die includes a plurality of top metal structures at a top surface of the integrated circuit die. The carrier die includes a plurality of dummy contact pads. The carrier die is bonded to the integrated circuit die by a bonding layer such that each dummy contact pad is directly over one or more of the top metal structures with the bonding layer between the dummy contact pads and the top metal structures. Embodiments of the present disclosure also relate to a method of forming an integrated circuit package.

Embodiments disclosed herein include photonics packages. In an embodiment, the photonics package comprises a substrate. In an embodiment, a first interposer is over the substrate, and a first die is on the first interposer. In an embodiment, a second interposer is over the substrate, and a second die is on the second interposer. In an embodiment, an optical bridge is between the first interposer and the second interposer.