1100 results about "Interposer" patented technology

The invention discloses a preparation method and structure of an interposer embedded with a silicon bridge and a high-density silicon capacitor, and belongs to the field of advanced packaging of integrated circuits. The method can be used for 2.5 D advanced packaging high-density interconnection; the interposer structure comprises an interposer back RDL rewiring layer, an intermediate layer which is formed by embedding a silicon bridge and a high-density silicon capacitor by using a high-molecular epoxy resin material EMC, and an RDL rewiring layer on the front side of the interposer. High-density vertical interconnection between the upper RDL layer and the lower RDL layer is achieved through an electroplating ultrahigh copper column penetrating through the resin material, micron-level and submicron-level ultrahigh-density interconnection can be achieved through a silicon bridge embedded in the EMC resin, and high-performance packaging-level power supply decoupling can be achieved through a high-density silicon capacitor embedded in the resin. The preparation method of the structure is easy to implement, the cost is greatly reduced compared with that of the TSV silicon adapter plate interposer, and the method can be used for large-scale mass production of 2.5 D interposers.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

A method includes: forming an interposer die using a substrate, the interposer die including a plurality of conductive vias in the substrate; bonding the interposer die to a first redistribution layer (RDL); encapsulating the interposer die; forming a second RDL over the interposer die on a side opposite to the first RDL; bonding a first semiconductor die with one of the first RDL and the second RDL; and encapsulating the first semiconductor die.

Methods for fabricating flexible interposers for providing electrical connection between devices mounted at different vertical positions with respect to a substrate or a planar interposer. A bonded structure may comprise a bent flexible interposer extending from a first interposer portion between a main device on the substrate or the planar interposer and a second interposer portion above the main device and above or below a device positioned above the main device and electrically connected to the main device via a bent portion of the flexible interposer.

Methods, systems, and devices for pass-through power delivery for logic-on-top semiconductor systems are described. A semiconductor system may be configured with a two-dimensional pattern of power delivery conductors that pass through semiconductor components of a stack (e.g., through one or more memory stacks), providing a more-distributed delivery of power to a logic component bonded with the stack. The power delivery conductors may include through-substrate vias that bypass circuitry of the stack, and thus may be allocated for providing power to the logic component. Such techniques may be combined with a redistribution component, such as a package substrate or interposer (e.g., opposite the logic component in the heterogeneous stack), which may include redistribution conductors that convert from relatively fewer interconnections at a surface of the semiconductor system (e.g., for solder interconnection) to relatively more interconnections at a surface bonded with the stack (e.g., for hybrid bonding interconnection).

A semiconductor package may include a package substrate, a first interposer on the package substrate, a first semiconductor chip and a second semiconductor chip that are on the first interposer, a second interposer on the first semiconductor chip, a third semiconductor chip on the second interposer, and a first through via that extends into the first semiconductor chip and is between the first interposer and the second interposer.

A transceiver including an electronics integrated circuit (EIC), a photonics receiver integrated circuit (photonics RIC), a photonics transmitter integrated circuit (photonics TIC), and an interposer. The photonics RIC and TIC are each electrically coupled with the EIC. The photonics TIC is separate from the photonics RIC and includes at least one optical structure having a thin film lithium-containing (TFLC) electro-optic material. The interposer is coupled with the EIC, the photonics RIC, and the photonics TIC. The interposer is configured to route at least one of electrical or optical signals between at least two of the photonics RIC, the photonics TIC, or the EIC.

A structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. The interposer includes a dielectric layer and through vias penetrating through the dielectric layer. The first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation.

Described herein is a novel approach that leverages a 3D stacked die complex with an active optical interposer integrated with an I / O chiplet including high-speed serializer / deserializer (SerDes). By integrating silicon in this way, shoreline constraints are eliminated, allowing for the SerDes macros to be placed virtually anywhere on the I / O chiplet. The photonic-based interconnects described herein improve upon conventional approaches based on co-packaged optics (CPO), Linear-drive Pluggable Optics (LPO) and copper-based solutions in terms of bandwidth and power consumption. The interconnects described herein rely on photonic-electronic packages in which a PIC provides processing units (e.g., XPU), electronic switching chips or other types of application-specific integrated circuits (ASIC) with access to optical fiber-based networks while multiple SerDes provide high-speed serialization and deserialization.

A photonics package is described. The photonics package includes a thin film lithium-containing (TFLC) photonics integrated circuit (PIC), an additional integrated circuit, and an interposer. The TFLC PIC includes an electrode and a TFLC optical component. The TFLC component includes at least one TFLC electro-optic material. The interposer is coupled with the TFLC PIC and the additional IC. At least one of the TFLC PIC or the interposer is configured such that a portion of the TFLC PIC is separated from an other component by an air cladding region.

A semiconductor package includes an interposer, a lower semiconductor chip located on the interposer and including a chip through via, lower stack structures located on the interposer and spaced apart from the lower semiconductor chip in a horizontal direction, a lower molding layer located on the interposer, a redistribution layer located on the lower molding layer, the lower semiconductor chip, and the lower stack structures and electrically connected to the chip through via of the lower semiconductor chip, an upper semiconductor chip located on the redistribution layer and electrically connected to the redistribution layer, upper stack structures spaced apart from the upper semiconductor chip in the horizontal direction, located on the redistribution layer, and electrically connected to the redistribution layer, and an upper molding layer located on the redistribution layer and on side surfaces of the upper semiconductor chip and side surfaces of each of the upper stack structures.

An electronic module is provided that includes a microchannel cooler having a glass manifold contacting a first side of a microchannel chip, a plurality of functional semiconductor chips located face up on a second side of the microchannel chip. Each semiconductor chip of the plurality of functional semiconductor chips is coefficient of thermal expansion (CTE) matched, and a first redistribution layer (RDL) containing structure or organic interposer is located above and in electrical contact with the plurality of functional semiconductor chips. In either case, the first RDL containing structure and the organic imposer are not CTE matched to the functional semiconductor chips.

The invention provides a silicon bridge packaging structure, which reduces the thickness of an organic interposer, reduces the complexity of a process flow and reduces the packaging cost. The packaging structure comprises an organic interposer, the organic interposer comprises a metal bump which is arranged on the lower surface and protrudes downwards and a multi-layer metal circuit layer, and the upper surface, corresponding to the organic interposer, of the metal circuit layer is provided with a metal micro-bump structure used for being connected with a chip; the organic carrier plate comprises a plurality of first metal bonding pads arranged on the upper surface and second metal bonding pads arranged on the lower surface; a functional chip; and a silicon bridge chip.

Provided is an interposer comprising: one or more photonic waveguide; one or more microwave circuit; one or more optical interconnect; and one or more electronic interconnect, further configured to support a quantum sensor, and methods of operating and fabricating thereof. Further provided is a the interposer containing one or more classical sensors. Further provided is a network of quantum sensors supported by said interposers.

A method of forming an integrated circuit includes forming a sacrificial semiconductor nanostructure and a dielectric interposer adjacent to each other between two stacked channels of a gate all around transistor. The method includes forming an inner spacer in contact with the dielectric interposer. The channels are released by removing the sacrificial semiconductor nanostructure and the dielectric interposer.

A copper diffusion-suppressing electrical bond between a first semiconductor wafer or chip or interposer and a second semiconductor wafer or chip or interposer includes a first bond pad metal with a first bond pad metal surface disposed on the first semiconductor wafer or chip or interposer, bonded with a second bond pad metal with a second bond pad metal surface disposed on the second semiconductor wafer or chip or interposer. A copper outdiffusion-suppressing coating such as a titanium, cobalt, nickel / gold, or nickel / palladium / gold layer may be disposed on the first copper bond pad metal surface and / or on the second copper bond pad metal surface. The copper of the bond pad metal may be doped with manganese to form a copper outdiffusion-suppressing surface manganese oxide. The bond pad metal may alternatively be tungsten to prevent copper outdiffusion.

A bonded structure is disclosed. The bonded structure can comprise a first semiconductor element having a first contact pad. An interposer can include a second contact pad on a first side of the interposer and a third contact pad and a fourth contact pad on a second side of the interposer opposite the first side, the second contact pad bonded to the first contact pad; a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad. A switching circuitry can be configured to switch between a first electrical connection between the second and third contact pads and a second electrical connection between the second and fourth contact pads.

The present disclosure relates to example implementations of optically accessible circuit packages. For example, this disclosure includes implementations for creating a circuit package with a photonic integrated circuit (PIC) connected to electrical integrated circuit (EIC) components via an organic interposer. In many implementations, the circuit package maintains optical access to a gating coupler (GC) region on the PIC via an internal cavity area in the organic interposer. In this way, a fiber array unit (FAU) or other optical connection can couple to the circuit package to communicate data from the EIC components of the circuit package and another circuit package or an external device connected to the FAU (e.g., both send and receive data with the cp) via the open access GC region.

A semiconductor package includes a package substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness, and an interposer module mounted on the upper surface layer of the package substrate in the second surface area. The semiconductor package may also include an interposer including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness. The semiconductor package may also include an printed circuit board substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness.

A package includes an encapsulant having a first side and a second side opposite to the first side, a first integrated circuit die and a second integrated circuit die embedded in the encapsulant, and a first interposer on the first side of the encapsulant. The first interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The package further includes a second interposer on the second side of the encapsulant. The second interposer is mechanically and electrically coupled to the first integrated circuit die and the second integrated circuit die. The second interposer optically or electrically couples the first integrated circuit die to the second integrated circuit die.

A semiconductor module may include an interposer including an active local silicon interconnect (LSI) die, a first semiconductor die on the interposer, and a plurality of second semiconductor dies adjacent the first semiconductor die on the interposer and coupled to the first semiconductor die by the active LSI die. A method of forming a semiconductor module may include attaching an active local silicon interconnect (LSI) die to a carrier substrate, forming a molding material layer around the active LSI die, forming an upper redistribution layer (RDL) structure on the active LSI die and the molding material layer, attaching a first semiconductor die to the upper RDL structure; and attaching a plurality of second semiconductor dies to the upper RDL structure such that the plurality of second semiconductor dies is coupled to the first semiconductor die by the active LSI die.

A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.

A first device includes a transceiver to communicate with a second device over an interposer, the interposer comprising a plurality of conductive traces between the first device and the second device. The first device also includes control logic, coupled to the transceiver associated with the first device, configured to send first data to the second device over a conductive trace of the plurality of conductive traces, simultaneously receive second data from the second device over the conductive trace, and extract the second data from a combined signal comprising the first data and the second data.

A system board includes a module board that connects to the system board with an interposer having compressible connectors. The module board can further be covered by a shield that has a metal alloy having an element to provide good electrical conductivity and an element to provide structural integrity and heat transfer. The module board can further include gaskets to interconnect the shield to a ground plane of the module board. the interposer board can further include an extra column of ground connections to reduce signaling noise between the interposer board and the system board.

Semiconductor packages and methods of fabricating semiconductor packages include a package substrate having a recess formed in a surface of the package substrate and at least one channel in a bottom surface of the recess. The recess may be configured to accommodate a semiconductor device located over a surface of an interposer that is bonded to the package substrate. Accordingly, a minimum gap distance may be maintained between the semiconductor device and the package substrate, which may ensure that sufficient underfill material may flow between the semiconductor device and the package substrate and within the at least one channel, thereby improving of the structural coupling between the interposer and the package substrate, and reducing the likelihood of package defects, such as delamination, cracking, and / or popcorn defects.

A vertically stacked 3D integrated circuit structure includes at least two chiplets: a first chiplet formed from a non-diamond semiconductor material, a second chiplet formed from diamond. The diamond chiplet is positioned vertically relative to the first chiplet and is electrically coupled thereto. Thermal vias are formed through one or more of the non-diamond chiplets and include material to form heat extraction pathways. These thermal vias are thermally coupled to a heat-spreading structure, which may include the diamond chiplet, a diamond interposer, or an encapsulating diamond-based packaging layer.

A semiconductor package includes an interposer having a first principle surface and a second principle surface opposite the first principle surface. One or more semiconductor dies are disposed on the first principle surface of the interposer, and are electrically connected with the second principle surface of the interposer by electrical vias passing through the interposer. A heat spreading lid disposed over the one or more semiconductor dies. A thermally conductive material is disposed between the one or more semiconductor dies and the heat spreading lid. The thermally conductive material thermally couples the one or more semiconductor dies and the heat spreading lid. In some examples, the heat spreading lid may be a thermoelectric cooler. In some examples, the thermally conductive material may be a mixture of a gel and a liquid metal.

The invention relates to a high-temperature-resistant multi-mode flexible sensing array based on a rotary negative Poisson's ratio structure interposer and a preparation method and application thereof, and the sensing array comprises a top packaging layer, a temperature sensing layer, a negative Poisson's ratio structure interposer, a piezoelectric sensing layer and a substrate packaging layer which are sequentially stacked from top to bottom. The negative Poisson's ratio structure intermediate layer is made of a high-modulus flexible composite material and comprises a plurality of rigid rotating units and flexible connecting areas, and a rotating square negative Poisson's ratio microstructure is formed. A thermal resistance type temperature sensing unit of the temperature sensing layer is arranged on the upper surface of the rigid rotating unit and comprises a graphene conductive network. The piezoelectric sensing layer comprises a three-dimensional interconnected leadless piezoelectric ceramic skeleton and an array stretchable electrode, is packaged in a flexible polymer matrix, and is used for sensing mechanical deformation. Compared with the prior art, the multi-mode flexible sensing array has the decoupling capability, and a flexible multi-mode sensor which can independently output temperature and mechanical deformation signals can be realized.

The invention discloses an optical engine and a preparation method thereof. The optical engine comprises an interposer; the plurality of VCSELs are integrated on the intermediate layer through a flip-chip process and are used for emitting continuous wave laser signals with different wavelengths; the plurality of first optical waveguides are processed on the intermediate layer, each first optical waveguide comprises a light input part, an electro-optical modulation part and a light output part, the light input parts are optically coupled with the VCSEL, continuous wave laser signals are coupled into the first optical waveguides, the electro-optical modulation parts are used for performing electro-optical modulation on the continuous wave laser signals to generate first modulated wave laser signals, and the light output parts are used for outputting the first modulated wave laser signals to the VCSEL. The light output part is used for outputting a first modulated wave laser signal; and the wavelength division multiplexer is integrated on the intermediate layer and comprises a plurality of input ports and an output port, the input ports of the wavelength division multiplexer are optically coupled with the optical output part of the first optical waveguide, and the first modulated wave laser signals with different wavelengths are combined and output to an output optical fiber which is optically coupled with the output port of the wavelength division multiplexer.