169 results about "Interposer" patented technology

Provided are a semiconductor package including semiconductor devices sealed on an interposer and capable of improving heat dissipation characteristics and warpage, and a method of manufacturing the semiconductor package. The semiconductor package includes an interposer, a first semiconductor device arranged on the interposer, a second semiconductor device spaced apart from the first semiconductor device on the interposer, and a heat dissipation plate arranged on upper surfaces of the first semiconductor device and the second semiconductor device and having a dam arranged in an edge portion thereof.

An insertion instrument comprises an insertion portion including a bending portion provided at a distal end side of the insertion portion, a first wire provided in the insertion portion, and an operation portion provided at a proximal end side of the insertion portion. The operation portion includes a bending operation unit. The bending operation unit includes a lever having a central shaft defining a central axis, a rotor coupled to the lever, a wire attachment surface to which the first wire is attached. An inner surface of the operation portion includes a receiver body and a restriction body. The receiver body supports the rotor for rotation about the central axis and for movement of the lever from a neutral position to an inclined position, where, in the inclined position, the central shaft is inclined relative to the central shaft in the neutral position. Movement of the lever from the neutral position to the inclined position pulls the first wire to bend the bending portion. The restriction surface restricts a portion of the rotation of the rotor about the central axis.

Alignment marks on an interposer are formed within a chip area instead of in a wafer scribe line or die street. A through-substrate via (TSV) trench and at least one alignment mark trench are formed in a chip area of a substrate. The TSV trench and the at least one alignment mark trench are filled with a metal to form a filled TSV trench and the at least one alignment mark. The thickness of the substrate is reduced to form a through-substrate via (TSV) from the filled TSV trench. This reduces process defects during dicing and improves yield.

A package structure and a package method are provided. The package structure includes: a photonic interposer configured to be integrated with a photonic device, where a first surface of the photonic interposer includes an optical coupling area; a chip bonded on the first surface and arranged spaced apart from the optical coupling area, where the chip is electrically connected to the photonic interposer; a protective ring located on the first surface and surrounding the optical coupling area, where the protective ring includes a cavity exposing the optical coupling area; and a molding layer located on the first surface, on a side of the chip, and outside of the cavity, wherein the molding layer covers side walls of the chip and outer walls of the protective ring.

A semiconductor package includes a package substrate, an interposer on the package substrate and including first upper pads, the first upper pads including a first set of upper pads and a second set of upper pads, a first semiconductor chip on the interposer and comprising first lower pads respectively connected to the first set of upper pads, a plurality of first pins on a first top surface of the first semiconductor chip and substantially uniformly spaced apart by a first distance, and a plurality of second pins on the first top surface of the first semiconductor chip and substantially uniformly spaced apart by a second distance that is different from the first distance, where the first top surface of the first semiconductor chip includes a first region and a second region that does not overlap the first region.

A wafer-scale compute system integrates multiple semiconductor stacks on a monolithic passive silicon substrate patterned into mechanically isolated silicon islands interconnected through through-silicon vias and redistribution wiring layers. Etched silicon spring structures provide in-plane and out-of-plane compliance, enabling wafer-scale assembly without mechanical stress. The substrate includes redundant wiring and multiple regulated power domains supplied by vertical modules. All communication between stacks occurs through the silicon substrate, forming a contiguous all-silicon computational domain with no organic circuit boards or interposers. The architecture delivers zetta-scale performance with high yield and mechanical reliability.

The application provides a CPU post-silicon verification system and method, and relates to the technical field of post-silicon verification. The CPU post-silicon verification system comprises an editable CPU simulation component, an interposer, a socket and a verification platform, and the editable CPU simulation component, the interposer, the socket and the verification platform are electrically connected in sequence; wherein the interposer is used for mapping the signals of the editable CPU simulation component into preset CPU pin definitions; the editable CPU simulation component is used for performing read-write operations on the verification platform, and when the read-write operations are successful, it is determined that the verification platform is in a non-fault state. The CPU post-silicon verification system and method provided by the application have the advantage that the principle of the verification platform can be verified.

Radiofrequency systems for use in advanced driver assistance systems (ADAS) can include a mixture of high frequency (e.g., above 1 GHz) analog and components and lower-frequency digital devices mounted on one main circuit board. Cost savings can be achieved by providing high-frequency signal paths on an interposer circuit board that is mounted to the main circuit board and couples devices requiring high-frequency signalling (e.g., distributing a local oscillator signal to several devices forming part of a cascaded radar system). The interposer is fabricated from special purpose materials suitable for routing high frequency signals with low loss, while the main circuit board can be fabricated from commodity materials suitable for lower frequency applications.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an interposer having a first surface and a second surface parallel to the first surface; a conductive via extending between the first surface and the second surface of the interposer; an insulation layer separating the conductive via from the interposer; a first electronic component positioned on the second surface and electrically connected to the conductive via; a first conductive element positioned on the first surface of the interposer and electrically connected to the conductive via; a spacer conformally positioned on the first surface of the interposer and on sidewalls of the first conductive element; and a passivation layer positioned on the spacer. The passivation layer has a first dielectric constant, and the spacer has a second dielectric constant less than the first dielectric constant.

Decoupling capacitor structures, sacrificial component structures, and assemblies are provided. For example, a decoupling capacitor structure includes a first interposer having opposing first and second surfaces, and a decoupling capacitor having opposing first and second surfaces. The decoupling capacitor is disposed adjacent to the first interposer such that the first surface of the decoupling capacitor is adjacent to the second surface of the first interposer. A first external terminal and a third external terminal of the decoupling capacitor are formed on the first surface of the decoupling capacitor and are electrically connected to the first interposer. The decoupling capacitor structure may include a second interposer such that the decoupling capacitor is sandwiched between the first and second interposers. One or more decoupling capacitor structures can be disposed in a substrate to form a decoupling capacitor assembly, and multiple decoupling capacitor structures can be stacked to form a multilayer structure.

A semiconductor module can include an interposer including an active local silicon interconnect (LSI) die, a first semiconductor die on the interposer, and a plurality of second semiconductor dies on the interposer adjacent to the first semiconductor die and coupled to the first semiconductor die through the active LSI die. A method of forming a semiconductor module can include attaching an active local silicon interconnect die to a carrier substrate, forming a molding material layer around the active LSI die, forming an upper redistribution layer (RDL) structure on the active LSI die and the molding material layer, attaching a first semiconductor die to the carrier substrate; and attaching a plurality of second semiconductor dies to the upper RDL structure such that the plurality of second semiconductor dies are coupled to the first semiconductor die through the active LSI die.

A processor package includes an interposer; a memory on the interposer; a processor on the interposer; and an optical engine on the interposer, wherein the optical engine includes: a photonic integrated circuit chip including circuit elements, the circuit elements configured to perform photoelectric conversion, and a coupling structure on the photonic integrated circuit chip, the coupling structure configured to provide at least one of an optical input path or an optical output path, wherein the at least one of the optical input path or the optical output path is connected to the photonic integrated circuit chip, and wherein the coupling structure includes: a plurality of light output patterns including a dummy pattern and an effective pattern, and a mold layer on the dummy pattern.

An interposer may include a first metal trace located on a first dielectric layer, a second dielectric layer located on the first dielectric layer, a line-shaped via located in the second dielectric layer and connected to the first metal trace, and a second metal trace located on the second dielectric layer and connected to the line-shaped via.

A chip package and method for fabricating the same are provided that includes embedded off-die inductors coupled in series. One of the off-die inductors is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The other of the series connected off-die inductors is disposed in a substrate of the chip package. The substrate may be either an interposer or a package substrate.

This application discloses overhanging cache stacked chiplets on glass core. A three-dimensional L3 cache producing overhanging cache chiplet architecture. Examples stack cache dies on caches in a system die and hybrid bond (HB) them together, producing a "T" shaped assembly attached to a glass core interposer via a field of solder microbumps. The coefficient of thermal expansion (CTE) of the glass core interposer can be tailored in an application specific manner.

An apparatus is provided which comprises: an interposer comprising traces and conductive contacts on a first interposer surface and a second interposer surface opposite the first interposer surface, a computing device coupled with contacts on the first interposer surface, a first memory array coupled with contacts on the first interposer surface, and a second memory array embedded between the first interposer surface and the second interposer surface, the second memory array inverted in orientation relative to the first memory array, the second memory array directly coupled through traces in the interposer with the first memory array and the computing device. Other embodiments are also disclosed and claimed.

A device includes a die including a set of contacts coupled to a first side of the die. The die also includes an active circuit coupled to the set of contacts. The device also includes a thermal interposer (TIL) adjacent to the first side of the die. The TIL includes a thermally conductive material having one or more through-holes (THVs) aligned with one or more first contacts of the set of contacts. The device also includes a set of electrically conductive connections coupled to the one or more first contacts and extending through the THVs.

The present application relates to the field of advanced semiconductor packaging technology, and particularly relates to a borosilicate system TGV glass interposer composite interconnection structure for three-dimensional integrated circuit packaging and a preparation method and application thereof. The structure comprises a borosilicate glass interposer, a TGV through array penetrating the interposer, a low-loss insulation / adhesion layer arranged on the upper and lower surfaces of the interposer, a fine re-routed layer, a ground shielding via array and a thermal diffusion metal layer. By adopting borosilicate glass as the core material of the interposer, realizing vertical interconnection through TGV, constructing a ground shielding and power integrity enhancement structure around the high-speed signal channel, and introducing a thermal diffusion layer and a stress buffer insulation layer, the requirements of high-density interconnection, low insertion loss, low crosstalk, low warpage and high reliability can be met. The structure is suitable for three-dimensional packaging scenes such as AI accelerator, high-performance computing, radio frequency front end, co-packaged optical and high-reliability sensor.

A semiconductor structure includes: an interposer including an integrated passive device, a die-side redistribution structure, first on-interposer bump structures, and second on-interposer bump structures. First die-side redistribution wiring interconnects electrically connect electrical nodes within the integrated passive device to the first on-interposer bump structures. Second die-side redistribution wiring interconnects provide a respective electrical connection between a respective pair of second on-interposer bump structures. A first semiconductor die includes first on-die bump structures that are bonded to the first on-interposer bump structures through first solder material portions, and further includes second on-die bump structures that are bonded to the second on-interposer bump structures through second solder material portions. The first semiconductor die includes first metal interconnect structures providing electrical connections between a respective one of the first on-interposer bump structures and a respective one of the second on-interposer bump structures.

A baseboard system for an information handling system. The baseboard system includes a plurality of components and an opposing plane interposer system, the opposing plane interposer system including a primary circuit board, the primary circuit board including a plurality of slots and a primary landing pad portion, the plurality of slots being installed on a top side of the primary circuit board, the primary landing pad portion being installed on a bottom side of the primary circuit board; and, an integrated circuit interposer circuit board, the integrated circuit interposer circuit board including an integrated circuit component and an interposer landing pad portion, the integrated circuit component being installed on a bottom side of the integrated circuit interposer circuit board, the interposer landing pad portion being installed on a top side of the integrated circuit interposer circuit board.

A monolithic microwave integrated circuit (MMIC) device includes a MMIC die comprising, which includes an active circuit layer, a first substrate material, at least one conductive through-semiconductor via (TSV) extending completely through the first substrate material from a top side to a bottom side of the MMIC die. The MMIC device also includes a thermally conductive interposer which includes: a second substrate material different from the first substrate material and electrically insulating at an operating voltage of the MMIC die, at least one conductive via, pad, or trace in electrical contact with the at least one conductive TSV or the active circuit layer, and a pocket configured to receive the MMIC die.

A device includes an interposer, a package attached to a first side of the interposer, and a plurality of passive devices and external connectors attached to a second side of the interposer. The package includes an encapsulant and integrated circuit devices in the encapsulant. The interposer electrically connects the passive devices and external connectors to the integrated circuit devices. The external connectors are disposed outside a perimeter of the package in a top-down view.

A method comprising: bonding a first die (68) to a first side of an interposer (96) using first electrical connectors (77, 78); bonding a second die (88) to the first side of the interposer using second electrical connectors (77, 78); attaching a first dummy die (106) to the first side of the interposer adjacent to the second die (88); encapsulating the first die, the second die, and the first dummy die with an encapsulating agent (112); and singulating the interposer (96) and the first dummy die (68) to form a housing structure (200), wherein the singulating comprises sawing through the interposer (96) and the first dummy die (68) to form the housing structure, the dummy die (68) having a sidewall surface (106') that is flush with the lateral dimensions of the interposer (96).

A system comprises one or more processor cores, including a management processor core that executes instructions to partition at least a portion of the one or more processor cores into one or more partitions. The system includes at least one distributed virtual memory (DVM) hub that obtains a first DVM message from a processor core; determines, based on a processor core identifier of the DVM message, one or more recipient processor cores for the first DVM message; and provides the first DVM message to the one or more recipient processor cores. The system includes one or more interrupt interposers that are each associated with a processor core and prevent an interrupt originating from the associated processor core from being provided to a processor core that is outside the partition of the associated processor core.

A circuit board includes a first circuit base board, a second circuit base board, an annular interposer disposed between the first circuit base board and the second circuit base board, and a conductive element. A first annular groove of the first circuit base board has a first internal extension groove. A second annular groove of the second circuit base board has a second internal extension groove. The annular interposer is located in the first annular groove and the second annular groove. The conductive element is disposed in the first internal extension groove and the second internal extension groove and electrically connects the first conductive layer and the second conductive layer.

This invention provides a semiconductor device including an interposer and a plurality of memory dies. The interposer has a first surface and a second surface opposite to the first surface. The interposer includes a first bonding pad adjacent to the first surface. The plurality of memory dies are arranged in an array on the first surface of the interposer. Each of the plurality of memory dies includes a second bonding pad, and the second bonding pad is in direct contact with a corresponding first bonding pad.

Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. The multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.

This invention discloses a type 0-3 polymer ferroelectric composite material for use in integrated circuit interposers and its preparation method. The composite material consists of an epoxy resin matrix and KBiFe2O5 ferroelectric powder dispersed therein, with 100 parts by mass of epoxy resin and 5-50 parts by mass of KBiFe2O5. KBiFe2O5 has a layered perovskite structure and a low intrinsic dielectric constant (<3.5), and a coefficient of thermal expansion of only 1.6-10 ppm / K. Surface modification of the ferroelectric powder with a silane coupling agent can significantly improve its interfacial bonding strength with the epoxy resin. This invention utilizes a type 0-3 composite structure to achieve adjustable coefficient of thermal expansion of the composite material within the range of 3-20 ppm / K while maintaining a low dielectric constant (3.0-3.8@1 MHz) and low dielectric loss (<0.005@1 MHz), enabling good matching with silicon chips (CTE approximately 3-5 ppm / K) and effectively reducing thermal cycling stress. The composite material has a simple preparation process, is compatible with existing packaging production lines, and is suitable for use as an interposer material in three-dimensional integrated circuit packaging, showing promising application prospects.