26 results about "Land grid array" patented technology

An integrated device includes one or more dies and a substrate. The substrate includes on-package contacts coupled to the one or more dies and off-package contacts configured to be coupled to a printed circuit board (PCB). The integrated device also includes a first set of electrical interconnects electrically coupled to a first subset of the off-package contacts and that form a ball grid array (BGA). The integrated device also includes a second set of electrical interconnects electrically coupled to a second subset of the off-package contacts and that form a land grid array (LGA).

The invention relates to a loading mechanism for grid array packaging. A loading mechanism for a grid array (LGA) semiconductor package may include a backplane configured to be attached to a mainboard; a socket attached to a side of the main board opposite to the back board; and a load plate configured to fix the LGA semiconductor package in the socket. The load board may be removably coupled to the backplane and may include a contact interface extending from the load board and configured to contact the LGA semiconductor package when the LGA semiconductor package is loaded into the receptacle. The load plate may also include three or more spring elements configured to receive mechanical tolerances in one or more of the loading mechanism, the LGA semiconductor package, or the receptacle.

An assembled electro-optical switch module includes a package substrate. Four optical socket members are disposed respectively to the package substrate. Each optical socket member includes four sockets closely packed in a row. Each socket has a recessed flat region with topside land grid array (LGA) interposer connected to bottom side solder bumps and a side notch opening aligned to an edge of the package substrate at the corresponding edge region. Sixteen optical modules in four sets are co-packaged in the package substrate. Each set has four optical modules respectively seated in the four sockets of each optical socket member with top side LGA interposer. Four clamp latch members are applied to clamp each of the four sets of optical modules in respective optical socket members. A data processor device with 51.2Tbps data interface is disposed to the package substrate and electrically coupled to each of the sixteen optical modules.

Aspects of the disclosure relate to an electronic device package. The electronic device package can include a laminate substrate. The electronic device package can include connection pads disposed on the laminate substrate and along a perimeter of the electronic device package. Connection pads that are along a first side of the laminate substrate can have a first orientation that is different than a second orientation of connection pads that are along a second side of the laminate substrate. The first side can be adjacent to the second side. Each of connection pads can have a minimum size for Kelvin sensing in a process technology for manufacturing the electronic device package. The electronic device package can include a die enclosed within a packaging structure.

An electronic network device includes a package substrate, an Integrated Circuit (IC) mounted on the package substrate, and a plurality of interconnection terminals disposed on a surface of the package substrate. The interconnection terminals include multiple pairs of signal terminals and multiple ground terminals. The interconnection terminals are arranged in a hexagonal grid in which (i) a given interconnection terminal is surrounded by six other interconnection terminals, and (ii) propagation paths between signal terminals that do not belong to a same pair are at least partially blocked by the ground terminals.

Disclosed herein is a method for producing a land grid array (LGA) socket connector assembly and the resultant assembly. The method comprises providing a carrier having a first carrier thickness with an array of vias, each having a first diameter, providing pockets around top surfaces of the vias, each having a second diameter and creating a portion of the pockets having a second carrier thickness that is less than the first carrier thickness, providing socket contact springs, each comprising a hole support structure that supports the socket contact spring within the via, and a contact beam configured to contact a conductor of an integrated circuit to be placed within the socket connector assembly, wherein a portion of carrier having a first carrier thickness is configured to prevent the contact beam from inelastically deforming when bent under load. Alternately, a contact feature may be used to prevent the inelastic deformation.

An integrated device includes one or more dies and a substrate. The substrate includes on-package contacts coupled to the one or more dies and off-package contacts configured to be coupled to a printed circuit board (PCB). The integrated device also includes a first set of electrical interconnects electrically coupled to a first subset of the off-package contacts and that form a ball grid array (BGA). The integrated device also includes a second set of electrical interconnects electrically coupled to a second subset of the off-package contacts and that form a land grid array (LGA).

DSM-LGA using substrates with different surface finish options include copper posts for electrical communication. The copper posts include a height-to-width ratio that cannot be achieved in traditional copper posts, as well as a taper ratio that forms a more rectangular cross section as opposed to traditional copper posts. Additionally, by using copper, the copper posts include a relatively high thermal conductivity (as compared to solder), thus allowing the copper posts to dissipate thermal energy generated by integrated circuits and other processors. Copper posts can take the form of a single, cylindrical post. Alternatively, copper posts can be merged to form a variety of copper structures used for various applications, including I / O, grounding / isolation, and substrate support.

A microelectronic system may include a microelectronic component having electrically conductive elements exposed at a first surface thereof, a socket mounted to a first surface of the microelectronic component and including a substrate embedded therein, one or more microelectronic elements each having active semiconductor devices therein and each having element contacts exposed at a front face thereof, and a plurality of socket pins mounted to and extending above the substrate, the socket pins being ground shielded coaxial socket pins. The one or more microelectronic elements may be disposed at least partially within a recess defined within the socket. The socket may have a land grid array comprising top surfaces of the plurality of the socket pins or electrically conductive pads mounted to corresponding ones of the socket pins, and the element contacts of the one or more microelectronic elements may be pressed into contact with the land grid array.

Packages with wafer level land grid arrays are described. In an embodiment, a package includes a die and a package routing layer over the die, where the package routing layer includes a first land that spans over a first set of vias, and a second land that spans over a second set of vias, where the vias may be connected to a metal redistribution line or directly connected to die contact pad of the die.

A novel method and interface are provided to generalize power delivery (PD) solutions and allow OEMs and suppliers to easily replace PD solutions using the same design and layout without having to re-spin the motherboard. This is achieved by defining a new interface and ball-out which support dual port PD solution that meet the system requirements. The embodiments employ an interposer to unify different PD solutions. The interposer is part of a unique Land Grid Array (LGA) soldered down solution with pre-defined interface employing a generic pinout to support PD solutions for dual type-C ports from different vendors. The interposer includes an LGA having a pattern of pads that is coupled to a LGA on a platform PCB with a matching pattern.

A loading mechanism for a land grid array (LGA) semiconductor package can include a backplate configured to attach to a motherboard, a socket attached to the motherboard opposite the backplate, and a load plate configured to secure the LGA semiconductor package into the socket. The load plate can be removably coupled to the backplate and can include contact interfaces extending from the load plate and configured to contact the LGA semiconductor package when the LGA semiconductor package is loaded into the socket. The load plate can also include three or more spring elements configured to accommodate mechanical tolerances in one or more of the loading mechanism, the LGA semiconductor package, or the socket.

Land grid array (LGA) sockets with low-profile housings and stamped cylindrical pins are disclosed. Each pin includes a top contact portion, a bottom contact portion, and a serpentine spring portion that compresses along the vertical axis. In some embodiments, a bent electrically conductive strip provides a shorter electrical path to support high-speed data transmission. In other embodiments, the pin comprises a stub that contacts a pin hole plating layer to provide a shorter electrical path. The pins may be formed from beryllium copper and plated with palladium-gold. The socket housing, formed from printed circuit board laminate layers, defines cavities that receive and constrain the pins to limit movement and prevent damage. Localized ground and power structures, including plated-through holes and shielding vias, reduce crosstalk. The low-profile socket designs enhance signal and power integrity while enabling cost-effective manufacturability through progressive stamping and laminate-based assembly.

A circuit board system has a first main board 10 having a cavity 71 (e.g. trench, hole) on its top side, a second printed circuit board (PCB) 21 with a first electronic component 22 on top side of PCB, and a second electronic component 23,30 on bottom side. The PCB is arranged on top side of main board. The second electronic component extends into the cavity (e.g. trench, hole) on main board. Cavity may extend through main board. May be bridges between cavities with pins, pads, or balls 70 on bridges for connecting PCB and main board. PCB may be connected through a ball grid array or land grid array. Second electronic component may be attached to heat sink or heat spreader by thermally conductive mold compound or resin. First electronic component may comprise a system on chip (SoC). Second electronic component may comprise passive electronic components 30, e.g. DRAM memory or MLCC capacitors.

A method for dimensioning a land grid array pad can include forming an initial landing area of a land grid array pad, wherein the initial landing area is dimensioned to cause at least a majority of a landing surface of one or more socket pins to land off of the initial landing area prior to actuation of one or more sockets including the one or more socket pins. The method can also include forming a final landing area of the land grid array pad, wherein the final landing area is dimensioned to maintain electrical contact with the landing surface of the one or more socket pins after actuation of the one or more sockets including the one or more socket pins. Various other methods and systems are also disclosed.

A heat sink component can include a body including a thermally conductive material that is electrically non-conductive. The body can have a top surface, a bottom surface opposite the top surface, and a plurality of side surfaces. The heat sink component also can include a heat source terminal formed over the bottom surface of the body. The heat source terminal can be spaced apart from the plurality of side surfaces. The heat sink component further can include a heat sink terminal formed over the bottom surface of the body. The heat sink terminal can be spaced apart from the plurality of side surfaces.

Embodiments of connector-less modules and associated platforms employing the module. The module employs a Land Grid Array (LGA) comprising an array of LGA pins on the underside of the module PCB that are configured to engage respective pads patterned on a motherboard or system board PCB by applying a downward force to the module PCB. A novel clip assembly is provided to apply the downward force, while also aligning the module PCB (and its LGA) to the motherboard or system board PCB. A heat shield is provided that is configured to be disposed over the module PCB to facilitate enhanced thermal spreading and lowering thermal resistance both towards the heat shield and the PCBs. Example modules include a WWAN module and an NVMe SSD module. The module PCB may employ an M.2 form factor or other form factors.

A microelectronic system may include a microelectronic component having electrically conductive elements exposed at a first surface thereof, a socket mounted to a first surface of the microelectronic component and including a substrate embedded therein, one or more microelectronic elements each having active semiconductor devices therein and each having element contacts exposed at a front face thereof, and a plurality of socket pins mounted to and extending above the substrate, the socket pins being ground shielded coaxial socket pins. The one or more microelectronic elements may be disposed at least partially within a recess defined within the socket. The socket may have a land grid array comprising top surfaces of the plurality of the socket pins or electrically conductive pads mounted to corresponding ones of the socket pins, and the element contacts of the one or more microelectronic elements may be pressed into contact with the land grid array.

The invention discloses a microwave packaging design of a grid array interface. The microwave packaging design comprises a waveguide, a PCB (Printed Circuit Board) and a ceramic package, the ceramic package comprises a ceramic bottom plate, an enclosure frame and a cover plate; the side, facing the PCB, of the ceramic bottom plate is further provided with planting balls and planting columns, and the ceramic package is connected with the PCB through the planting balls. One end of the planting column is connected with the ceramic bottom plate, and the other end of the planting column penetrates through the PCB and extends into the waveguide; and the ceramic package is coupled with the waveguide through the planting column. The ceramic package disclosed by the invention can be simultaneously interconnected and fused with a waveguide and a PCB (Printed Circuit Board) multilayer board, so that the system integration level and the design flexibility are remarkably improved. And the ceramic package can directly realize radio frequency signal interconnection transmission with the waveguide structure through column-planting electromagnetic coupling, so that low-loss and miniaturized product performance is achieved, and the noise coefficient of a receiving front end and the power output efficiency of a transmitting tail end are optimized.

A semiconductor device has a semiconductor package including a substrate comprising a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A fanged metal mask is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The fanged metal mask is removed after forming the shielding layer.

A method and related structure for a encapsulant defined land grid array (LGA) may comprise a semiconductor chip comprising conductive studs disposed over an active layer of the semiconductor chip, and a first encapsulant disposed around at least a portion of sidewalls of the conductive studs. A surface of the first encapsulant and conductive studs may be planarized. Conductive traces may be disposed over the encapsulant and coupled with the conductive studs. A dielectric layer may be disposed adjacent the conductive traces. LGA pads may be coupled with the conductive traces. A second encapsulant may be disposed over the dielectric layer and the LGA pads. A planar surface may be formed comprising the second encapsulant around the LGA pads and attachment areas on or over the LGA pads. The plurality of attachment areas may be coplanar or recessed the planar surface.

In one embodiment, an apparatus includes a socket interconnect that implements a liquid metal (LM)-based connection mechanism and another type of connection mechanism, such as a land grid array (LGA)-, pin grid array (PGA)-, or compression mount technology (CMT)-based connection mechanism.

A memory module, a motherboard, and a latch assembly coupled to the memory module and the motherboard are described, the latch assembly including a connector coupled to the motherboard, a first lever coupled to the connector via a first pivot point, an load member extending through an opening in the first lever, a second lever coupled to the load member via a second pivot point, and a spring to bias the load member away from the opening in the first lever. The latch assembly may be used as a dual inline memory module (DIMM) retention assembly for compression mount technology (CMT) and land grid array (LGA) connector loading.

The present application relates to the field of integrated circuit packaging technology, and particularly relates to a parallel seam welding method suitable for pin grid array ceramic packaging. A special tool clamp is designed, and a special "special-shaped" electrode is designed and processed; the tool clamp is installed on a stage of a parallel seam welding device; a pair of "special-shaped" electrodes are respectively installed on horizontal electrode shafts of the parallel seam welding device, and a shell is installed in a groove of the tool clamp; welding track simulation and debugging are performed according to a welding starting point position, a welding distance and an electrode assembly position; determined process parameters are input into welding software, and a cover plate and the shell are pre-tack welded and fixed; the electrode is adjusted to realize "obstacle-avoiding" welding in an X-axis direction; the electrode is adjusted again to realize "obstacle-avoiding" welding in a Y-axis direction, and the parallel seam welding is completed. The electrode can realize perfect obstacle avoidance around a sealing surface, and problems such as local physical interference, over-melting and under-welding in the welding process are avoided.

To provide an electronic device package.SOLUTION: An electronic device package can include a laminate substrate. The electronic device package can include connection pads disposed on the laminate substrate and along the perimeter of the electronic device package. Connection pads that are along the first side of the laminate substrate can have a first orientation that is different from a second orientation of connection pads that are along the second side of the laminate substrate. The first side can be adjacent to the second side. Each of the connection pads can have a minimum size for Kelvin sensing in process technology for manufacturing the electronic device package. The electronic device package can include a die enclosed within a packaging structure.SELECTED DRAWING: Figure 1A

The utility model provides a grid array assembly, a circuit board, electronic equipment and a movable platform, the grid array assembly comprises a first circuit board and a grid array device, and the first surface of the first circuit board is provided with a plurality of first bonding pads; the grid array device comprises a second circuit board, a second surface of the second circuit board is provided with a plurality of second bonding pads, and the plurality of first bonding pads and the plurality of second bonding pads are in one-to-one correspondence and are welded and fixed; wherein the first bonding pad is provided with a solder layer, in a plane parallel to the first circuit board, the projection area of the solder layer before welding is larger than that of the second bonding pad, and the projection area of the first bonding pad is larger than that of the second bonding pad corresponding to the first bonding pad. When the second bonding pad on the grid array device is warped, in the welding process of the first bonding pad and the second bonding pad, the welding flux layer is liquefied and then is influenced by surface tension to be filled between the first bonding pad and the second bonding pad, so that the welding area of the first bonding pad and the second bonding pad is increased, and the product reliability is improved.