2201 results about "Motherboard" patented technology

The invention provides a server voltage monitoring system and method, electronic equipment and a storage medium, and relates to the technical field of computers, the system comprises a complex programmable logic device CPLD, and an initial timing module, a voltage acquisition module, an abnormal data storage module, a CPU processor and a baseboard management controller BMC module which are respectively in communication connection with the CPLD. The initial timing module activates the monitoring function of the CPLD through a startup signal; the voltage acquisition module acquires voltage data under the control of the CPLD so as to read the voltage data of the server mainboard; the CPLD obtains voltage data, compares the voltage data with a reference voltage range of the abnormal data storage module, triggers an interrupt signal after identifying abnormal fluctuation voltage, and feeds back the interrupt signal to the CPU and the BMC, so that the CPU and the BMC quickly output an alarm. The system covers full-cycle monitoring from startup to BMC startup, supports efficient acquisition, dynamic detection and low-delay response of multi-path voltage, relieves the voltage pressure of a BMC monitoring mainboard, and provides reliable guarantee for power supply safety of a server.

The invention provides a detection system and method of a display control panel, equipment, a medium and a program product, and relates to the technical field of equipment detection, and the system comprises a test host, and a mainboard to be detected and a detection device which are connected with the test host; the mainboard to be tested comprises a display screen driving module; the test host is used for respectively outputting a test image signal to the mainboard to be tested and the detection device; the to-be-tested mainboard is used for performing signal conversion on the test image signal based on the display screen driving module to obtain a display screen driving signal and outputting the display screen driving signal to the detection device; and the detection device is used for carrying out pixel comparison on image data in the test image signal and the display screen driving signal, and determining a detection result of the mainboard to be detected based on a pixel comparison result. Based on the device, the test precision, efficiency and consistency of the display control panel can be effectively improved, the uncertainty caused by manual intervention is reduced, the test cost is reduced, and the device has high universality and adaptability.

The invention provides a server mainboard and a link management method, which can be applied to the technical field of servers. The server mainboard comprises: at least one server node, which comprises a host bus interface and a programming bus interface; the connector is electrically connected with the at least one expansion board through a cable; the first controller comprises a control bus interface and is used for receiving the link bit number information sent by the at least one expansion board and carrying out misplug verification on the at least one expansion board; the link control module is used for determining a service node bus interface from the host bus interface and the programming bus interface based on the received in-place signal of the at least one expansion board, and taking the service node bus interface as a target bus interface in a first time period; and taking the control bus interface as a target bus interface in a second time period different from the first time period, so that a target link for transmitting a target serial bus signal is formed between the target bus interface and the connector.

The invention discloses an equipment control system and method for OPS computer mainboard production, and relates to the technical field of equipment control, and the method comprises the steps: collecting technological parameters, and constructing a topological vector space; key information in the line changing process is recorded and stored in the context memory network; when a new OPS mainboard production order is received, identifying a product model in the order, and performing similarity retrieval in the topological vector space and the context memory network; taking the parameters retrieved by the topological space as basic parameters, taking the adjustment strategy extracted from the context memory network as increment, and generating initial process parameter setting; small-batch trial production is carried out, and an actual production result is compared with an expected result; and utilizing a reinforcement learning algorithm to generate optimization parameters. According to the method, through collaborative retrieval of the topological vector space and the context memory network, the optimal process parameters are rapidly obtained, the line changing debugging time is shortened, and more accurate control is completed.

The embodiment of the invention discloses a GPU BOX, a server, an interconnection system and a high-speed interconnection and data interaction method. The GPU BOX high-speed interconnection method is characterized in that the GPU BOX comprises a GPU and a control mainboard, an internal PCIe switch, an internal storage device, a first DMA controller and a system controller are integrated in the control mainboard, and a second DMA controller is integrated in the GPU; the system controller receives the reading instruction and performs data read-write initialization on the first DMA controller and the second DMA controller based on the reading instruction; the first DMA controller after data read-write initialization reads cache data from the internal storage device, and transmits the cache data to the GPU via the internal PCIe switch through the established GDS connection; wherein the GDS connection between the GPU and the internal storage device is established through the system controller, the second DMA controller, the internal PCIe switch and the first DMA controller. According to the method, high-speed direct data transmission of the GPU BOX can be achieved, CPU data transfer is not needed, and the data transmission efficiency is greatly improved.

The present application relates to a test tool and test method for an interface of a motherboard to be tested of a server. The test tool for an interface of a motherboard to be tested of a server comprises a test tool, wherein the test tool comprises a tool core board, a Riser adapter card and an OCP adapter card. The Riser adapter card and the OCP adapter card each comprise a gold finger interface and a SlimSAS connector, and the Riser adapter card and the OCP adapter card are respectively used for transferring and transmitting signals of Riser interfaces and OCP interfaces on said motherboard to the tool core board. The tool core board, the Riser adapter card and the OCP adapter card are respectively connected to the corresponding interfaces on said motherboard by means of cables, so that the test of the interfaces on said motherboard can be realized.

The invention discloses a server starting control method and electronic equipment, relates to the technical field of computers, is applied to a universal boot loader, and comprises the following steps: obtaining a signature verification public key through an input interface; verifying and decrypting the signed mirror image header of the kernel mirror image by using the signature verification public key so as to recover the original mirror image header of the kernel mirror image; extracting a reference metric value of the kernel mirror image from the head of the original mirror image; calculating a to-be-verified metric value based on the kernel mirror image of which the head of the original mirror image is recovered, and comparing whether the to-be-verified metric value is consistent with the reference metric value or not; and if yes, loading the operating system. On the basis of not modifying the design of the server mainboard, active, complete and efficient trusted measurement of the BMC starting process is realized.

The invention discloses a GPU hot plug method, device and equipment and a storage medium, and relates to the technical field of computers, and the method comprises the steps: processing an initial surge current peak value based on a reverse compensation signal generated by an initial power phase difference between a mainboard and a GPU, and determining a to-be-optimized network signal based on an obtained target surge current peak value and an initial network signal; adjusting the initial signal reflection coefficient of the to-be-optimized network signal by using the programmable LC array, optimizing the to-be-optimized network signal by using the obtained target signal reflection coefficient, performing protocol compatibility processing on the mainboard and the GPU based on the obtained target network signal, and diagnosing the obtained target GPU. And after the obtained diagnosis result represents that the diagnosis is passed, performing hot plugging by using a preset plugging protocol, a GPS synchronous clock and a prediction result of the temperature, the load and the surge current peak value of the target GPU predicted by the prediction model. In this way, the security of executing the GPU hot plug operation can be improved.

The invention discloses a substrate management controller and a substrate management controller control method and device, and relates to the technical field of servers, and the substrate management controller comprises a processor module which is used for obtaining configuration information of a firmware program and an enable signal of the substrate management controller, and running the substrate management controller based on the firmware program, the configuration information is sent to the electrifying control module; and the power-on control module is used for receiving the configuration information, generating an enable signal based on the configuration information, and controlling the power-on time sequence of different devices on the server mainboard based on the enable signal. According to the technical scheme, the functions of the CPLD are integrated into the BMC, the functions of the CPLD and the functions of the BMC are achieved at the same time through the BMC, the technical problems that in the related technology, the functions of the BMC and the functions of the CPLD are achieved through corresponding independent chips, and consequently system power consumption is increased, and cost is increased are solved, and the technical effects of reducing the system power consumption and reducing the cost are achieved.

A memory module has pads on the top and bottom surfaces of a module printed circuit board (PCB). The pads match the pin layout of one or more memory devices to be mounted on the memory module. The pads on one surface of the PCB electrically interconnect to the memory device(s), and the pads on the other surface electrically interconnect to pads on a system board, such as a motherboard. With the pad layout on the memory module, the pad layout of the system board can be the same for a memory-down implementation and for a removable memory module. The pad layout provides good signal-to-noise performance and can enable a memory module for low power double data rate (LPDDR) memory, double data rate (DDR) memory, and graphics double data rate (GDDR) memory.

The invention discloses a computer mainboard abnormity identification method and system, and relates to the technical field of computer hardware diagnosis and maintenance, and the method comprises the following steps: collecting voltage, temperature and current signal parameters on a mainboard in real time; preprocessing the signal parameters to extract features; and inputting the preprocessed feature data into a pre-trained machine learning model, wherein the model is generated based on historical fault case training. According to the computer mainboard abnormity identification method and system, the voltage, temperature and current signal parameters of the mainboard are collected in real time, the pre-trained machine learning model is used for abnormal mode identification, the accuracy and the real-time performance of mainboard abnormity detection are remarkably improved, dominant faults can be identified, and the fault detection efficiency is improved. In addition, potential anomalies with high concealment, intermittency and relevance can be captured, the missing report rate and the false report rate are effectively reduced, time sequence analysis and spectrum analysis are combined, the capturing capacity of instantaneous anomalies is enhanced, and anomaly positioning is more accurate.

The utility model belongs to the technical field of server architecture design, and particularly provides a heterogeneous computing system, a server and a data center, the system comprises a switching unit and at least two types of computing units, the number of the computing units of each type is a plurality, all the computing units are standard high-speed serial computer expansion bus board cards, and the switching unit is provided with a plurality of high-speed serial computer expansion bus slots; and all the computing units are respectively connected with the high-speed serial computer expansion bus slots on the switching unit. The computing unit is designed in the form of a PCIe card, the appearance form of a general server mainboard in the past is changed, different types of computing units can be conveniently subjected to heterogeneous system construction on a Switch bottom plate, and the heterogeneous computing system capable of being freely matched and deployed can improve the utilization efficiency of computing resources.

The invention discloses a 5G wireless pressure transmitter with a displacement anti-theft monitoring function and an implementation method, and belongs to the technical field of oilfield equipment informatization, the 5G wireless pressure transmitter comprises a shell with a front cover and a rear cover, a main battery, a backup battery and a mainboard are arranged in the shell, and magnets are additionally arranged on the inner sides of the front cover and the rear cover respectively. A reed switch I, a reed switch II, a main control circuit, a power supply monitoring circuit, a 5G module and a three-axis acceleration sensor are arranged on the main board, the reed switch I and the reed switch II are respectively fixed on a front cover inner side magnet and a rear cover inner side magnet, and the reed switch I and the reed switch II are respectively connected with the main control circuit. The main control circuit is respectively connected with the 5G module and the three-axis acceleration sensor, the main battery and the backup battery are respectively connected with the power supply monitoring circuit, and the power supply monitoring circuit is connected with the main control circuit; monitoring, alarming and position tracking of the position, illegal displacement, illegal opening of a front cover and a rear cover, illegal removal of a battery and stealing and robbery of the pressure transmitter of the long-stop well pressure instrument can be achieved.

The embodiment of the invention provides a display mother board and a preparation method thereof, a preparation method of a display panel and a display device, and relates to the technical field of display, the display mother board comprises a substrate, a pixel defining layer, a light emitting unit, an alignment mark and a light absorption layer; the pixel defining layer is located on one side of the substrate, a pixel opening is defined by the pixel defining layer, and at least part of the light-emitting unit is located in the pixel opening; the alignment mark is located in the substrate and / or on the substrate; the light absorption layer is located on the side, away from the substrate, of the alignment mark and covers at least part of the alignment mark. According to the display mother set, the color difference between the alignment mark and the alignment mark on the mask can be larger, so that the alignment between the alignment mark and the alignment mark on the mask can be more accurate, and the quality of the display mother set can be improved.

Embodiments of the present application provide a memory system, a method and apparatus for adjusting memory resources, an electronic device, and a non-transitory readable storage medium. The memory system includes a first motherboard, and a processor and a high-speed interconnection channel interface that are integrated on the first motherboard; a first adapter board, and a high-speed interconnection channel interface, a chip and a memory module that are integrated on the first adapter board; and at least one connecting cable; the at least one connecting cable is used to establish a physical link between the high-speed interconnection channel interface of the first motherboard and the high-speed interconnection channel interface of the first adapter board, and used to convert the high-speed channel interconnection signal into a processor internal dedicated bus signal transmitted by a physical link based on a peripheral component interconnect express; and the chip of the first adapter board is used to acquire the converted processor internal dedicated bus signal, and convert the processor internal dedicated bus signal into a double data rate memory signal. By the connecting cable, the high-speed channel interconnection signals are converted into IPB resources to expand DRAM resources.

The invention provides a mainboard testing method and system, and relates to the technical field of mainboard testing methods.The mainboard testing method comprises the steps that firstly, an impedance compensation matrix is generated through pre-calibration sweep frequency signals, full-band dynamic calibration is conducted on probe impedance characteristics, and signal attenuation and phase deviation caused by impedance mismatch between a testing probe and a mainboard interface are eliminated; secondly, based on multi-channel frequency domain filtering and linear combination, separating frequency domain sensitive frequency bands and time domain fluctuation characteristics of test parameters, calculating parameter weights by fusing frequency domain energy and time domain variance, avoiding the limitation of single domain analysis, and enhancing the detection sensitivity of the hidden defects of the mainboard; according to the test parameter weight vector and the probe weight mapping matrix, the test parameter weight vector is converted into a test probe weight vector, finally, the parameter importance is quantified as a basis for probe excitation intensity and sampling rate adjustment, and the beneficial effect that test resources are distributed according to needs is achieved.

The invention discloses a data scheduling and control method based on mainboard memory straight-through, and relates to the technical field of computer hardware, the method comprises the following steps: pre-allocating a straight-through memory area for mounting equipment in a firmware initialization stage, establishing a mapping relation between equipment identification and a physical address of an exclusive memory segment, and through address translation and access control rules of a firmware layer, the device bypasses a system cache level and accesses the exclusive memory segment in a direct memory access mode. Constructing a firmware scheduling table based on the mapping relation to manage access requests of all devices, monitoring transmission delay in real time, and dynamically adjusting priority weight and bandwidth allocation in the scheduling table according to a monitoring result; and sequencing the requests according to the updated scheduling table to complete scheduling and control of the memory access behavior of the equipment. According to the method and the device, the delay bottleneck caused by multi-level copying and firmware scheduling lag in mainboard data forwarding is effectively solved.

Embodiments herein relate to a semiconductor device which includes one or more voltage regulator (VR) chiplets coupled to a package interposer, where the package interposer includes coaxial magnetic composite core inductors to provide power to one or more load die. In one possible configuration, the one or more VR chiplets are coupled to the bottom side of the package interposer, the bottom side of the package interposer is coupled to the top side of a motherboard, and the one or more load die are coupled to the top side of the package interposer. In another possible configuration, the one or more VR chiplets are coupled to the bottom side of the package interposer, the top side of the package interposer is coupled to the bottom side of a motherboard and the one or more load die are coupled to the top side of the motherboard.

The embodiment of the invention provides a mainboard assembly and electronic equipment, and aims to solve the problem that the efficiency of an antenna is low, in the electronic equipment, a middle frame is at least partially arranged between a battery and a first radiator, the middle frame is provided with a window, the first radiator covers at least part of the window, clearance is provided for a first antenna through the arranged window, and the efficiency of the antenna is improved. Or the partial thickness of the middle frame provides the clearance of the first antenna, so that the gain of the first antenna is improved.

A liquid cooling apparatus and system for the immersion cooling of electronic devices including in particular servers and other IT hardware nodes having an array of heat generating devices including microprocessors, RAM, motherboards etc having different operational temperatures. The present apparatus and system is adapted for at least an in-series flow of cooling liquid in direct contact with the different heat generating devices so as to provide multi-stage heat transfer phases for enhanced energy efficiency and operational control and performance of the electronic device.

An information handling system main printed circuit board having a CPU couples to a graphics printed circuit board having a GPU with an interposer that includes contacts and wirelines that communicate signals between the separate boards. For example, an interposer couples to an upper and lower side of the main and graphics printed circuit boards to align spring contacts with contact pads of the main and graphics printed circuit so that signals are transferred through the interposer, which also provides a physical structure to define a motherboard with the assembly of the main and graphics printed circuit boards into a single piece.

A liquid cooling device and a server are provided. The liquid cooling device includes at least two motherboards provided in a stack, and each motherboard being provided with at least two heat generating elements; and a plurality of liquid cooling plates attached to the plurality of heat generating elements in a one-to-one correspondence. Two liquid cooling plates corresponding to two heat generating elements on the same motherboard are connected in series form a liquid cooling loop, and a plurality of liquid cooling loops are connected in parallel.

The utility model relates to the technical field of computer remote control equipment, and provides low-power-consumption PCIe (Peripheral Component Interconnect Express) card insertion type computer remote control equipment. The device is composed of a PCIe board card and a USB expansion board card, and the PCIe board card integrates a network module, a first power supply module and an HDMI module. The first power supply module covers a mainboard power supply interface unit, a case power supply interface unit, a PCIE interface unit and a Poe power supply unit, the network module comprises an Ethernet unit and a wireless local area network unit, and the USB expansion board card is equipped with a second power supply module. All the modules cooperate with one another, and various power supply and networking modes are achieved. In addition, the equipment is further provided with a baffle used for fixing the position of the equipment in the case. The PCIe board card adopts a half-height board card design, the baffle is a standard baffle or a half-height baffle, PCIe full-height and half-height installation modes are compatible, and the adaptability and flexibility of the equipment in different case environments are further improved.

The invention relates to the technical field of electronic products, in particular to a flexible circuit board and electronic equipment. The flexible circuit board is used for connecting a USB interface and a mainboard in the electronic equipment. The flexible circuit board comprises two flexible boards which are detachably connected, namely a first flexible board and a second flexible board, the first flexible board is arranged on the rear side of the battery and connected with the USB interface, and the second flexible board is arranged on the front side of the battery and connected with the mainboard. When the USB interface needs to be disassembled, the first flexible plate can be seen by opening the cover plate on the rear side of the electronic equipment, and due to the fact that the first flexible plate and the second flexible plate are detachably connected, the first flexible plate can be conveniently disconnected from the second flexible plate, the first flexible plate is taken down, and then subsequent processing is conducted on the USB interface. Therefore, the battery does not need to be disassembled, the disassembly step of the USB interface is simplified, the complexity of disassembly can be reduced, the battery does not need to be installed again, and the assembly difficulty and the maintenance cost are reduced.

An information handling system may include a motherboard, an information handling resource bay, a first connector coupled to the motherboard and configured to electrically couple to a compatible information handling resource inserted into the information handling resource bay, and a mechanical guard coupled to the information handling resource bay such that the mechanical guard covers a portion of an opening of the information handling resource bay proximate to the first connector, wherein the mechanical guard is arranged relative to the opening such that when an attempt is made to insert an incompatible information handling resource into the information handling resource bay, the mechanical guard mechanically interferes with an interference feature of the incompatible information handling resource to prevent full insertion of a second connector of the incompatible information handling resource into the first connector.

The invention relates to a satellite-borne super-large-scale digital phased array system based on a JESD204B clock synchronization network, and the system comprises a radio frequency antenna layer which is used for receiving and transmitting electromagnetic waves in a space, and completing the mutual conversion of a radio frequency signal and a space electromagnetic wave; the sub-array baseband layer is used for realizing S-band 64-path intermediate frequency signal sampling, transmitting and digital domain multi-beam synthesis in a transceiving link, realizing data transmission with the mother board clock layer, and completing a reconstruction function of a baseband module signal processing FPGA (Field Programmable Gate Array) through a low-speed interface; the mother board clock layer serves as a function of realizing data summarization and distribution and performs task scheduling and management on the whole digital phased array system, and a JESD204B clock tree network is designed in the board and is distributed to a synchronous clock of each baseband module so as to indicate a target signal to complete synchronous sampling and emission output. By adopting the system, access, efficient tracking and accurate pointing of massive ground users can be realized.

A server including a motherboard, a first connector, an expansion card, a second connector and an auxiliary assembly. The first connector is disposed on the motherboard. The second connector is disposed on the expansion card and plugged with the first connector. The auxiliary assembly includes a handle and a mounting protrusion. The handle is movably disposed on the motherboard, and the mounting protrusion is disposed on the expansion card. When the handle pushes the mounting protrusion, the handle facilitates the second connector and the first connector to be plugged with or detach from each other, so as to facilitate the motherboard to be electrically connected to or electrically disconnected from the expansion card.

The invention relates to a server fault positioning system and method, and the system comprises a debugging card and a mainboard, and the debugging card is electrically connected with the mainboard. The debugging card is used for acquiring a power-on self-test code of the mainboard and matching the power-on self-test code with a pre-stored fault code library; determining a fault code corresponding to the power-on self-test code, and determining a fault module corresponding to the fault code in the target server; the mainboard is used for calling and starting BIOS debugging firmware stored in the debugging card, entering a debugging mode and obtaining enumeration information of a fault module; the debugging card is also used for analyzing the enumeration information and determining a state code corresponding to each unit included in the fault module; respectively matching each state code with a pre-stored state code library; and determining a fault state code which cannot be matched with the correct state code in the state code library, and determining a fault unit corresponding to the fault state code. Through the method and the device, the problem of relatively low fault positioning efficiency of the server in related technologies is solved.

An interposer module incorporates at least one flip-chip or other densely pitched IC (DP-chip) into a motherboard assembly without placing undue requirements on the motherboard. The interposer module includes a rigid, densely pitched, multilayer circuit card having an interconnection array for attachment of the DP-chip interconnection points, and a mezzanine connector for removable mating to a compatible motherboard interconnector. Clusters of power connections, clusters of differential pairs of high frequency connections, and clusters of low frequency control connections and / or differential pairs of clock connections are each surrounded and isolated by ground connections. A compartment cover having a lid and isolating dividers can be placed over the DP-chip to isolate high frequency areas of the module from each other and from other RF sensitive areas. Thermally conductive material can extend from the cover lid to the DP-chip, and a cooling fan can circulate air past cooling fingers extending from the lid.