13 results about "PCI Express" patented technology

A dockable expansion device for a minicomputer is provided. The minicomputer includes a thermal module, a motherboard, and a first connector. The thermal module is positioned on one side of the motherboard, and the first connector is mounted on another side of the motherboard opposite the thermal module. The dockable expansion device includes a casing and a Mobile PCI Express Module (MXM) expansion board. The MXM expansion board includes a slot for connecting an MXM graphics module, and a second connector. The second connector is compatible with the first connector and installed facing an opening of the casing. The first connector is exposed from a bottom surface of the minicomputer, and the second connector is configured to align with the first connector when the minicomputer is docked with the dockable expansion device.

According to one embodiment, a method, computer system, and computer program product for adjusting output swing voltage of a Peripheral Component Interconnect Express (PCIe) system is provided. The present invention may include training a neural network, recording, in real time, lane input data of PCIe lanes comprising a PCIe link, generating eye diagrams representing the PCIe lanes based on the lane input data, predicting, by the trained neural network, predicted eye heights for the PCIe lanes, and adjusting a current output swing voltage of one or more PCIe lanes based on the predicted eye heights.

The application provides a large model training acceleration method and system based on CUDA shared memory and a PCIe expansion card, hardware configuration information is acquired to identify the PCIe expansion card and build an expansion storage space, and a unified management heterogeneous memory space is formed in combination with GPU shared memory; in the training process, according to a preset initialization strategy, model data blocks are loaded to different levels of the heterogeneous memory, data access frequency is monitored in real time, data migration instructions are dynamically generated based on multiple frequency thresholds, and intelligent scheduling of the data blocks among the levels of storage is realized; a transparent address remapping mechanism is used to enable CUDA kernel functions to seamlessly access the heterogeneous memory space; periodic data snapshots and persistent storage are simultaneously supported, and quick recovery after interruption of training is ensured; the application breaks through the GPU display memory capacity limit, improves the large model training efficiency, reduces the dependence on multi-card hardware and cost, and guarantees data security and training reliability.

The application discloses a switch and a communication system for realizing UALink and PCIe protocol conversion. A PCIe controller of the switch is connected with each UALink port of the switch to receive a UALink data packet of an external processor. A converter of the switch analyzes the data packet to obtain a target port ID and a sector index. The switch determines a PCIe base address and a sector size associated with the switch according to the corresponding UALink port ID in a protocol conversion table of the switch, and determines a corresponding PCIe target address in combination with the extracted sector index, to generate head data of a PCIe transaction layer data packet, and store the head data into a head information register of the switch. If the target port ID extracted by the converter for multiple times represents a same PCIe port, the head data in the register is repeatedly used to encapsulate a PCIe data packet, and the PCIe data packet is sent out through the PCIe port.

A first set of parameter values are programed to a first set of sequencer registers. A second set of parameter values are programmed to a second set of sequencer registers. In response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.

According to one embodiment, a method, computer system, and computer program product for adjusting output swing voltage of a Peripheral Component Interconnect Express (PCIe) system is provided. The present invention may include training a neural network, recording, in real time, lane input data of PCIe lanes comprising a PCIe link, generating eye diagrams representing the PCIe lanes based on the lane input data, predicting, by the trained neural network, predicted eye heights for the PCIe lanes, and adjusting a current output swing voltage of one or more PCIe lanes based on the predicted eye heights.

A first set of parameter values are programed to a first set of sequencer registers. A second set of parameter values are programmed to a second set of sequencer registers. In response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.

PCI Express (PCIE) is an IO interconnect standard that is developed and implemented as a tree network within Computers and servers for connecting to peripheral devices. Currently PCIE has achieved stability such that PCIE can be used as a basis for other applications. A PCIE based scheme inter-connecting multiple PCIE enabled processing systems as a cluster with at least one PCIE root complex controlling at least a PCIE bus, enabling the scalability of PCIE architecture to be applied for data transport between the connected system. The interconnection uses an outbound port enabled for system interconnection on the PCIE bus of each PCIE enabled computer connecting to one inbound port on an independently programmable network switch having a plurality of inbound ports. The interconnection is using PCIE protocol for data transfer within the cluster to interconnect processors, memory controllers, storage and other network components in Data centers.

A dynamic method and system for configuring PCI Express (PCIe) bifurcation is provided. A baseboard management controller (BMC) receives system condition data representing current hardware configuration and operational metrics, including device presence, negotiated link widths, error counts, and thermal events. A trained machine learning model, such as a decision tree, predicts boot success outcomes for multiple candidate bifurcation configurations. The BMC selects a preferred configuration based on the predictions and writes it to a reserved memory buffer (RMB). During subsequent initialization, a basic input / output system (BIOS) retrieves the preferred configuration from the RMB and applies it to initialize PCIe links. The model is periodically retrained with new boot outcomes to refine predictions, enabling adaptive, self-learning bifurcation without repeated BIOS recompilation or reflashing.

A modular compute platform for artificial-intelligence inference is disclosed. Each compute module delivers exaFLOPS-class throughput within a six-hundred-watt envelope and can be installed on diverse carrier boards such as PCI Express, automotive, robotic, or rackmount systems. Modules include vertically integrated logic and memory for high-bandwidth communication and local storage of neural-network parameters. Uniform mechanical and thermal interfaces allow identical modules to serve multiple markets, enabling wide deployment of exa-scale inference capability.

A PCI Express accelerator card capable of exa-class artificial-intelligence inference within a six-hundred-watt power envelope is disclosed. The card receives twelve-volt DC power through a 12VHPWR connector and employs a multi-phase voltage-regulation network that distributes regulated power to stacked semiconductor dies on a silicon substrate. Distributed temperature sensors and predictive control firmware coordinate electrical and thermal management to maintain safe junction temperatures using standard air or liquid cooling, enabling desktop-class exa-FLOPS performance without immersion systems.

The invention discloses a switch for realizing UALink and PCIe protocol conversion and a communication system. A PCIe controller of the switch is connected with each UALink port of the switch so as to receive a UALink data packet of an external processor; the converter of the switch analyzes the data packet to obtain a target port ID and a sector index; the switch determines a PCIe base address and a sector size associated with the switch in a protocol conversion table of the switch according to the corresponding UALink port ID, determines a corresponding PCIe target address in combination with the extracted sector index, further generates header data of a PCIe transaction layer data packet, and stores the header data in a header information register of the switch; and if the target port IDs extracted by the converter for multiple times are represented as the same PCIe port, the header data in the register is repeatedly utilized to package to obtain a PCIe data packet, and the PCIe data packet is sent outwards through the PCIe port.