25 results about "PCI Express" patented technology

A dockable expansion device for a minicomputer is provided. The minicomputer includes a thermal module, a motherboard, and a first connector. The thermal module is positioned on one side of the motherboard, and the first connector is mounted on another side of the motherboard opposite the thermal module. The dockable expansion device includes a casing and a Mobile PCI Express Module (MXM) expansion board. The MXM expansion board includes a slot for connecting an MXM graphics module, and a second connector. The second connector is compatible with the first connector and installed facing an opening of the casing. The first connector is exposed from a bottom surface of the minicomputer, and the second connector is configured to align with the first connector when the minicomputer is docked with the dockable expansion device.

The present invention relates to a circuit board structure applied to a mobile PCI Express module, which complies with the PCIe 4.0 specification according to the stack-up design, the size and impedance control of the conductors, and the degree of signal attenuation. The circuit board structure includes a top signal layer, a bottom signal layer, a power layer, a plurality of first insulating layers, and a second insulating layer. The bottom signal layer and the top signal layer include a core board and conductive copper wires. The power layer is disposed between the top signal layer and the bottom signal layer. The first insulating layer is disposed between the top signal layer and the power layer and between the bottom signal layer and the power layer. The second insulating layer is disposed between the power layer and the first insulating layer. Among them, the dielectric loss values of the first insulating layer and the second insulating layer are between 0.004 and 0.014, and the length of the conductive copper wire is between 500 mil and 2500 mil, so that the signal loss of the top signal layer and the bottom signal layer is less than 8 dB.

According to one embodiment, a method, computer system, and computer program product for adjusting output swing voltage of a Peripheral Component Interconnect Express (PCIe) system is provided. The present invention may include training a neural network, recording, in real time, lane input data of PCIe lanes comprising a PCIe link, generating eye diagrams representing the PCIe lanes based on the lane input data, predicting, by the trained neural network, predicted eye heights for the PCIe lanes, and adjusting a current output swing voltage of one or more PCIe lanes based on the predicted eye heights.

The application provides a large model training acceleration method and system based on CUDA shared memory and a PCIe expansion card, hardware configuration information is acquired to identify the PCIe expansion card and build an expansion storage space, and a unified management heterogeneous memory space is formed in combination with GPU shared memory; in the training process, according to a preset initialization strategy, model data blocks are loaded to different levels of the heterogeneous memory, data access frequency is monitored in real time, data migration instructions are dynamically generated based on multiple frequency thresholds, and intelligent scheduling of the data blocks among the levels of storage is realized; a transparent address remapping mechanism is used to enable CUDA kernel functions to seamlessly access the heterogeneous memory space; periodic data snapshots and persistent storage are simultaneously supported, and quick recovery after interruption of training is ensured; the application breaks through the GPU display memory capacity limit, improves the large model training efficiency, reduces the dependence on multi-card hardware and cost, and guarantees data security and training reliability.

A circuit board structure for mobile PCI express module is applied to conform to PCI Express 4.0 specification. The circuit board structure includes a top signal layer and a bottom signal layer with a core and a conductive copper wire, a power supply layer disposed between the top signal layer and the bottom signal layer, a plurality of first insulating layers disposed between the top signal layer and the power supply layer and between the bottom signal layer and the power supply layer, and a plurality of second insulating layers disposed between the power supply layer and the first insulating layers. The dielectric loss values of the first insulating layer and the second insulating layer are between 0.004 and 0.014, and the length of the conductive cooper wire is between 500 and 2500 mil, so that the signal loss of the mobile PCI express module is less than 8 dB.

The application discloses a switch and a communication system for realizing UALink and PCIe protocol conversion. A PCIe controller of the switch is connected with each UALink port of the switch to receive a UALink data packet of an external processor. A converter of the switch analyzes the data packet to obtain a target port ID and a sector index. The switch determines a PCIe base address and a sector size associated with the switch according to the corresponding UALink port ID in a protocol conversion table of the switch, and determines a corresponding PCIe target address in combination with the extracted sector index, to generate head data of a PCIe transaction layer data packet, and store the head data into a head information register of the switch. If the target port ID extracted by the converter for multiple times represents a same PCIe port, the head data in the register is repeatedly used to encapsulate a PCIe data packet, and the PCIe data packet is sent out through the PCIe port.

A first set of parameter values are programed to a first set of sequencer registers. A second set of parameter values are programmed to a second set of sequencer registers. In response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.

According to one embodiment, a method, computer system, and computer program product for adjusting output swing voltage of a Peripheral Component Interconnect Express (PCIe) system is provided. The present invention may include training a neural network, recording, in real time, lane input data of PCIe lanes comprising a PCIe link, generating eye diagrams representing the PCIe lanes based on the lane input data, predicting, by the trained neural network, predicted eye heights for the PCIe lanes, and adjusting a current output swing voltage of one or more PCIe lanes based on the predicted eye heights.

A first set of parameter values are programed to a first set of sequencer registers. A second set of parameter values are programmed to a second set of sequencer registers. In response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.

A method for exchanging interface information between different communication partners for the communication of the communication partners via PCI Express. The method includes: a) ascertaining an interface definition, which describes memory areas and an internal memory layout of a first communication partner which a second communication partner is to access to read and / or write data; b) creating a serialized form of the interface definition ascertained in step a); c) providing the serialized form of the interface definition created in step b) to the second communication partner; and d) automatically configuring the second communication partner with the transmitted interface definition for the communication between the communication partners.

Examples described herein relate to a device including circuitry to permit or deny the device to write-to or read-from kernel space memory of a virtualized execution environment by use of multiple process identifiers. In some examples, the device is communicatively coupled with the virtualized execution environment in a manner consistent with one or more of: Single Root IO Virtualization (SR-IOV), Scalable I / O Virtualization (SIOV), or PCI express (PCIe). In some examples, to control write or read operations to kernel space memory of a virtualized execution environment by the device by use of multiple process identifiers, the circuitry is to perform an address translation based on a first process identifier and second process identifier associated with the virtualized execution environment.

PCI Express (PCIE) is an IO interconnect standard that is developed and implemented as a tree network within Computers and servers for connecting to peripheral devices. Currently PCIE has achieved stability such that PCIE can be used as a basis for other applications. A PCIE based scheme inter-connecting multiple PCIE enabled processing systems as a cluster with at least one PCIE root complex controlling at least a PCIE bus, enabling the scalability of PCIE architecture to be applied for data transport between the connected system. The interconnection uses an outbound port enabled for system interconnection on the PCIE bus of each PCIE enabled computer connecting to one inbound port on an independently programmable network switch having a plurality of inbound ports. The interconnection is using PCIE protocol for data transfer within the cluster to interconnect processors, memory controllers, storage and other network components in Data centers.

A dynamic method and system for configuring PCI Express (PCIe) bifurcation is provided. A baseboard management controller (BMC) receives system condition data representing current hardware configuration and operational metrics, including device presence, negotiated link widths, error counts, and thermal events. A trained machine learning model, such as a decision tree, predicts boot success outcomes for multiple candidate bifurcation configurations. The BMC selects a preferred configuration based on the predictions and writes it to a reserved memory buffer (RMB). During subsequent initialization, a basic input / output system (BIOS) retrieves the preferred configuration from the RMB and applies it to initialize PCIe links. The model is periodically retrained with new boot outcomes to refine predictions, enabling adaptive, self-learning bifurcation without repeated BIOS recompilation or reflashing.

The invention discloses a software test platform based on high-speed multi-interface ground inspection. The software test platform comprises a test case and upper computer test software, the test case is provided with a plurality of interface board cards of different types, and the interface board cards communicate with the test case through a PCI Express bus; the upper computer test software is set to be capable of being connected with, reading and writing data of different interface board cards at the same time, and the upper computer test software comprises a middleware layer written by C + + and an upper computer application program written by a C # language. The invention provides a software test platform and a test method based on high-speed multi-interface ground detection, which support a plurality of different types of interfaces, ensure the data transmission consistency in a multi-interface environment, avoid data loss or error, enhance the data processing capability and response speed, and ensure the real-time requirement in a high-speed data stream scene.

The invention discloses a SlimLine high-speed signal switching control circuit, and relates to the field of quality management, and the circuit comprises a mainboard which comprises a CPU0, a CPU1 and a SlimLine signal transmitting end; the SlimLine alternative switching card is used for automatically switching the NVME HDD signal and the SATA HDD signal according to the requirement, and the SATA HDD signal is used for switching the NVME HDD signal and the SATA HDD signal according to the requirement; according to the SlimLine high-speed signal switching control circuit, an NVME or an SATA HDD is automatically switched according to requirements by manufacturing an ''SlimLine either-or transfer card''; a high-speed passive switch with high performance is provided, is specially designed for PCI Express data switching application, supports data transmission as high as 5.0 Gbps, and is passive and low in power consumption; and the electronic relay is used for switching different hardware channels to replace mechanism switching.

A virtualised PHY (V-PHY) Interface for the PCI Express protocol is provided to enable a first PIPE-compliant component located on a first circuit die to communicate with a second PIPE-compliant component located on a second circuit die, where the first and second circuit dies are communicatively coupled to one another via a die-to-die (D2D) interface. The V-PHY interface can enable this communication transparently so that neither the first component nor second component needs to have any knowledge of the D2D interface or indeed that they are communicating across dies.

PCI-Express (PCIE) is a hierarchical Bus or-I / O interconnect standard-used for interconnection between a root-complex of a PCIE enabled computing system and peripheral devices over the bus that may include hierarchically connected and controlled PCIE switches.The current application describes a PCIE based interconnect scheme for a plurality of PCIE enabled computing systems connected in a cluster using a network switch, having a plurality of inbound PCIE ports, The network switch is independently configured and controlled as a hub of a star interconnection topology for switching and data-transfer between its inbound PCIE ports. Connecting an outbound PCIE port, enabled for interconnection, on each of the plurality of the PCIE enabled computing systems of the cluster to one of the plurality of inbound PCIE ports on the network switch the star interconnection for communication and data-transfer between the PCIE enabled systems of the cluster through the network switch is enabled.

The present disclosure relates to systems, methods, and computer-readable media for facilitating efficient retrieval of diagnostic information from a computing endpoint that experiences a failure condition. For example, systems described herein may detect or otherwise identify a failure condition associating with the computing endpoint operating in an erroneous or unpredictable matter. Systems described herein may involve carving out a portion of memory on the computing endpoint that is accessible to a host system (e.g., a CPU). Systems described herein may further provide a discoverable resource that enables a host system to identify and collect the diagnostic data in response to identifying a failure condition in an efficient manner and without requiring that the computing endpoint be capable of responding to data requests.

A modular compute platform for artificial-intelligence inference is disclosed. Each compute module delivers exaFLOPS-class throughput within a six-hundred-watt envelope and can be installed on diverse carrier boards such as PCI Express, automotive, robotic, or rackmount systems. Modules include vertically integrated logic and memory for high-bandwidth communication and local storage of neural-network parameters. Uniform mechanical and thermal interfaces allow identical modules to serve multiple markets, enabling wide deployment of exa-scale inference capability.

Method for exchanging interface information between different communication partners for communication between the communication partners (3,4) via PCI Express, comprising the following steps: a) determining an interface definition (7) which describes memory areas (8) and an internal memory layout of a first communication partner (4) which a second communication partner (3) is to access for reading and / or writing data; b) creating a serialized form of the interface definition (7) determined in step a); c) providing the serialized form of the interface definition (7) created in step b) to the second communication partner (3); and d) Automatic configuration of the second communication partner (3) with the transmitted interface definition (7) for the communication of the communication partners (3,4).

A PCI Express accelerator card capable of exa-class artificial-intelligence inference within a six-hundred-watt power envelope is disclosed. The card receives twelve-volt DC power through a 12VHPWR connector and employs a multi-phase voltage-regulation network that distributes regulated power to stacked semiconductor dies on a silicon substrate. Distributed temperature sensors and predictive control firmware coordinate electrical and thermal management to maintain safe junction temperatures using standard air or liquid cooling, enabling desktop-class exa-FLOPS performance without immersion systems.

An adapter cable can include a receptacle connector including contact pins as defined for a peripheral component interconnect express (PCIe) connector; edge connectors having edge pins as defined for a PCIe add-in card (AIC); and connections connecting the receptacle connector to the edge connectors, each connection connecting one of the contact pins to one of the edge pins.

The present disclosure relates to systems, methods, and computer-readable media for facilitating efficient retrieval of diagnostic information from a computing endpoint that experiences a failure condition. For example, systems described herein may detect or otherwise identify a failure condition associating with the computing endpoint operating in an erroneous or unpredictable matter. Systems described herein may involve carving out a portion of memory on the computing endpoint that is accessible to a host system (e.g., a CPU). Systems described herein may further provide a discoverable resource that enables a host system to identify and collect the diagnostic data in response to identifying a failure condition in an efficient manner and without requiring that the computing endpoint be capable of responding to data requests.

The invention discloses a switch for realizing UALink and PCIe protocol conversion and a communication system. A PCIe controller of the switch is connected with each UALink port of the switch so as to receive a UALink data packet of an external processor; the converter of the switch analyzes the data packet to obtain a target port ID and a sector index; the switch determines a PCIe base address and a sector size associated with the switch in a protocol conversion table of the switch according to the corresponding UALink port ID, determines a corresponding PCIe target address in combination with the extracted sector index, further generates header data of a PCIe transaction layer data packet, and stores the header data in a header information register of the switch; and if the target port IDs extracted by the converter for multiple times are represented as the same PCIe port, the header data in the register is repeatedly utilized to package to obtain a PCIe data packet, and the PCIe data packet is sent outwards through the PCIe port.