765 results about "Control bus" patented technology

An ExpressCard contains flash memory. The ExpressCard has an ExpressCard connector that plugs into a host, such as a personal computer, digital camera, or personal digital assistant (PDA). A controller chip on the ExpressCard uses a pair of differential Universal-Serial-Bus (USB) data lines in the connector to communicate with the USB host, or can use PCI Express, Firewire, or other protocols. One or more flash-memory chips on the ExpressCard are controlled by a flash-memory controller in the controller chip. Two or more channels of a flash bus have a shared control bus but separate ready lines. The separate ready lines allow flash-memory chips in the two channels to finish operations at different times.

Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. First the single or dual in-line memory module (SIMM or DIMM) includes in-line bus switches. The bus switches are between the SIMM or DIMM module tabs (system) and random access memory devices (RAM) and are either in a high impedance (off) or active state depending on the READ/WRITE state of the RAM. When in the high impedance state, the effective loading of the module is that of the bit switch device. The logic for determining the READ/WRITE state may be embedded in an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches, be provided by a memory controller or, generated by the RAM itself. The bus switches are active when the RAM is performing a read or a write and inactive otherwise. The RAM is Fast Page Mode (FPM) and Extended Data Output (EDO) or Synchronous DRAM (SDRAM).

Various embodiments of the present invention methods for discovery, configuration, and coordinating data communications between master and slave devices in a communication system. Exemplary embodiments are described with reference to a two-wire point-to-point bus system, although the method can be used in other communication systems. Provisions are included for controlling the sequential powering of the bus and slave devices.

The invention discloses a hybrid cloud computing system based on a cloud bus and a realization method of the hybrid cloud computing system. The system is based on a local private cloud, one or more public clouds are integrated, the internal constitution of the local private cloud is consistent with that of the public cloud, both the internal constitution of the local private cloud and the internal constitution of the public cloud comprise an infrastructure, a virtualization layer, a cloud platform layer, a cloud bus layer, a cloud application layer, a management center and a storage center, wherein the hardware resources on a bottom layer are grouped into a virtual cluster through the infrastructure and the virtualization layer so as to provide different virtual resources to the superior layer; the cloud platform is used for operating a web application program or a service and utilizing an open interface to carry out the secondary development and application integration; and the cloud bus layer is used for managing and monitoring various services on the cloud platform layer and is a hub for connecting the cloud application layer and the cloud platform layer, and the cloud bus layer is established on the basis of SOA (service oriented architecture) concept and comprises a control bus, a plurality of node buses and an adapter. Due to the adoption of the hybrid cloud computing system, the migration of the existing IT (internet) environment of an enterprise to a cloud computing environment can be accelerated, the investment can be reduced, and the resource can be adequately utilized.

A Digital Addressable Lighting Interface (DALI) master and DALI control bus power supply in combination with at least one DALI sub-master are connected to a single DALI control bus. The single DALI control bus may have a plurality of DALI slave devices, e.g., luminaries connected thereto and disbursed throughout a plurality of offices and/or rooms. The DALI master and the at least one DALI sub-master allow local control of the lighting in each office or room while maintaining the simplicity and cost effectiveness of a single DALI control bus system. Collision of commands sent simultaneously by two or more DALI masters may be detected and the corrupted commands retransmitted.

There is disclosed a system and method for providing an improved common control bus for use in the on-line insertion of line replaceable units (such as circuit board cards) into a backplane of a processor shelf, a modem shelf, or a similar type of equipment. The present invention increases the number of device locations that a common control bus can access. The present invention comprises a complex programmable logic device on a circuit board card that is coupled to a common control bus. The complex programmable logic device is capable of selectively coupling to the common control bus each one of a plurality of device locations on the circuit board card. The complex programmable logic device controls data access to and from each device that is coupled to the common control bus.

A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.

A machine, system and method for user-guided teaching and modifications of voice commands and actions to be executed by a conversational learning system. The machine includes a system bus for communicating data and control signals received from the conversational learning system to a computer system, a vehicle data and control bus for connecting devices and sensors in the machine, a bridge module for connecting the vehicle data and control bus to the system bus, machine subsystems coupled to the vehicle data and control bus having a respective user interface for receiving a voice command or input signal from a user, a memory coupled to the system bus for storing action command sequences learned for a new voice command and a processing unit coupled to the system bus for automatically executing the action command sequences learned when the new voice command is spoken.

The invention provides a pure electric passenger vehicle communication system based on three ways of CAN buses, comprising a plurality of controllers and three ways of CAN buses, wherein, the CAN buses comprise three ways of CAN buses which are coupled with the plurality of controllers and consist of a CAN1 bus, a CAN2 bus, and a CAN3 bus; the CAN1 bus is a high-speed CAN bus and used for the control of a power system; the CAN2 bus is a high-speed CAN bus and used for the transmission of power battery monometer data; and the CAN3 bus is a low-speed CAN bus, provided with a plurality of vehicle body control nodes, and used for achieving the information collection and control of each part of the vehicle body. The system causes the loading rate of the power system control bus to be greatly reduced, ensures the real-time performance of the control, and improves the driving safety of the electric vehicle.

A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The satellite devices are also connected to industry standard buses/devices. The central hub also communicates with a processor and system memory over additional buses. Each link bus includes a status line that allows each device connected to the same link bus to request control of the bus. The link bus protocol establishes a window in which the status signal may convey arbitration request information in a time-multiplexed manner. The protocol further includes a method of determining whether control of the bus can be transferred to a different device. Each device takes part in the decision process and thus, the arbitration method of the invention is decentralized.

A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The configurable width buffer device includes an interface and a configurable serialization circuit capable of varying a data path width or a number of contacts used at the interface of the configurable width buffer device in accessing the at least one memory device. In an alternate embodiment of the present invention, a multiplexer/demultiplexer circuit is provided. A state storage provides a data width for the configurable width buffer and a SPD provides the configurable width buffer and/or module capabilities to the memory system.

A control module (100) includes a first signal processing unit (102) that is coupled to a second signal processing unit (114) by a control bus (130), an address bus (131) and a data bus (132). The control module conveys seed value addresses (108) and expected result addresses (110) over the address bus, seed values (118) and verification set output values (107) over the data bus, and compares each verification set output value to an expected result (120), thereby allowing the control module to determine whether the first signal processing unit, the control bus, the address bus, and the data bus are collectively functioning correctly. By properly selecting the seed value addresses, expected result addresses, seed values, and expected results (and correspondingly, verification set output values), proper operation of each line of the address bus and control bus may be individually verified.

A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.

A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared address and control bus interconnecting the virtual channel memory controller and the first and second synchronous memory devices. The first and second synchronous memory devices are addressed with the shared address bus, and the first and second memory locations are accessed via the first and second data buses, respectively.

A system for providing on-die termination (ODT) of a control signal bus. The system includes a memory device that includes a plurality of data bus connectors, one or both of a load signal connector and a reset signal connector, a control bus connector, an ODT, and a mechanism. The ODT is in communication with the control bus connector, and the ODT provides a level of termination resistance to a control bus connected to the control bus connector. The mechanism latches data received via the data bus connectors in response to a signal received via one or both of the load signal connector and the reset signal connector. The data is utilized to set the level of termination resistance provided by the ODT.

An in-vivo sensing device having multiple imagers controlled by a single processor and a method for communicating between the processor and the imagers. The processor and imagers are connected via common data and control busses, instead of by direct separate conducting lines thereby reducing the number of pins on the processor and the corresponding number of conducting lines.

A dynamically coordinatable electrical distribution system includes a plurality of intelligently-controlled protection devices (PDs), a communication and control bus (comm/control) bus, and a central computer. The plurality of intelligently-controlled PDs is configured to protect a plurality of associated electrical loads from faults, developing faults, and other undesired electrical anomalies. Each of the PDs further has electrically adjustable time-current characteristics. The intelligently-controlled PDs are communicatively coupled to the comm/control bus and configured to report current data representative of real-time currents flowing through their respective loads to the central computer, via the comm/control bus. The central computer is configured to communicate with the plurality of PDs over the comm/control bus and dynamically coordinate the time-current characteristics of the plurality of PDs based on the current data it receives from the PDs.

A micromechanical panel display driver is shown in which only one driver and control bus are needed for each color. Furthermore, the elements are made with uniform film thicknesses, thereby minimizing the number of steps needed to fabricate the display. Here 6 bits are provided with temporal and aperture weighting. The use of temporal weighting generally requires the activation of most pixels twice/frame, which consumes considerable power. It should also be possible to eliminate temporal weighting by redistributing the contact area into a larger number of aperture weights and by adding a row electrode. Here pixels are activated only in response to a charge in the image. This generally reduces the drive power, since many pixels in a typical image do not change from frame to frame.

The invention discloses a TCP online quick calibration method and device applied to an industrial robot. The device comprises a control cabinet, a TCP calibration device, the industrial robot, a terminal tool and control buses; the control cabinet is separately connected with the TCP calibration device and the industrial robot through the control buses; the terminal tool is mounted on the industrial robot; the TCP calibration device includes a TCP detecting device, a calibration controller and a mounting base; the TCP detecting device is fixedly mounted on one side of the industrial robot through the mounting base; and a measuring plane is parallel to a XOY plane of an industrial robot base coordinate system. According to on-off signals of a correlation photoelectric sensor, the pose data of a flange is recorded, and the pose deviations of the terminal tool in X/Y axis and Z axis directions are calculated and compensated; and through multiple times of repeated operations, the TCP calibration errors are reduced, the operation precision of the industrial robot is effectively improved, the stop maintenance time of the industrial robot is reduced, and the automation degree of an industrial production line is improved.

A circuit and method utilizing a power control data bus for implementing power control. Various aspects of the present invention provide an electrical circuit that comprises a power supply circuit that outputs electrical power. The electrical circuit may also comprise an integrated circuit that receives electrical power from the power supply circuit. The electrical circuit may also comprise a power control data bus, which communicatively couples a power control data bus interface of the power supply circuit and a power control data bus interface of the integrated circuit. The power control data bus may, for example, carry power control data between the integrated circuit and the power supply circuit. Various aspects of the present invention also provide a method that comprises communicating power control data over a power control data bus and utilizing the power control data to control characteristics of electrical power provided to an integrated circuit or module.

The invention discloses a convolutional-neural-network accelerating system based on a field-programmable gate array. The convolutional-neural-network accelerating system comprises a general processor,the field-programmable gate array, a storage module, a data bus and a control bus, wherein the general processor is a soft core of a reduced instruction set, and is responsible for starting an accelerator, being in communication with a host terminal, conducting time measurement and the like; a DDR3 DRAM serves as an external storage of the accelerator system; an AXI4-Lite bus is used for demand transmission, and an AXI4 bus is used for data transmission; the field-programmable gate array comprises multiple processing engines (PE), and each processing engine adopts a most-suitable fragment unfolding strategy to correspond to calculation of one layer in the convolutional neural network; all the processing engines are mapped onto a same FPGA chip, and therefore different layers can simultaneously work in a production line mode. Compared with an existing convolutional-neural-network accelerating system, the convolutional-neural-network accelerating system based on the field-programmable gate array can obtain higher energy efficiency benefit.

The invention discloses an uninterruptible power supply device based on microgrid and a dispatching control method thereof. The device comprises an energy storage component, a distributed power component, at least one inverter module, an AC/DC loading module which contains an AC bus, a DC bus, a dispatching control bus, an AC load control bus, a DC load control bus and a loading unit connected with the DC bus and the AC bus, and a dispatching control module, wherein the energy storage component is connected with the DC bus and the dispatching control bus; the distributed power component is connected with the DC bus and the dispatching control bus and used to convert energy sources to electric energy, convert the electric energy to a DC with controllable voltage, current and and power and output the DC to the DC bus; the inverter module is connected with the DC bus, the AC bus and the dispatching control bus; and the dispatching control module is connected with the dispatching control bus. By adopting the device of the invention, the applicability of the distributed power can be increased and the reliability of supplying power for users can be increased.

The embodiments of the invention disclose an operation training system and method of special vehicles. The system comprises a simulation system, a controller, an immersed type display apparatus and a driving operation console of the special vehicles, wherein the driving operation console comprises operation components consistent with operation components in actual driving cabins of the special vehicles in an airport; the controller is connected with the driving operation console through a control bus and is in communicating connection with the simulation system for receiving operation control instructions sent by users through operating the driving operation console and converting the operation control instructions into digital operation control signals for transmission to the simulation system; the simulation system stores setup data of virtual three-dimensional scenes for realizing synchronization and interaction between operation of the driving operation console and changing of the states of the virtual three-dimensional scenes; and the immersed type display apparatus is used for displaying the virtual three-dimensional scenes of current special vehicles. According to the embodiments of the invention, the problems caused by fewer actual operation opportunities during training of special vehicle drivers of a civil aviation airport in the prior art can be solved.

The invention discloses a fiber monitoring system. The fiber monitoring system comprises multiple monitoring hosts and a first monitoring server connected with the monitoring hosts, wherein the monitoring hosts comprise monitoring modules, the monitoring modules comprise optical transceivers used for receiving optical signals after transmission through a fiber to be detected, optical signal ports and micro processors, the optical transceivers are connected with the optical signal ports, the optical signal ports are connected with the micro processors through a data/control bus, the micro processors are used for processing the optical signals which are transmitted through the optical signal ports to the micro processors and are used for sending processing results to the first monitoring server, the first monitoring server comprises an alarm module, the alarm module is used for carrying out alarm after receiving the processing results of the micro processors. The fiber monitoring system can reduce and prevent optical cable faults and can position positions of the optical cable faults.

A method and system are described which provide flexible coupling between a coprocessor and a control processor. The system includes a coprocessor and a system control bus connecting the coprocessor with the control processor. The coprocessor has two modes of access. In the first mode of access, the coprocessor retrieves an instruction stored in instruction memory and, in the second mode of access, the coprocessor retrieves an instruction from the control processor. The system control bus provides a path for loading an instruction to the coprocessor's shadow instruction register. The coprocessor, upon retrieving an entry in its instruction memory associated with the shadow instruction resigter, determines whether to load the instruction as an address in its program counter or to load the contents of the shadow instruction register into the instruction decode register.

A method for conveying control information in an ultrasound system is provided. The method provides unique identifiers for the processing components in a beamformer of an ultrasound system. The method formats control information into at least one packet based on a packetized protocol, the control information relating to beamforming operations carried out by the processing components. The method conveys the control information to the processing components.

The invention discloses a single event upset-resistant satellite-borne data processing system. The system comprises a CPU, a FLASH FPGA, an SDRAM, a first NOR FLASH, an SRAM FPGA and a NAND FLASH, wherein data, an address and a control bus of the CPU are connected with the FLASH FPGA and the SDRAM; the FLASH FPGA is connected with the first NOR FLASH, the SRAM FPGA and the NAND FLASH; an EMI module of the CPU has an ECC encoding/decoding function; the FLASH FPGA is used for CPU software guidance, SRAM FPGA configuration and refreshing and NAND FLASH control; all logic of the FLASH FPGA is subjected to triple modular redundancy design; the SDRAM is used for CPU software running, and stored data is subjected to ECC encoding so as to realize "single-error-correcting and double-error-detecting" fault tolerance; and the first NOR FLASH is used for storing a startup program of the CPU, an application of the CPU and a configuration program of the SRAM FPGA. The system has the advantages of high reliability, in-orbit updating, low cost and large storage capacity, and can realize single event upset resistance.

A data processing system is disclosed which includes a first processor having an m-byte data width, an n-byte data bus, where n is less than m, and a second processor electrically coupled to the bus which performs bus transactions utilizing n-byte packets of data. An adaptor is electrically coupled between the first processor and the bus which converts n-byte packets of data input from the bus to m-byte packets of data, and converts m-byte packets of data input from the first processor to n-byte packets of data, thereby enabling the first processor to transmit data to and receive data from the bus utilizing m-byte packets of data. In a second aspect of the present invention, a method and system are provided for arbitrating between two bus masters having disparate bus acquisition protocols. In response to a second bus master asserting a bus request when a first bus master controls the bus, control of the bus is removed from the first bus master. Thereafter, in response to a signal transmitted from an arbitration control unit to the first bus master instructing the first bus master to terminate its bus transactions, control of the bus is granted to the second bus master. In response to the second bus master terminating its bus request, control of the bus is granted to the first bus master and a signal is transmitted from the arbitration control unit to the first bus master acknowledging the grant of control.

The present invention is detection and display method and device for computer self-test information. The method includes in the power-on self test (POST) state executing curing program in the BIOS in the POST stage of computer system to send POST information in certain data structure to controller chip and transmit the information to the display module timely so as to display the POST procedure and information in characters and sentences; and displaying fault information, if any, in the display module. The device for the detection and display includes a controller connected to the system control bus of the computer mainboard to obtain POST information; and a display module connected to the controller to display real-time POST information. The present invention makes it possible to display POST information conveniently and intuitively.

A machine, system and method for user-guided teaching of deictic references and referent objects of deictic references to a conversational system. The machine includes a system bus for communicating data and control signals received from the conversational system to the computer system, a data and control bus for connecting devices and sensors in the machine, a bridge module for connecting the data and control bus to the system bus, respective machine subsystems coupled to the data and control bus, the respective machine subsystems having a respective user interface for receiving a deictic reference from a user, a memory coupled to the system bus for storing deictic references and objects of the deictic references learned by the conversational system and a central processing unit coupled to the system bus for executing the deictic references with respect to the objects of the deictic references learned.