52 results about "DIMM" patented technology

The invention relates to the technical field of heat dissipation performance testing, and discloses a heat dissipation performance testing system of a water-cooling radiator and a testing method of the heat dissipation performance testing system. The method comprises the steps that real-time temperature distribution data of a CPU, a DIMM and a GPU in a supercomputing server under a preset load are collected, and meanwhile the inlet temperature, the outlet temperature and flow parameters of cooling liquid of the integrated liquid cooling radiator are recorded. A three-dimensional heat conduction field model is constructed based on the data, and a local heat exchange coefficient matrix between the surface of each chip and the cooling liquid is obtained through calculation. And inputting the matrix into a fluid dynamic simulation network, and generating a turbulence intensity distribution diagram of the flowing state of the cooling liquid in the cold plate by combining a viscosity change curve of the cooling liquid and micro-channel structure parameters of the cold plate. Dividing a heat dissipation performance evaluation area according to the distribution diagram, and extracting cooling liquid flow velocity fluctuation characteristics for an area with turbulence intensity higher than a first threshold value; and marking the defect coordinates of the micro-channel structure for the region with the turbulence intensity lower than a second threshold value.

The present disclosure belongs to the technical field of storage chip designs. Disclosed are a memory module and an electronic device. The memory module includes at least two memory expander controller (MXC) chips, a peripheral component Interconnect express (PCIe) golden finger, a multichannel input / output (MCIO) connector, and a dual inline memory module (DIMM), wherein the MXC chips are connected to the DIMM through a double data rate 5 (DDR5) synchronous dynamic random access memory (DRAM) interface controller port, a compute express link (CXL) port of at least one of the MXC chips interacts with an external device through the PCIe golden finger, and the CXL port of at least one of the MXC chips interacts with the external device through the MCIO connector. The present disclosure may improve the memory capacity of the memory module.

A cooling assembly for liquid cooling of a heat-generating component such as a dual in-line memory module (DIMM) in a computer device is disclosed. The cooling assembly includes a bracket holding a micro-pipe assembly. The micro-pipe assembly has a cold manifold, a hot manifold and a series of micro-pipes. The micro-pipes are fluidly coupled between the cold manifold and hot manifold to allow coolant flow between the cold manifold and the hot manifold. The bracket positions the micro-pipe assembly such that micro-pipes are positioned proximate to opposite sides of the heat-generating component. A coolant inlet supplies coolant to the cold manifold and a coolant outlet collecting coolant from the hot manifold.

An apparatus for DIMM cooling includes an inflatable cold plate configured for placement in a slot between two memory cards connected to a motherboard of a computing device. The inflatable cold plate expands to contact the two memory cards in response to pressure from a cooling fluid and the inflatable cold plate is configured to transfer heat from the two memory cards to the cooling fluid. The inflatable cold plate is in fluid communication with a fluid pump configured to pump the cooling fluid through the inflatable cold plate at a sufficient pressure to pressurize the inflatable cold plate against the two memory cards and to circulate the cooling fluid through the inflatable cold plate to transfer heat from the inflatable cold plate.

A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

The embodiment of the application provides a kind of storage extension equipment and computing device, including: cable interface, PCIE interface, first CXL controller, second CXL controller and DIMM;First CXL controller connects first part DIMM, and second CXL controller connects second part DIMM;First part CXL interface of first CXL controller connects cable interface, and second part CXL interface connects PCIE interface;First part CXL interface and second part CXL interface of first CXL controller can access all DIMM connected by first CXL controller;First part CXL interface of second CXL controller connects cable interface, and second part CXL interface connects PCIE interface;First part CXL interface and second part CXL interface of second CXL controller can access all DIMM connected by second CXL controller, can improve the access space of single memory access port of storage extension equipment.

The present disclosure relates to field of Dual In-Line Memory Modules that discloses method and system for generating memory maps. The method comprises detecting, by computing system, at least one of DIMM and one or more Dynamic Random Access Memory (DRAM) chips associated with computing system. The one or more accelerators are configured in at least one of DIMM and one or more DRAM chips. Further, the method includes determining accelerator information for each of one or more accelerators via at least one of Serial Presence Detect (SPD) and Multi-Purpose Register (MPR) associated with at least one of DIMM and one or more DRAM chips. Method includes generating unique memory map for each of one or more accelerators based on accelerator information of corresponding one or more accelerators. As a result, performance of computing system may be improved as accelerator capabilities of one or more accelerators are effectively utilized.

A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.

A system and method enabling the use of convection cooled dual-inline memory modules (DIMM) in non-convection environments, specifically used for computing applications for harsh environments. This system and method describes a design which transfers heat from the various components on the memory module to thermally opportunistic areas of an enclosure in the absence of sufficient or in some cases any convective cooling conditions. The system and method describes a sandwiched metal heat plate assembly, being constructed from a thermally conductive material, which is attached to a heat pipe, designed to be highly thermally conductive, which is further attached to a thermally conductive cold plate saddle, which in turn is connected to a thermal sink. The heat generated in the DIMM is conducted to the heat plate by way of a thermal interface material, this energy transferred to the heat pipe, and then to a cold plate which dissipates the energy to the ambient environment. The system does not require a plurality of fins inside the enclosure, liquid cooling, nor airflow within the enclosure to accomplish the memory thermal management. The invention includes a heat pipe saddle, a heat pipe, a clamshell heat extraction mechanism in conjunction with a thermal interface compound for improving the heat transfer from the DIMM to the heat sink.

An apparatus for DIMM cooling includes an inflatable cold plate 102 configured for placement in a slot between two memory cards 104 connected to a motherboard 106 of a computing device. The inflatable cold plate 102 expands to contact the two memory cards 104 in response to pressure from a cooling fluid and the inflatable cold plate 102 is configured to transfer heat from the two memory cards 104 to the cooling fluid. The inflatable cold plate 102 is in fluid communication with a fluid pump 114 configured to pump the cooling fluid through the inflatable cold plate 102 at a sufficient pressure to pressurize the inflatable cold plate 102 against the two memory cards 104 and to circulate the cooling fluid through the inflatable cold plate 102 to transfer heat from the inflatable cold plate 102.

Examples described herein relate to a system that includes: a first device comprising a motherboard; a second device comprising a dual in-line memory module (DIMM); and an arrangement of a signal pin and ground pin pair coupled to the motherboard and DIMM wherein portions of the signal pin and ground pin pair are proximate each other.

Storage system (1500, 2300), comprising: a plurality of non-volatile memory devices (1540, 2340); a controller (1530, 2330) in communication with the plurality of non-volatile memory devices (1540, 2340), the controller (1530, 2330) being configured to: Receiving a read command from a host (100); in response to receiving the read command from the host (100), reading data from the plurality of non-volatile memory devices (1540, 2340); Performing an operation with an indefinite duration from the host's perspective; Sending a ready signal to the host (100) after performing the operation; Receiving a send command from the host (100); and in response to receiving the send command from the host (100), sending the data to the host (100); a plurality of data buffers (1550, 2100, 2200, 2350) in communication with the controller (1530, 2330) and configured to store data sent between the controller (1530, 2330) and the host (100); and a command and address buffer (1520, 2320) configured to store commands and addresses sent from the host (100), wherein the command and address buffer (1520, 2320) is further configured to synchronize the flow of data into and out of the plurality of data buffers (1550, 2100, 2200, 2350).

System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ / MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ / MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.

Methods and apparatus for cooling of dual in-line memory modules are disclosed. An example apparatus includes: a heat pipe, and a first base to house the heat pipe. The first base is to be thermally coupled to a first side of a dual in-line memory module (DIMM). The example apparatus further includes a second base to be thermally coupled to a second side of a DIMM. The second side is opposite the first side. The second base is to be thermally coupled to the first base.

A buffer for error correction in memory modules is described. In one or more implementations, a memory module (e.g., a DIMM) configured for error correction code (ECC) includes a plurality of memory chips, wherein at least one memory chip includes memory die split between a first memory subchannel and a second memory subchannel. The memory module also includes a plurality of registered clock drivers (RCDs), wherein at least one RCD is configured to handle input addresses for both the first memory subchannel and the second memory subchannel. This configuration allows for efficient use of memory resources and flexibility in memory addressing, particularly for scenarios requiring ECC functionality or when dealing with memory chips of different capacities.

The present invention provides a skew resistance PID device and processing method that improves the parallel processing performance of an IDP (In-DIMM Processor). [Solution] The skew resistance PID device according to the present invention is composed of multiple ranks each containing multiple banks, and includes DIMMs (Dual In-line Memory Modules) including an IDP that processes internal memory operations, a memory controller, and a host CPU that is connected to the DIMM via the memory controller and replicates join keys on a bank and rank basis to improve the parallel processing performance of the IDP.

Provided is an illuminated server-specific R-DIMM, including a printed circuit board, a plurality of dynamic random access memories, a registering clock driver, and at least one light-emitting diode. The dynamic random access memories, the registering clock driver, and the at least one light-emitting diode are all arranged on the printed circuit board. As such, the illuminated server-specific R-DIMM of the present invention can emit light through the light-emitting diode under a stable current, highlighting the aesthetic appearance, which is in line with demands of the chassis design for artificial intelligence creators, game developers, and demonstration workstations or servers.

A motherboard implementing a T-topology bus architecture between a host controller and two or more DDR5 DIMM slots is combined with one or more DIMM terminator cards installed in at least one of the DDR5 DIMM slots to increase the performance of DDR5 DIMM memory accesses.

Systems and techniques for vertical module connectors with pin-clamp mechanisms are described. An example module connector includes two cross-members, with each cross-member including at least one row of pins. Upon insertion, the pins are arranged to make electrical contact with pins on a memory module (e.g., a dual in-line memory module (DIMM)). The module connector also includes a clamping mechanism (e.g., a hinge assembly) that closes a first cross-member against or towards a second cross-member in response to or after insertion of the memory module. The module connector further includes a locking mechanism to maintain a closed state of the two cross-members and provide electrical contact between the row of pins on each cross-member and pins on the memory module. The described module connector allows for the insertion of memory modules with increased pins without reduced insertion force.

A multi-slot connector having reduced DIMM-to-DIMM pitch distances can support up to 64 memory channels for next generation DDR (double data rate) technology, including DDR6. To support the increase in memory channels, while compensating for limited form factor motherboards, the multi-slot connector includes two or more slots for devices, such as DIMMs, to connect to a motherboard or other platform. Reduced pitch distances between the DIMMs, shortened connector pins, thinner contacts, and complementary reduced pitch distances in a ball grid array (BGA) used to connect to the motherboard or other platform, provides a compact multi-slot connector that can support up to 64 memory channels with improved performance characteristics. An optional cooling device can be employed between the slots as needed to maintain optimal performance.

The utility model belongs to the technical field of memory banks, and discloses a liquid cooling heat dissipation device for a DIMM, which comprises a heat conduction assembly, a liquid cooling assembly and a rotating assembly, and is characterized in that the heat conduction assembly comprises a heat conduction plate and a heat pipe, and the heat conduction plate is arranged between the heat pipe and the DIMM; the liquid cooling assembly comprises a first water collector, a second water collector and a circulating pipe, two ends of the circulating pipe are respectively communicated with the first water collector and the second water collector, one end of the heat pipe is fixedly connected with one of the first water collector and the second water collector, and the other end of the heat pipe is selectively connected with the other one of the first water collector and the second water collector; the rotating assembly is connected with the first water collector or the second water collector. Thus, the heat conducting plate and the DIMM are assembled, then the DIMM is inserted into the memory slot, the heat conducting plate can well transfer heat of the DIMM by adjusting connection between the heat conducting plate and the DIMM, the heat pipe can rotate in the direction close to or away from the heat conducting plate under the action of the rotating assembly, and enough space is conveniently reserved around the DIMM to assemble and disassemble the DIMM.

Systems and methods are disclosed that include a first memory device, a second memory device coupled to the first memory device, where the second memory device has a lower access latency than the first memory device and acts as a cache for the first memory device. A processing device, which is operatively coupled to the first and second memory devices, can track access statistics for a section of data stored at the second memory device, the section having a first granularity, and based on the access statistics, determine to update the section of data stored at the second memory device from the first granularity to a second granularity. The processing device can further retrieve additional data associated with the section of data from the first memory device and store the additional data at the second memory device to form a new section having the second granularity.

The utility model discloses a kind of PCB structure of promoting DDR5-DIMM threading capacity, including PCB board main body, a row of first pin pads is arranged on the PCB board main body, this row first pin pad includes multiple first signal pin pads and multiple first ground pin pads, the inside of one side of each first signal pin pad is opened with a first signal hole tangential to its edge, the outside of one side of the PCB board main body where each first signal pin pad is opened with first signal hole is opened with a first ground hole on the same horizontal line with the first signal hole. The utility model improves threading capacity and signal quality by optimizing the layout of signal hole and ground hole.

An apparatus is described. The apparatus includes a dual-in line memory module (DIMM) socket having a first latch and a second latch. One of the first latch and the second latch having a feature for a user to apply force to release a DIMM from the DIMM socket. The other of the first latch and the second latch not having a feature for the user to apply force so that one end of the DIMM releases before an opposite end of the DIMM during release of the DIMM from the DIMM socket.

A substrate with a hinge is disclosed. In one aspect, the substrate may be a printed circuit board (PCB) or the like with a socket configured to receive a memory module, such as a dual inline memory module (DIMM). The substrate further includes a hinge that allows the portion of the substrate with the socket to rotate ninety (90) degrees so that a memory module inserted into the socket is then parallel to the other portion of the substrate. By allowing the memory module to be so positioned, the overall shape and configuration of a module using the substrate may fit a smaller form factor.

According to the power supply management system of the computing device and the computing device, when the second terminal voltage of the control module is lower than the set value, the output power supply of the power supply unit is abnormal, at the moment, the switching module is switched to the standby power supply for supplying power, and the CPU is controlled to enter the standby state; the standby power supply supplies power to the standby voltage regulator and the memory voltage regulator, the standby voltage regulator is used for providing power for maintaining the standby function of each module in the standby state, and the memory voltage regulator is used for providing power for maintaining the original functions of the memory module and the data storage related module in the standby state. According to the embodiment of the invention, the universal DIMM can be matched based on the CPU on the market, the memory data protection after the power failure of the computing equipment is realized, the CPU does not need to support the NVDIMM, the NVDIMM does not need to be matched, and the hardware cost is reduced.

The invention relates to a cross-point array memory in a non-volatile dual in-line memory module. An indication of power loss may be received at a cross-point array memory dual in-line memory module (DIMM) operating component of a memory subsystem. The cross-point array memory (DIMM) operation component includes a volatile memory component and a non-volatile cross-point array memory component. In response to receiving the indication of power loss, a type of write operation for the non-volatile cross-point array memory component of the cross-point array memory (DIMM) operating component is determined based on a characteristic of the memory subsystem. Data stored at the volatile memory component of the cross-point array memory (DIMM) operating component is retrieved, and the data is written to the non-volatile cross-point array memory component of the cross-point array memory (DIMM) operating component by using the determined type of write operation.

A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In one embodiment, a memory system includes a set of memory modules, each memory module including one or more quasi-volatile memory circuits interconnected to at least one memory controller where each memory module includes a set of memory ports; a DIMM controller and processor in communication with each of the memory modules; and multiple processor ports to be coupled to respective processing units external to the memory system. The memory ports of each memory module are coupled to the processor ports and to the DIMM controller and processor so that each memory module is accessible by respective processing units that are coupled to the processor ports and by the DIMM controller and process.

Binary sparse encoding of data can be used to reduce an amount of data read from the stochastic associative memory while processing a query. Read performance of the stochastic associated memory is optimized to enhance the query throughput by modifying access patterns to reduce the time to read the stochastic associated memory. Read performance of the stochastic associative memory can be further improved through the use of cluster aware sharding and replication for parallelized similarity search. Clusters are partitioned across multiple Dual In-line Memory Modules (DIMMs), each DIMM including stochastic associative memory, to achieve maximum latency advantage.

A translation cache and configurable error checking and correction (“ECC”) memory reduces ECC memory overhead. The translation cache supports a configurable ECC memory capable of storing a portion of a cache line, along with any ECC data, in corresponding parts of memory devices to reduce the ECC memory overhead in a memory subsystem. The corresponding parts include any same one of an upper, lower, left or right part of memory devices in a memory module, including dynamic random access memory (“DRAM”) devices in a dual inline memory module (“DIMM”).