4 results about "DIMM" patented technology

Systems and methods are disclosed that include a first memory device, a second memory device coupled to the first memory device, where the second memory device has a lower access latency than the first memory device and acts as a cache for the first memory device. A processing device, which is operatively coupled to the first and second memory devices, can track access statistics for a section of data stored at the second memory device, the section having a first granularity, and based on the access statistics, determine to update the section of data stored at the second memory device from the first granularity to a second granularity. The processing device can further retrieve additional data associated with the section of data from the first memory device and store the additional data at the second memory device to form a new section having the second granularity.

The utility model discloses a kind of PCB structure of promoting DDR5-DIMM threading capacity, including PCB board main body, a row of first pin pads is arranged on the PCB board main body, this row first pin pad includes multiple first signal pin pads and multiple first ground pin pads, the inside of one side of each first signal pin pad is opened with a first signal hole tangential to its edge, the outside of one side of the PCB board main body where each first signal pin pad is opened with first signal hole is opened with a first ground hole on the same horizontal line with the first signal hole. The utility model improves threading capacity and signal quality by optimizing the layout of signal hole and ground hole.

A memory module adapter card can adapt multiple compression-attached memory modules (CAMMs) to a dual inline memory module (DIMM) connector. Multiplexer circuitry on the adapter card enables multiplexing data amongst the memory modules attached to the adapter card during a same burst access sequence.

The present invention relates to a memory module having an electronic fuse which protects devices within the memory module by shutting off excessive current or voltage in an electrical overstress condition in which the excessive current or voltage is applied, the memory module comprising: a memory device array composed of a DDR SDRAM; a register clock driver chip which distributes signals received from a memory controller to the memory device array; a power management integrated circuit chip which distributes and supplies input power to components including the memory device array and an RCD; a serial configuration recognition chip which stores initial device information; and an electronic fuse which shuts off the input power when the input power is under electrical overstress, wherein the memory module may further comprise an electronic fuse integrated package in which the register clock driver chip or the power management integrated circuit chip and the electronic fuse are embedded in a single package.