13 results about "Host controller interface" patented technology

The invention relates to a universal serial bus hub device and a control method thereof. The universal serial bus hub device comprises a first downlink port, an extensible host controller interface, a second downlink port, a router and an uplink port. The first downlink port is configured to receive first universal serial bus data. The extensible host controller interface is configured to convert the first universal serial bus data to peripheral component interconnect express data. The second downlink port is configured to receive second universal serial bus data. The router is configured to convert the peripheral component interconnect express data to the first tunnel data and convert the second universal serial bus data to the second tunnel data. The uplink port is configured to output the first tunnel data and the second tunnel data.

A first device and a method performed by the same are provided. The method comprises the following steps: a first host sends an HCI setting minimum encryption key size command to a first controller through a first host controller interface (HCI), wherein the HCI setting minimum encryption key size command comprises a parameter for specifying a minimum encryption key size; and receiving, by the first host, an HCI encryption change event from the first controller via the first HCI, the HCI encryption change event comprising a first parameter indicating that an encryption change has occurred, where the HCI encryption change event comprising a second parameter specifying a size of a key for encryption, the first controller does not negotiate a key size less than the minimum encryption key size, where the HCI encryption change event further includes a third parameter for an identifier of a connection between the first device and the second device, where the HCI encryption change event occurs on the first device, and where the first controller does not negotiate a key size less than the minimum encryption key size. To inform the first host when a change has occurred for connection encryption present between the first device and the second device.

The application discloses a high-availability array type USB device management system and method. The system comprises an embedded control surface module, a data surface cascade module and a power surface independent control module; the data surface cascade module comprises a hub controller and a plurality of USB physical ports; the power surface independent control module comprises a load switch for independent power supply of the ports and an analog-to-digital converter for collecting power supply current characteristics; a host computer end is configured with a virtual host controller interface driver; the embedded control surface module obtains characteristic quantity to calculate a deadlock state evaluation factor, controls power supply reset when the evaluation factor is over a threshold value, intercepts a request block, encapsulates a custom topology header and sends the custom topology header to the host computer end to build a virtual topology tree in a kernel. The application can accurately identify a bottom-layer hardware deadlock and apply hard isolation, isolate system device enumeration disorder caused by peripheral reset and ensure that an automatic control instruction has absolute physical certainty.

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device (FMD). The HCI is configured to obtain an indication that a size of a particular write buffer (WB) of the FMD is to increase. The FMD includes a plurality of memory resources including a plurality of logical units (LUs) and at least a particular WB. The HCI is also configured to select a particular memory resource for write buffer reallocation based at least in part on a particular usage metric for the particular memory resource.

In a multi-processor computing device having a Universal Flash Storage (UFS) host controller interface operating in Multi-Circular Queue (MCQ) mode, mappings between processors and completion queues (CQs) may be dynamically changed based on one or more conditions. A condition may be detected that may impair the performance of one of the processors in accessing a CQ. When such a condition is detected, the UFS host controller system may update a queue-to-processor mapping, which may include replacing an association between a CQ and a processor with an association between the CQ and another processor.

The present application relates to the technical field of computers. Disclosed are a method for managing hard disks, and a computer device and a storage medium. The method comprises: receiving asynchronous event data of a target asynchronous event associated with a target non-volatile memory host controller interface hard disk; controlling the target non-volatile memory host controller interface hard disk to be in a read-only state or a non-writable state; when it is determined on the basis of the asynchronous event data of the target asynchronous event that the target non-volatile memory host controller interface hard disk needs to be deleted from a target redundant array of independent disks, deleting the target non-volatile memory host controller interface hard disk from the target redundant array of independent disks, and switching a non-volatile memory host controller interface hard disk provided to a target database from the target non-volatile memory host controller interface hard disk to another non-volatile memory host controller interface hard disk in the target redundant array of independent disks.

A Universal Flash Storage (UFS) host controller supporting input / output virtualization (IOV) is disclosed. The host controller comprises a programmable Function ID (FID) to Stream ID (SID) mapping unit configured to assign unique stream IDs to physical and virtual UFS Host Controller Interface (UFSHCI) functions. The mapping unit includes registers accessible only within the physical UFSHCI's address space, allowing exclusive control by the host operating system. When a data transfer request is received, the host controller maps it to an assigned stream ID based on the programmable mapping. A UFS device coupled to the host controller validates received stream IDs before executing data transfer requests. This mechanism enables isolation of data streams between virtual functions, enhancing security in virtualized storage environments and accommodating evolving system requirements.

The application discloses a data processing method, device and equipment and a readable storage medium in the technical field of storage, and the method comprises the following steps: receiving a read-write command sent by a host based on a non-volatile memory host controller interface protocol; in the process of analyzing the read-write command to determine to-be-processed data, determining a data cache mark of the to-be-processed data by using a command extension type field in the read-write command; determining a cache mode corresponding to the data cache mark; and processing the to-be-processed data according to a cache strategy matched with the cache mode and responding to the host. In the application, the read-write command sent by the host can control the VWC behavior in the NVMe device, so that the NVMe device can be compatible with the requirements of multiple scenes and the VWC can exert the maximum performance.

A host controller interface configured to provide interfacing between a host device and a storage device includes processing circuitry; a doorbell register configured to store head and tail pointers for one or more first queues; and an entry buffer configured to store a first command from a first queue of the one or more first queues, wherein the processing circuitry is configured to determine an order in which commands of the one or more first queues are to be processed, route the first command to be stored in the entry buffer according to the determined order, and route a first response to be stored in a second queue of one or more second queues.

A host device includes a system memory that includes a logical-to-physical (L2P) cache and a second cache. The host device also includes a host controller interface (HCI) configured to be coupled to the flash memory device. The HCI is configured to determine that a particular region of the L2P address mapping table is to be removed from the L2P cache. The L2P address mapping table is configured to include a mapping between logical memory addresses and physical memory addresses of the flash memory device. The HCI is also configured to identify a particular sub-region of the particular region that has an access metric that satisfies a retention criterion. The HCI is further configured to store the particular sub-region into the second cache. The HCI is also configured to remove a particular region from the L2P cache.

The application discloses a communication transmission method and product, electronic equipment and medium, and relates to the technical field of storage. In the method, a host end determines a non-volatile memory host controller interface specification protocol command according to address information of a device managed by the host end, and sends the command to the device, so that any device can obtain address information of other devices, which is a prerequisite for realizing direct data transmission between devices. Further, the host end determines an end-to-end data transmission instruction according to address information of a source device and address information of a target device, and sends the instruction to the source device. That is, in the method, in the case that any device stores address information of other devices, an end-to-end data transmission instruction of the source device and the target device is added, so that the source device and the target device can directly perform data transmission, that is, bypassing the host memory transfer, the number of data copying times is reduced, and the delay and the occupation of host resources are reduced.

A universal serial bus (USB) hub includes a first downstream facing port (DFP), an extensible host controller interface (xHCI), a second downstream facing port (DFP), a router, and an upstream facing port (UFP). The first downstream facing port (DFP) is configured to receive a first universal serial bus (USB) data. The extensible host controller interface (xHCI) is configured to convert the first universal serial bus (USB) data into a peripheral component interconnection express (PCIe) data. The second downstream facing port (DFP) is configured to receive a second universal serial bus (USB) data. The router is configured to convert the peripheral component interconnection express (PCIe) data into a first tunneling data, and convert the second universal serial bus (USB) data into a second tunneling data. The upstream facing port (UFP) is configured to output the first tunneling data and the second tunneling data.

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device and configured to receive a notification from the flash memory device that a performance threshold register value has been exceeded when the flash memory device is configured to use a shared write buffer. The HCI is further configured to perform a remedial action in response to receiving the notification, the remedial action including reallocating a portion of the first logical unit (LU).