422 results about "Dataflow" patented technology

An architecture capable of stream parsing of the H.264 Content Based Adaptive Binary Arithmetic Coding (CABAC) format is disclosed. The architecture employs a two pass dataflow approach to implement the functions of CABAC bit parsing and decoding processes (based on the H.264 CABAC algorithm). The architecture can be implemented, for example, as a system-on-chip (SOC) for a video/audio decoder for use high definition television broadcasting (HDTV) applications. Other such video/audio decoder applications are enabled as well.

System and method for creating and executing a graphical program. A first plurality of graphical program elements (GPEs) having a first model of computation (MoC), e.g., homogenous dataflow, are assembled in a graphical program in response to first input. A structure, including an interior portion, is displayed in the graphical program, indicating use of a second MoC, e.g., multi-rate dataflow, for GPEs within the interior portion. A second plurality of GPEs having the second MoC are assembled within the interior portion of the structure in response to second input. The second plurality of GPEs are converted into a new third plurality of GPEs having the first MoC, e.g., by parsing the second plurality of GPEs to determine multiple primitives according to the second MoC, determining the third plurality of GPEs based on the primitives, and assembling the third plurality of GPEs in the graphical program.

The application of a watershed algorithm to pixels and their touch values obtained from a scan of a touch sensor panel to determine patches corresponding to images of touch is disclosed. Prior to applying the watershed algorithm, background pixels having little or no touch values can be eliminated. A primary merge algorithm can then merge adjacent patches together when the saddle point between them is shallow as compared to the peak represented by the patches. However, if two candidate patches for merging have a total number of pixels below a certain threshold, these two patches may not be merged under the assumption that the patches might have been caused by different fingertips. Conversely, if two candidate patches for merging have a total number of pixels above a certain threshold, these two patches can be merged under the assumption that the patches were caused by a single thumb or palm.

A graphical representation of the firewall and a network coupled to the firewall is generated and displayed. A number of an inbound port of the network is displayed. An arrow adjacent to the port number pointing toward the network is displayed to indicate that a communication is permitted to the port. The port number and the arrow are located between an icon for the network and an icon for the firewall. A port number of a destination of a communication originating from the network is displayed. Also, another arrow adjacent to the destination port number pointing toward the firewall is displayed to indicate that a communication is permitted to the destination port number. The destination port number and the other arrow are located between an icon for the network and an icon for the firewall. A table including definitions of a plurality of rules is generated and displayed. Each of the definitions includes entries for a source IP address and destination IP address of a permitted but vulnerable data flow. The source IP address and destination IP address entries are color coded to indicate security levels of respective source and destination networks. Another table includes definitions of a misconfigured data flow, and entries for a source IP address and destination IP address of the misconfigured data flow. The source IP address and destination IP address are color coded to indicate security levels of respective source network and destination network.

A method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement is provided. The method includes combining a plurality of cells and arithmetic units to form a plurality of groups, assigning a cache unit to a group, and connecting the cache unit to a higher level unit via a tree structure. The cache unit may send requests for required commands to the higher level cache unit, which may return a command sequence including the required command, if the higher level cache unit holds the first command sequence including the required command in the higher level cache unit's local memory.

A scalable pipelined pixel shader that processes packets of data and preserves the format of each packet at each processing stage. Each packet is an ordered array of data values, at least one of which is an instruction pointer. Each member of the ordered array can be indicative of any type of data. As a packet progresses through the pixel shader during processing, each member of the ordered array can be replaced by a sequence of data values indicative of different types of data (e.g., an address of a texel, a texel, or a partially or fully processed color value). Information required for the pixel shader to process each packet is contained in the packet, and thus the pixel shader is scalable in the sense that it can be implemented in modular fashion to include any number of identical pipelined processing stages and can execute the same program regardless of the number of stages. Preferably, each processing stage is itself scalable, can be implemented to include an arbitrary number of identical pipelined instruction execution stages known as microblenders, and can execute the same program regardless of the number of microblenders. The current value of the instruction pointer (IP) in a packet determines the next instruction to be executed on the data contained in the packet. Any processing unit can change the instruction that will be executed by a subsequent processing unit by modifying the IP (and/or condition codes) of a packet that it asserts to the subsequent processing unit. Other aspects of the invention include graphics processors (each including a pixel shader configured in accordance with the invention), methods and systems for generating packets of data for processing in accordance with the invention, and methods for pipelined processing of packets of data.

A method for processing messages is provided where at least one algorithmic conduit is defined, and at least one conduit rule for controlling at least one algorithmic conduit is defined. An algorithmic conduit is a persistent connection, controlled by explicit, independent, dynamic rules, and capable of processing messages among data communicators such as devices, systems, or programs. Messages can be monitored, filtered, transformed, correlated, or processed in other ways without modifying the data communicators. A message conduit hub system allows creation and management of algorithmic conduits to serve as active, virtualized links carrying rules-based data streams among configurable endpoints. These “smart” connections are managed using parameters, logic, and other control interfaces for tailoring behavior to a particular application, site, or user. A message conduit hub system may be implemented as a stand-alone device, as part of a larger system, or as an “encapsulation layer” for an existing application.

Described herein is an operator-based approach to representing dataflows. A dataflow is a set of one or more operations and one or more flows of data that are processed successively by the set of operations. A dataflow is described by a generic description in which operations in a dataflow are represented by operators. An operator defines a primitive operation (e.g. join, filter), specifying not only the type of operation, but the inputs and outputs, rules, and criteria that govern the operation. From the generic description, a code implementation is generated that may be completely executed on a source database system and target data warehouse, without need for an intermediate system to participate in the execution of the code implementation, such as a data movement engine.

A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.

A mobile communication system is provided which is capable of preventing a reduction in user throughput and system throughput. In a radio base station, a dataflow control unit controls an Iub dataflow from an RNC, a buffer stores the dataflow for each terminal in each corresponding queue, and a scheduler schedules the dataflow. An HARQ control unit controls retransmission of the dataflow and corrects CQI report values received from a terminal at a corrector. An encoding processor encodes the dataflow, and a demodulator demodulates data received from the terminal. After the demodulation of the data received from the terminal, the demodulator sends CQI information and Ack/Nack information to the HARQ control unit. The corrector in the HARQ control unit then corrects the CQI report value in accordance with these received CQI information and Ack/Nack information.

A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

A method and system for developing data integration applications with reusable semantic types to represent and process application data. Methods include creating schemas to describe external data, creating semantic types to describe internal data, mapping schemas to semantic types, developing dataflows that configure input and output operations using schemas, mappings, and semantic types and all other transformation operations and functions based solely on semantic types, and executing dataflows defined in this manner.

A method for processing instructions and data in a processor includes steps of: preparing an input stream of data for processing in a data path in response to a first set of instructions specifying a dynamic parameter; and processing the input stream of data in the same data path in response to a second set of instructions. A common portion of a dataflow is used for preparing the input stream of data for processing in response to a first set of instructions under the control of a dynamic parameter specified by an instruction of the first set of instructions, and for operand data routing based on the instruction specification of a second set of instructions during the processing of the input stream in response to the second set of instructions.

A method and apparatus for detecting polymorphic viral code in a computer program is provided. The apparatus comprises an emulator, an operational code analyzer and an heuristic analyzer. The emulator emulates a selected number of instructions of the computer program. The operational code analyzer collects and stores information corresponding to operands and operators used in the instructions and the state of registers/flags after each emulated instruction execution. The heuristic analyzer determines a probability that the computer program contains viral code based on an heuristic analysis of register/flag state information supplied by the operational code analyzer.

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. More specifically, embodiments of the present invention are directed to an instruction set of an object memory fabric. This object memory fabric instruction set can be used to provide a unique instruction model based on triggers defined in metadata of the memory objects. This model represents a dynamic dataflow method of execution in which processes are performed based on actual dependencies of the memory objects. This provides a high degree of memory and execution parallelism which in turn provides tolerance of variations in access delays between memory objects. In this model, sequences of instructions are executed and managed based on data access. These sequences can be of arbitrary length but short sequences are more efficient and provide greater parallelism.

Methods and systems for converting synchronous circuit designs to asynchronous circuit designs, and particularly programmable asynchronous circuit designs. Provide is a systematic, workable and repeatable process for evaluating synchronous circuit designs, converting the wires, switches/connections and logic functions to equivalent-function asynchronous circuit designs and hence implementing a functionally equivalent asynchronous circuit with all the benefits thereof. Further provided are a process for systematically doing the conversion and hardware equivalents (in form or functional description) for the asynchronous components. Using the present invention, any synchronous circuit design can be converted to an asynchronous equivalent, typically with no change to the original design implementation.

A data processing apparatus has an interpreter environment for dynamically implementing a program constructed based on a command set defined independently of a native command group, in a native environment constructed based on the native command group processed by a processor configuring hardware. The apparatus generates an intermediate data stream in each of a plurality of stages into which an input data stream is divided in interpretation in the native environment and filters the intermediate data stream to generate a filtered data stream in the interpreter environment.

A microprocessor coupled to a system memory includes a load request signal that requests data be loaded from the system memory into the microprocessor in response to a load instruction. The load request signal includes a load virtual page address. The microprocessor also includes a prefetch request signal that requests a cache line be prefetched from the system memory into the microprocessor in response to a prefetch instruction. The prefetch request signal includes a prefetch virtual page address. The microprocessor also includes a memory subsystem including a first translation look-aside buffer (TLB) that translates the load virtual page address into a load physical page address, and a second TLB that translates the prefetch virtual page address into a prefetch physical page address.

A method of evaluating an architecture for an integrated circuit device is disclosed. The method comprises generating a library of primitives for a predetermined architecture; transforming an original dataflow program into an intermediate format; transforming the intermediate format to a dataflow program defined in terms of the predefined library of primitives; and generating an implementation profile comprising information related to an implementation of the original dataflow program in an integrated circuit having the predetermined architecture. A method of evaluating an architecture for an integrated circuit device is also disclosed.