41 results about "Analog computer" patented technology

The invention discloses a memory power consumption test system, method and device, and relates to the technical field of computers, a test controller with a computer fast interconnection core, a load generator and a first board card are adopted to build a simulation working environment of a computer fast interconnection memory, the test controller issues a test command to the load generator, and the test command is sent to the first board card. The load generator simulates computer fast interconnection transaction operation on the tested memory according to the test command, and the test controller synchronously collects state parameters of the tested memory to calculate power consumption data when the tested memory executes the computer fast interconnection transaction operation; therefore, the power consumption data when the computer fast interconnection memory executes the computer fast interconnection transaction can be measured, and the power consumption characteristics of the computer fast interconnection memory in different working states can be accurately measured and analyzed. The problem that a traditional memory power consumption test scheme cannot accurately simulate a working scene of a computer fast interconnection memory and cannot obtain an accurate test result is solved.

A computer-implemented method of simulating a propagation of a malware through a set of computer systems, the method comprising: identifying a simulated computer system infected with a simulated malware; determining a first signature of the simulated malware; determining that a mutation condition for the simulated malware has been met; and in response to determining that the mutation period has been met, changing the first signature of the simulated malware to a second signature.

A computer-implemented method of simulating a propagation of a malware through a set of computer systems, the method comprising: identifying a simulated computer system infected with a simulated malware; determining a first signature of the simulated malware; determining that a mutation condition for the simulated malware has been met; and in response to determining that the mutation period has been met, changing the first signature of the simulated malware to a second signature.

An operator learning model generator is provided for training a smoothed operator learning model for predicting airflow dynamics in a room used by a controller connected to a heating, ventilation, and air conditioning (HVAC) system. The operator learning model generator includes an interface circuit configured to receive a training dataset via a network connected to a simulation computer, wherein the training dataset includes un-trajectories of airflow in the room for various time series of control actions applied to the HVAC system; a memory configured to store the smoothed operator learning model including an autoencoder and a neural ordinary differential equation, the training dataset, and training instructions for the smoothed operator learning model; and a processor configured to train the smoothed operator learning model stored in the memory, wherein the training instructions include jerk regularization that constrains smoothness of dynamics predicted by the smoothed operator learning model.

The invention discloses an image seeker tracking performance test method based on a simulated moving target, which comprises the following steps of: generating a simulated target and a moving track through a target simulation computer, projecting the simulated target and the moving track to a curtain, and tracking the simulated target on the curtain by an image seeker to realize the tracking speed precision and the maximum tracking speed test; then the size of the target under the tracking distance is obtained through calculation, the target simulation computer generates a simulation target and a motion trail and projects the simulation target and the motion trail to the curtain, the image seeker tracks the simulation target on the curtain through the reflective collimator, and tracking distance testing is achieved. A dynamic simulation target is provided for image seeker tracking, meanwhile, external field environment factors such as target definition, light intensity and target shielding are introduced, and the method has the advantages that the testing method is simple, the testing environment is easy to build, and online tracking debugging and synchronous testing are facilitated.

A switchless computer mouse comprising: a keyplate operable to be depressed over a range of motion; a conductive element coupled to the keyplate; a sensor configured separate from the conductive element; a haptic element; and one or more processors operable to: control the sensor to detect a position of the conductive element over the keyplate range of motion; and control the haptic element to generate a haptic feedback when the sensor detects that the position of the conductive element corresponds to a preset threshold position within the range of motion.

The invention discloses a flight-engine coupling-based propulsion system simulation architecture, relates to the technical field of aircraft simulation, and is used for solving the technical problem of dynamic response mismatch of a flight control system and an engine in an existing simulation platform. The flight-launch coupling-based propulsion system simulation architecture comprises a propulsion terminal module, a flight management computer module, an engine simulation computer and a pilot cockpit system, the propulsion terminal module is provided with a sequential logic and state management mechanism and is used for simulating an execution unit response process and a fly-by-wire accelerator process when the aircraft is started; the flight management computer module is used for carrying out automatic control and resolving functions and carrying out automatic accelerator resolving, accelerator mode switching and flight launching instruction management; the engine simulation computer is used for performing dynamic simulation tasks of an engine control system and engine performance; and the pilot cockpit system is used for receiving pilot operation input and displaying state feedback of the simulation architecture.

The invention relates to a method for operating at least one electrochemical system (1), in particular an electrochemical system for producing hydrogen. According to the invention, at least one operating variable is modeled on an analog computer (4), said operating variable being dependent on the operation of the electrochemical plant (1) and being detectable by means of a sensor (6), the analog computer (4) reads out operating data from a control computer (3) for controlling the electrochemical system (1) and uses the operating data to reflect the actual operating state. The invention further relates to a simulation computer (4) for carrying out the steps of the method according to the invention, the simulation computer (4) being designed to carry out the simulation during ongoing operation of the electrochemical plant (1).

The invention provides an embedded digital-analog hybrid array system and method based on modular mosaic units. The method comprises the steps that a tested radar transmits a radar signal in a real-time coupling mode; the cluster scene mapping unit resolves cluster scene time-space-spectrum-energy information under the unified coordinate system in real time and generates corresponding control parameters; the digital-analog hybrid system control unit calculates array control parameters of the analog array and the digital array according to the control parameters; the digital-analog mixing unit completes cluster scene simulation according to the array control parameters and completes cluster target characteristic dynamic simulation; and the computer real-time control unit controls the working time sequence and information interaction of other modules in real time according to the input signal, solves a three-axis control instruction of the flight turntable in real time, and sends the instruction to the cluster scene mapping unit and the flight turntable. According to the invention, cluster target simulation is completed through an embedded digital array, and dynamic simulation of electromagnetic characteristics of a cluster complex scene is rapidly realized.

This application provides a dental simulation workbench training system and method based on spatial computing technology, for solving problems that prior simulator only supports single-player use, only trains based on an oral model, lacks full-process doctor-patient communication. A virtual-real fusion head-mounted display acquires positioning data of physical objects in real space. A situation observation server arranges virtual entities and generates a scene file. A simulation computer generates a mixed-reality treatment scenario, a virtual patient, and dental instruments from the scene file, allowing a complete patient journey, from entry to the end of treatment, to be replicated. Force sensation information is generated, and both poses of a force tool and a virtual tool are controlled to match with a pose of a force feedback tool. A user wears the head-mounted display to perform treatment. Multiple people are supported to watch the treatment of the same dental simulation workbench through a network.

A method to debug instruction execution errors in a simulated computer system is provided. The method includes generating two separate simulations of the same system and causing a code including a set of instructions to execute on the two separate simulations. The computer implemented method further includes performing an efficient trace operation starting from a start instruction to an end instruction of the set of instructions on the two separate simulations. When trace operation is performed, an instruction execution deviation is identified between the code executed in the two separate simulations by comparing checksum values at a reporting frequency, determining that the comparison of the checksum values indicates a mismatch, and using instruction count and the reporting frequency to capture at least one instruction leading up to the instruction execution deviation.

A polyhedral reduced-order model (ROM) generator is provided for use by an optimization controller in a heating, ventilation, and air conditioning system. The physical model generator includes: interface circuitry for receiving a training dataset via a network connected to an analog computer; a memory for storing the polyhedral ROM for predicting the dynamics of airflow in a room, the training dataset, and instructions for calculating parameters of the polyhedral ROM; and a processor for calculating the parameters of the polyhedral ROM. The computation includes computing a global projection operation from a higher-dimensional state to a reduced-order state, computing a global lifting operation from the reduced-order state to a higher-dimensional state, constructing a local reduced-order model of the reduced-order state dynamics for each physical parameter value in the training dataset, and generating the polyhedral ROM by combining a weighted average of the local reduced-order model with the projection and lifting between the reduced-order state and the full state.

The present invention relates to the field of artificial intelligence technology, and discloses an analog computer chip; the analog computer chip includes an input layer, N addition layers and an output layer; each addition layer includes multiple adders; each input interface in the input layer is connected to each adder in the first addition layer through different operation units; in the N addition layers, each adder in the upper addition layer is connected to each adder in the lower addition layer through different operation units; each operation unit has a transfer function corresponding to its node parameter; and multiple adders in the Nth adder layer are connected one-to-one with multiple output interfaces in the output layer; the operation units and adders are both composed of analog devices. In the above scheme, using the analog computer chip as an artificial intelligence chip can reduce the size of the artificial intelligence chip, increase the speed of the artificial intelligence chip, and reduce the power consumption of the artificial intelligence chip.

A training round for performing indirect fire mission, including a top end oriented towards a direction of projectile motion of the training round. A bottom end is situated opposite to the top end. The top end and the bottom end are separated by a first distance. An adjuster is arranged between the top end and the bottom end to adjust a length of the training round. The adjuster compresses such that the top end and the bottom end are separated by a second distance. The second distance is less than the first distance. A round sensor attached to the training round and communicatively couples to a simulation computer while performing the indirect fire training mission.

The present invention relates to the field of artificial intelligence technology, and discloses a working method for simulating a computer chip. The method includes: receiving training data and initial values of model parameters; the initial values of the model parameters are used to initialize the parameters of the storage arithmetic unit; according to the training data, the regulator iteratively updates the parameters of the storage arithmetic unit, and when the iteration completion condition is satisfied, a first arithmetic model corresponding to the storage arithmetic unit is generated; inputting the model input value corresponding to the first target scenario into the analog computer chip, and outputting the model output value corresponding to the first target scenario through the first arithmetic model in the analog computer chip. The above solution can autonomously generate an arithmetic model inside the analog computer chip and can perform self-learning updates, thereby increasing the application scope of the working method and improving the accuracy of the artificial intelligence chip applying the working method.

A compact flight simulation system uses a flight simulation platform having a base and a simulator cabin positioned above the base. A plurality of actuators is connected between the base and a side of the simulator cabin in a location on the side of the simulator cabin substantially corresponding to a center of mass of the simulator cabin. The simulation system has a simulation computer receiving flight control signals from the simulator cabin and outputting a simulated flight state to an actuation controller, wherein the actuation controller controls movement of the plurality of actuators. The compact flight simulation system provides a motion platform design with maximal range within a constrained space, a motion cueing optimized motion envelope, and dynamic characteristics.

The present application discloses a highly integrated analog computer chip, which relates to the field of artificial intelligence chips. The analog computer chip includes an input end, multiple storage modules, multiple operation modules and an output end; the input end includes multiple input interfaces for inputting external voltage signals; the storage modules and the operation modules are both composed of analog devices, and are respectively configured as n-level storage modules and n-level operation modules, and the storage modules and operation modules at each level are cascaded in sequence; the output end includes multiple output interfaces for outputting the voltage signal generated by the n-th level operation module. The storage module and the operation module of the analog computer chip only require a few analog components to realize the transfer operation, which improves the integration of the chip. At the same time, the input voltage signal is nonlinearly transformed through the storage module, and then the accumulation operation is performed through the operation module, and then enters the next level to circulate in sequence, which greatly simplifies the network architecture and further improves the integration of the chip.

A method and system for executing external software code with a computer application. The method includes generating test data inputs based on values of interest in the external software code; generating simulations, including simulation parameters based on the values of interest in the external software code, to emulate the behavior of the computer application; executing the external software code in test iterations, using the test data inputs and simulations, in a sandbox environment isolated from a production environment; monitoring a line coverage of the external software code during the execution of the external software code; determining whether the line coverage of the external software code meets the predetermined completion threshold value; and in response to determining that the line coverage of the code meets the predetermined completion threshold value, verifying the external software code for use with the computer application in the production environment, and executing the external software code.

The present invention relates to the field of artificial intelligence technology, and discloses a method for generating a model of a simulated computer chip. The method includes: obtaining a training data set; iteratively updating a neural network model according to the training data set until an iteration condition is met, so as to obtain target parameter values of various transfer functions in the neural network model; wherein, the neural network model includes n layers of computing nodes, and any computing node in each layer of computing nodes is connected to each node in the upper layer through different transfer functions; the target parameter values of the transfer functions between the computing nodes are used to correspondingly set the parameters of the computing units between the adders in the model of the simulated computer chip, thereby generating the model of the simulated computer chip; the topological structure of the model of the simulated computer chip is the same as the topological structure of the neural network model. The above solution enables the simulated computer chip to have stronger computing power and faster computing speed when having the same volume.

The present invention relates to the field of artificial intelligence technology, and discloses an analog computer chip with an on-chip training system. In the computing structure of the analog computer chip, the input end of the analog computer chip is connected to the output end of the analog computer chip through n-layer memories and n-layer operators, and two adjacent layers of operators are connected through a layer of memory; the on-chip training system includes an error threshold comparator, an n-layer trainer, and an n-layer updater; the output end of the analog computer chip is also connected to the error threshold comparator; the error threshold comparator is used to control the working state of the on-chip training system according to the difference between the actual output value and the expected output value of the output end of the analog computer chip. The on-chip training system is set in the analog computer chip of the present application, and the computing model is generated autonomously, and self-learning updates are performed, thereby improving the accuracy of the artificial intelligence chip and expanding the application scope of the artificial intelligence chip.

The invention relates to a test system (1) for testing vehicle components, wherein the test system (1) has a test system (2) for physically testing at least one vehicle component (3) and a computer (4) external to the test system (2), wherein the test system (1) is configured to carry out a simulation of a behavior of the vehicle component (3) at first operating points (11) of the vehicle component (3) using at least one simulation module (5) of the test system (1) and to carry out a check of the behavior of the vehicle component (3) at second operating points (12) of the vehicle component (3) using the test system (2), wherein the test system (1) is configuredto determine the first operating points (11) and the second operating points (12) depending on at least one area of ​​use of the vehicle component (3) and to process a result of the simulation (101) with a result of the test (102) to form a joint test result (103) with the aid of the external computer (4).

The invention discloses an intelligent centralized control computer monitoring system based on cloud computing, and relates to the technical field of power plants, and the intelligent centralized control computer monitoring system based on cloud computing comprises a data acquisition unit. A monitoring sensor sends data of monitored power plant equipment to the system, data cleaning and data arrangement are carried out on the obtained data of the monitored power plant equipment, abnormal data are input into an equipment abnormity identification model building module, abnormal equipment and an abnormity monitoring sensor are identified, and the abnormal equipment is identified. Therefore, monitoring personnel can monitor the hydraulic power plant by checking pictures of the analog computer monitoring system, so that the monitoring personnel can know abnormal nodes in time and inform maintenance personnel of the abnormal nodes to handle the abnormal nodes in time, data abnormity caused by faults of the monitoring sensor can be avoided, and the maintenance efficiency of the hydraulic power plant is improved. And the situation that the equipment needs to be checked one by one is avoided, so that abnormal nodes can be maintained in time.

A method includes generating, via a virtual machine, a group of code traces, each code trace of the group of code traces corresponding to a respective algorithm, of a group of algorithms, and a corresponding input. The method also includes fine-tuning a generative model in accordance with the group of code traces. The method further includes receiving, at the fine-tuned generative model, computer programming code. The method also includes generating, via the fine-tuned generative mode, one or more computer programming code statements corresponding to the computer programming code or simulate an expected output of the computer programming code.

A method to debug instruction execution errors in a simulated computer system is provided. The method includes generating two separate simulations of the same system and causing a code including a set of instructions to execute on the two separate simulations. The computer implemented method further includes performing an efficient trace operation starting from a start instruction to an end instruction of the set of instructions on the two separate simulations. When trace operation is performed, an instruction execution deviation is identified between the code executed in the two separate simulations by comparing checksum values at a reporting frequency, determining that the comparison of the checksum values indicates a mismatch, and using instruction count and the reporting frequency to capture at least one instruction leading up to the instruction execution deviation.

Method for simulating a computer system (100) for the design, verification and / or manufacture of the computer system (100), wherein the computer system (100) comprises a first component (102) and a communication link (104), wherein the first component (102) is configured to execute a first function for determining an output variable of the first component (102), wherein the first component (102) is configured to output the output variable to the communication link (104), wherein in the simulation the runtime of the execution of the first function is estimated and the output variable or information about the output variable is output to the communication link (104) at the end of the estimated runtime, wherein the output variable is specified or estimated, or the information is specified or estimated or determined depending on the output variable.

A switchless computer mouse comprising: a keyplate operable to be depressed over a range of motion; a conductive element coupled to the keyplate; a sensor configured separate from the conductive element; a haptic element; and one or more processors operable to: control the sensor to detect a position of the conductive element over the keyplate range of motion; and control the haptic element to generate a haptic feedback when the sensor detects that the position of the conductive element corresponds to a preset threshold position within the range of motion.

A polytopic reduced-order model (ROM) generator is provided for a polytopic reduced-order model (ROM) used by an optimization controller in a heating, ventilation and air conditioning system. The physica model generator includes an interface circuit to receive a training dataset via a network connected to a simulation computer, a memory to store the polytopic ROM for predicting dynamics of airflow in the room, the training dataset, and instructions for calculating the parameters of the polytopic ROM, a processor to calculate the parameters of the polytopic ROM. The calculations include computing a global projection operation from high-dimensional state to reduced state, computing a global lifting operation from reduced state to high-dimensional state, constructing local reduced models of reduced state dynamics for each physical parameter value in the training dataset, and generating the polytopic ROM by combining a weighted average of the local reduced models with projection and lifting between reduced state and full state.

The invention relates to a system having a sensor simulation computer for calculating model data, an ESI unit for generating sensor raw data, and a switching device, the sensor simulation computer having a first connector (5) and a second connector (6), two lines (7) being connected to the first connector and four lines (7) being connected to the second connector, the ESI unit has a receiver (8) to which four lines (7) are connected, a switching device is connected between the first connector and the receiver and between the second connector and the receiver, and the switching device is designed and controllable in such a way that two lines (7) connected to the first connector and two lines (7) connected to the second connector can be connected to the four lines (7) connected to the receiver, or the four lines (7) connected to the second connector can be connected to the four lines (7) connected to the receiver. In this way, a system is provided that can accommodate various requirements in a simple manner.

The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h / J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.

A system comprising a sensor simulation computer for calculating model data, an ESI unit for generating raw sensor data and a switching device. The sensor simulation computer has a first DisplayPort connector and a second DisplayPort connector. Two DisplayPort lines are connected to the first DisplayPort connector and four DisplayPort lines are connected to the second DisplayPort connector. The ESI unit has a DisplayPort receiver to which four DisplayPort lines are connected. The switching device is interposed between the first and second DisplayPort connectors and the DisplayPort receiver. The switching device can be configured such that either the two DisplayPort lines connected to the first DisplayPort connector and two DisplayPort lines connected to the second DisplayPort connector are connectable to the four DisplayPort lines connected to the DisplayPort receiver, or the four DisplayPort lines connected to the second DisplayPort connector are connectable to the four DisplayPort lines connected to the DisplayPort receiver.