264 results about "Data port" patented technology

The main object of the invention is an antenna module for an acoustic point defence system (SAD) and an acoustic system comprising said module. The antenna module comprises at least one array of electroacoustic transmitting transducers (TX) and at least one array of electroacoustic receiving transducers (RX). The arrays of transmitting transducers and the arrays receiving transducers have the characteristic of being housed in a watertight container adapted to be submerged in water when the module is in operation, for example by means of a hoist or winch device (SMMR - Launching and Recovery System). The container has watertight accesses, for example via watertight connectors, for at least one cable for a power supply signal, connected or connectable with a power supply unit external to the container, and for at least one cable for a data signal, connected or connectable to a remote control unit adapted to send commands and receive target detection states and / or signals. The antenna module comprises a local control and calculation unit housed inside the container, which local control and calculation unit is equipped with an input for the power supply signal and a port for the data signal, and is interfaced with the arrays of transducers for controlling the signal transmitted by the arrays of transmitting transducers and processing the signals received by the arrays of receiving transducers on the basis of commands received by the data port.

Disclosed is an LED driver circuit, a multi-wire communication device and a method for an LED display system. The device comprises a controller providing at least one of a configuration data packet, a brightness data packet, and a display data packet; the LED driver circuits, wherein the LED driver circuits are cascaded to provide a first data channel using first data ports and second data ports, the LED driver circuits are connected in parallel to provide a second data channel using third data ports. The device relays an enable signal or an address data packet stage by stage using the first data channel, transmit at least one of the configuration data packet, the brightness data packet and the display data packet in parallel using the second data channel. The number of the cascaded LED driver circuits can be infinite, the number of data wires is reduced, data rate is increased.

A display device includes an input port, an output port, a data port, a detection circuit, a processor, and a connection tips circuit. The detection circuit generates a first state value according to a connection state of the input port, and generates a second state value according to a connection state of the output port. The processor generates a third state value according to a connection state of the data port. The processor determines a connection between the display device and an audiovisual source and provides a connection tips signal according to the first state value, the second state value, and the third state value. The connection tips circuit controls the display device to display a connection tips image in response to the connection tips signal.

A data storage device comprising a data port, configured to transceive data via a wired communication channel, a control port, configured to transceive data via a peer-to-peer wireless communication channel, a non-volatile storage medium, and a controller. In response to receiving, from a user device, via the control port, a command to enable control channel access, the controller performs an unlocking process, and, in response to completing the unlocking process, transitions from a locked state to a control channel access state. In response to being in the control channel access state, and in response to receiving, from the user device, via the control port, a write command, the controller stores write data in the storage medium, and, in response to receiving, from a host computer, via the data port, a command to access the storage medium, the controller transmits, to the host computer, a locked state indication.

The invention discloses a bridge and a bridge circuit thereof, the bridge circuit comprises an SPI interface, a bridge conversion chip, an isolation circuit, an enable circuit and a UART interface, the SPI interface is coupled and electrically connected with the bridge conversion chip, and the SPI interface is also electrically connected with an SPI interface of a host of a battery management system. A data port of the bridging conversion chip is coupled and electrically connected with the UART interface through an isolation circuit, the bridging conversion chip is further electrically connected with a data sending port of the UART interface through a corresponding enable circuit, the UART interface is further electrically connected with a UART interface of the AFE, and the host is used for configuring configuration parameters for the UART interface to communicate with the preset AFE; the SPI interface is used for transmitting an SPI signal between the host and the bridging conversion chip; the bridging conversion chip is used for converting UART signals and SPI signals; the isolation circuit is used for carrying out noise interference isolation on the UART signal converted by the bridging conversion chip; the enabling circuit is used for enabling a data sending port of the UART interface; and the UART is used for transmitting a UART signal between the AFE and the bridging conversion chip.

A memory device has a relatively wide, multi-pad data port for sending and receiving bursts of read and write data, respectively, to and from a requesting host. The host can fractionalize the multi-pad data port into narrower bidirectional ports to simultaneously communicate read and write data. The memory device increases burst lengths in proportion to reductions in port width to maintain access granularity. The width fractions of the narrower data ports can be controlled by the host responsive to e.g. a ratio of read to write transactions.

The invention relates to the technical field of high-speed interfaces, and discloses a channel binding method, device, equipment, medium and program product.The method is applied to the receiving direction of an FPGA chip and comprises the steps that a data transmission protocol is obtained, and the number of channels is determined according to the data transmission protocol; determining a primary channel and a secondary channel based on the number of channels; when the main channel receives target data and confirms a target frame header of the target data, the main channel is controlled to send out an alignment signal; the alignment signal is transmitted to the secondary channel through the whole internet; when the secondary channel receives the alignment signal, a first-in first-out queue read pointer corresponding to the secondary channel is adjusted, so that the secondary channel is aligned with the primary channel; and after the first-in first-out queue read pointers corresponding to the secondary channels are adjusted, reading data from the first-in first-out queues corresponding to the secondary channels, and outputting the data from a data port in the receiving direction of the physical coding sub-layer. The method can meet the requirements of different protocols for the number of bound channels, and greatly improves the flexibility of channel binding.

A security apparatus includes a body having an opening at a forward edge of the body, a lock cylinder located within the body, and an engagement mechanism including a first finger and a second finger extending out of the body through an opening. The lock cylinder is configured to move the first and second fingers between a first position in which the engagement mechanism is removable from the data port and a second position in which the engagement mechanism is secured to the data port. Each of the first and second fingers includes a surface configured to engage the sidewall of the portable electronic device. An alignment member is configured to extend into the opening and remain within the opening when the engagement mechanism is in the second position, wherein the alignment member includes a surface configured to engage the forward edge of the body.

Techniques for enabling precision monitoring of one or more data-throughput counters at one or more network interfaces are disclosed. A command-batch based polling technique enables a system to monitor with precision, e.g., at a high-speed, data-packet traffic through one or more data ports at a network interface. The command-batch based polling technique may enable polling of data-throughput counters for the data ports at the network interface every 1 ms, 10 ms, or 100 ms to monitor the high-speed flow of data-packet traffic through the data ports without loss of count data from overwriting.

The invention relates to the technical field of cold-chain logistics and information processing, and provides a cold-chain logistics information distribution and tracing system for data management, which comprises a server, a distributed verification module, a node sampling prediction module, a logistics data push module and an environment monitoring module, the distributed verification module is used for collecting data port states of a plurality of logistics nodes and performing consistency verification on node data so as to form an inter-node trusted data set; the node sampling prediction module is used for carrying out periodic sampling on a freight vehicle, storage equipment and a temperature control device, calculating a freight priority index Freight Priority Index and generating prediction data; the logistics data pushing module is used for dynamically pushing node data according to a freight transport priority index and a system load index (Network Load), and generating a delivery feedback index (Delivery Feedback) on the basis of feedback information; the environment monitoring module is used for monitoring cold chain transportation and storage environment parameters in real time, and recording and tracing temperature control states and safety alarm information of all nodes.

The present application relates to the field of supply chain management, and discloses a logistics information management device and system based on the Internet of Things. The device comprises a support frame; a conveyor belt is fixedly connected to the upper surface of the support frame; a detection compartment is fixedly connected to the upper surface of the support frame; the conveyor belt is arranged inside the detection compartment; a scanner is fixedly connected to the lower surface of the detection compartment; the scanner is arranged above the conveyor belt; a console is fixedly connected to an outer wall of the detection compartment; and a data port is fixedly connected to the lower surface of the console. The system comprises an Internet interface module. Because the device can support multiple Internet of Things communication protocols, the device can integrate data from multiple sources; by receiving data from various sensors in real time, a data processing module can process the data in real time, thereby better planning and optimizing logistics paths and processes; and big data technology can be used for processing large amounts of data collected from sensors and devices.

Systems and methods related to communication interface are provided. An interface circuitry arrangement for communication between integrated circuit (IC) devices, the interface circuitry arrangement including serial peripheral interface (SPI) circuitry having an SPI clock port, an SPI data port, and an SPI chip select (CS) port; inter-integrated circuit (I2C) circuitry having an I2C clock port and an I2C data port, wherein the I2C clock port and the SPI clock port are electrically coupled to a first connection port, and wherein the I2C data port and the SPI data port are electrically coupled to a second connection port; pattern detection circuitry to detect a signal pattern at a third connection port, the third connection port electrically coupled to the SPI CS port; and selection circuitry to selectively couple the SPI circuitry or the I2C circuitry to a data path responsive to an output of the pattern detection circuitry.

A direct memory access (DMA) system includes a plurality of read circuits and a switch coupled to a plurality of data port controllers configured to communicate with one or more data processing systems. The DMA system includes a read scheduler circuit coupled to the plurality of read circuits and the switch. The read scheduler circuit is configured to receive read requests from the plurality of read circuits, request allocation of entries of a data memory for the read requests, and submit the read requests to the one more data processing systems via the switch. The DMA system includes a read reassembly circuit coupled to the plurality of read circuits, the switch, and the read scheduler circuit. The read reassembly circuit is configured to reorder read completion data received from the switch for the read requests and provide read completion data, as reordered, to the plurality of read circuits.

The utility model provides a layout structure of a bidirectional buffer. The layout structure comprises a bonding pad layout area and a first / second port layout area, the bonding pad layout area comprises a first bonding pad used for signal input, a second bonding pad used for signal input and output, a third bonding pad used for being connected with a power supply and a fourth bonding pad used for being grounded; the first port layout area and the second port layout area respectively comprise a control port area and at least one data port area; the first control port area and the second control port area are respectively connected with the first bonding pads, and the at least one first data port area and the at least one second data port area are sequentially arranged along the first direction and are connected with the second bonding pads in a one-to-one correspondence manner; one of the first and second control port areas is configured to control the transmission direction of a data signal, the other one is configured to control the output state of the circuit, and the first and second data port areas comprise a bidirectional data logic module configured to receive and send out the data signal. The layout structure can realize miniaturization of the chip.

A security device includes: a body having an opening at a front edge of the body; the lock cylinder is positioned in the main body; and an engagement mechanism including a first finger and a second finger extending out of the body through the opening. The lock cylinder is configured to move the first finger and the second finger between a first position in which the engagement mechanism is removable from the data port and a second position in which the engagement mechanism is removable from the data port. In the second position, the engagement mechanism is secured to the data port. Each of the first and second fingers includes a surface configured to engage a sidewall of the portable electronic device. The alignment member is configured to extend into the opening and remain within the opening when the engagement mechanism is in the second position, where the alignment member includes a surface configured to engage the front edge of the body.

The utility model relates to a communication circuit and a scooter. According to the communication circuit, a first withstand voltage boosting module comprises a withstand voltage controllable switching device and is used for being switched on or switched off under the control of a bias signal; data transmission between the first data port and the second data port is opened or closed, and the withstand voltage values of the first data port and the second data port are increased to a first voltage threshold value; the second withstand voltage boosting module comprises a withstand voltage unidirectional switching device and is used for sending a clock signal from the master device to the slave device and increasing the withstand voltage values of the first clock port and the second clock port to a second voltage threshold; the first response speed increasing module comprises a first impedance network and is used for increasing the level change rate of the first data port and the first clock port; and the second response speed increasing module comprises a second impedance network and is used for increasing the level change rate of the second data port and the second clock port. According to the I2C communication port provided by the embodiment of the invention, 100V voltage resistance can be realized, and the response speed is at a microsecond level.

Embodiments of the present disclosure provide a storage chip and a storage system. The storage chip is configured such that characterization parameters representing the process corner of the storage chip are stored therein, and a reference voltage with an adjustable magnitude is further provided therein. The magnitude of the reference voltage is adjustable based on the characterization parameters, and the storage chip adjusts the delay of data read from a storage unit to output from a data port based on the reference voltage. Embodiments of the present disclosure are beneficial to improving the neatness of data signal transmission and preventing data conflicts.

A bidirectional address allocation method and system are used for allocating independent addresses to N units awaiting address allocation of at least one module awaiting address allocation. A first serial data port of a controller, two serial data ports of each of the N units awaiting address allocation, and a second serial data port of the controller are sequentially connected in series. In the module awaiting address allocation, a direction starting from a unit awaiting address allocation connected to the first serial data port of the controller is a forward direction, and a direction from a unit awaiting address allocation connected to the second serial data port of the controller is a reverse direction. The method includes: performing forward address allocation; determining whether address allocation for the N units awaiting address allocation is completed; changing an input / output direction; and performing reverse address allocation.

The application provides a communication circuit and a clothes processing apparatus, and belongs to the technical field of home appliance control. The communication circuit comprises a switch module. The switch module is connected with a display module. The switch module is also connected with a main control module. The switch module is disconnected when the data port of the display module is in a signal idle state, so as to control the circuit between the display module and the main control module to be disconnected. The switch module is closed when the data port of the display module is in a signal transmission state, so as to control the circuit between the display module and the main control module to be conducted. The switch module is disconnected when the signal is idle, so that the circuit between the display module and the main control module is disconnected, no static power consumption loss is generated, the static power consumption in the signal idle state is avoided, and the overall power consumption is reduced. The switch module is closed when the signal is transmitted, so that the circuit between the display module and the main control module is conducted, and the communication function between the display module and the main control module is realized.

This invention discloses a data transmission device, an electronic device, and a method for switching data transmission paths. The data transmission device includes multiple data ports, a System-on-a-Chip (SOC) module, and a switching switch. The SOC module includes a control unit, which has at least a USB pin, a GPIO pin, a USB_ID pin, and a VBUS pin. The switching switch is connected to the USB pin and the GPIO pin respectively, and can selectively connect to the multiple data ports. The control unit is used to acquire the level signals of the USB_ID pin and the VBUS pin, and control the connection state of the switching switch with the multiple data ports based on the level signals. According to the data transmission device of this invention, by setting a switching switch, the development cost of the USB pin can be reduced, and the difficulty of production and maintenance can be lowered.

The present disclosure provides an information transmission method, a memory, a control device and an electronic device, the method comprising: receiving a first target instruction sent externally; outputting first duty cycle data of an internal data clock signal through a first group of data ports based on the first target instruction, and the first duty cycle data lasting in the first group of data ports at least until a first end instruction sent externally is received.

A communications system may include a host device and an external display. A wired path may couple a first data port on the host device to a second data port on the external display. The host device may drive the external display to display images via the wired path. A first radio on the host device may generate first wireless performance metric data and a second radio on the external display may generate second wireless performance metric data. The external display may transmit the second wireless performance metric data to the host device over the wired path. The host device may switch between conveying wireless data using the first radio or the second radio based on the first and second wireless performance metric data.

The invention discloses a method and a device for improving data transmission efficiency by a GPU (Graphics Processing Unit) through bandwidth sharing, and the method comprises the following steps of: grouping L2 cache sub-partitions in a manner that four sub-partitions form a group, sharing a data port by the four sub-partitions in the group, and jointly executing a data return task of a single sub-partition; the L2 cache judges whether the current sub-partition is served or not, and the scheduler in the group checks the next sub-partition through polling scheduling and judges whether the current sub-partition has a request or not. If the current sub-partition has a request and the head-of-queue request is read hit, determining to serve the sub-partition; when the current sub-partition is not served and the queue head request is a write request or read missing, the sub-partition and the served sub-partition are subjected to parallel processing; the L2 cache divides the data into four parts and sends the four parts to the multiplexer module, and the multiplexer module of each sub-partition selects corresponding signal input and transmits the data to a data port; the aggregated data port sends the data back to the L1 cache through the NoC; and counting and confirming that the complete cache line data is received by a counter in the SM. The device comprises a processor and a memory.

Transceiver integrated circuit suitable for distributed placement across an active antenna unit. ICs with two serial data ports configured to transmit and receive aggregated signal-port IQ data packets with adjacent ICs within a subarray of ICs, or to a beamformer processor. A packet header inspection circuit may identify aggregated signal-port IQ data packets for local processing, and identify received aggregated signal-port IQ data packets for processing by another device.

The utility model provides a combination line which comprises a total port which is connected with a communication port through at least two groups of twisted pairs serving as communication lines and is connected with a data port through at least one group of twisted pairs serving as data lines. Comprising an anti-abrasion adhesive tape, and the anti-abrasion adhesive tape wraps the communication line and / or the data line and / or the communication line and the data line. Wiring is simplified, the number of needed cables is reduced, cost is reduced, efficiency is improved, and space layout is optimized.

This invention discloses an IGBT overcurrent protection circuit with fault latching function, including an IGBT module, an IGBT driver module, a central control module, an overcurrent detection module, and an overcurrent latch module. The signal output terminal of the IGBT module is connected to the signal input terminal of the overcurrent detection module, the enable output terminal of the overcurrent detection module is connected to the enable input terminal of the IGBT driver module, the signal output terminal of the overcurrent detection module is connected to the signal input terminal of the overcurrent latch module, the signal output terminal of the overcurrent latch module is connected to the first data port of the central control module, the second data port of the central control module is connected to the signal input terminal of the IGBT driver module, and the signal output terminal of the IGBT driver module is connected to the signal input terminal of the IGBT module. This invention directly controls the IGBT driver module to turn off the IGBT module by the overcurrent detection module, and the overcurrent latch module connected to the overcurrent detection module sends a fault signal to the central control module, promptly notifying the central control module to disable the IGBT driver module and keep the IGBT module continuously on.

The utility model provides wire harness detection equipment, and belongs to the technical field of wire harness detection. The detection equipment comprises a detection box body, an upper cover plate, a bearing device and a circuit board, a first through hole is formed in the side face of the detection box body, one edge of the upper cover plate is connected to the top of the detection box body through a hinge, a plurality of second through holes are formed in the upper cover plate, a pair of insertion ports are formed in the upper cover plate, and the bearing device is arranged on the lower surface of the upper cover plate. The bearing device comprises buffering pieces, a first bearing plate and a second bearing plate, the buffering pieces are arranged on the lower surface of the upper cover plate, the first bearing plate is horizontally arranged on the four buffering pieces, a first groove is formed in the first bearing plate, the second bearing plate is detachably arranged on the first bearing plate, a second groove is formed in the second bearing plate, and the buffering pieces are arranged on the lower surface of the upper cover plate. The second groove and the first groove define a bearing space, the circuit board is arranged in the bearing space, the data port in the circuit board is exposed through the second through hole, the circuit board is connected with the plug-in interface, and the circuit board can be replaced by disassembling the bearing device.

The invention provides eye adjusting equipment integrating eyelid opening, fundus photography and a data port, and belongs to the technical field of intelligent medical wearable equipment. The equipment comprises a glasses frame main body, a non-invasive eyelid opening mechanism, a high-resolution fundus photographing module, diopter-adjustable lenses, a data processing unit and a wired and wireless data port. The eyelid opening mechanism adopts a medical silica gel flexible opening sheet and a push rod, so that safe and automatic eyelid separation is realized; the fundus photographing module supports clear imaging at a field angle of 30-50 degrees based on infrared illumination and a CMOS sensor, and has pupil tracking and automatic focusing functions; the built-in electric control zoom lens can dynamically adjust the diopter from 6.0 D to + 4.0 D. The problems that existing fundus examination equipment is large in size, complex to operate, serious in eyelid shielding, unable to use and the like are solved, and the fundus examination equipment has remarkable clinical application value and industrialization prospects.

This application discloses a privacy-aware and data de-identification system and method for unmanned aerial vehicles (UAVs). The system includes an airborne edge computing unit, multi-source sensors, a dual-channel data processor, a security encryption and transmission module, and a policy management interface. It is implemented through three parallel pipelines: a real-time privacy-aware pipeline uses a lightweight neural network to detect sensitive targets such as faces and license plates and outputs bounding boxes; a dynamic and precise de-identification pipeline calls a policy library to perform context-aware de-identification on the target area; and a dual-stream split-path controllable transmission pipeline transmits the de-identified data stream to the business platform in real time via a public network, while simultaneously transmitting the encrypted original data stream to a trusted data port through an independent secure channel.

The present invention relates to the field of high-speed interface technology, and discloses a channel binding method, apparatus, device, medium, and program product. The method is applied to the receiving direction of an FPGA chip, and includes the following steps: obtaining a data transmission protocol and confirming the number of channels according to the data transmission protocol; confirming a primary channel and a secondary channel based on the number of channels; when the primary channel receives target data and confirms the target frame header of the target data, controlling the primary channel to send an alignment signal; and transmitting the alignment signal to the secondary channel via the entire Internet; when the secondary channel receives the alignment signal, adjusting the first-in-first-out queue read pointer corresponding to the secondary channel so that the secondary channel is aligned with the primary channel; after the first-in-first-out queue read pointers corresponding to each secondary channel are adjusted, reading data from the first-in-first-out queue corresponding to the secondary channel and outputting it from the data port in the receiving direction of the physical coding sublayer. The method can adapt to the number of bound channels required by different protocols, greatly increasing the flexibility of channel binding.