89 results about "Digital processor" patented technology

The invention discloses a short-circuit current limiting and short-circuit recovery transient voltage control device and method for an aviation three-stage power generation system, and the device comprises a three-stage power generator, a power generator controller, a current sensor, a voltage and current collection module, and an asymmetric half-bridge excitation control circuit. Collecting the output current iL and voltage UL of the generator through a digital processor of the generator controller; when short circuit occurs, the given voltage USet of the voltage regulating loop is linearly reduced in a piecewise mode according to the relation between the iL and a preset threshold value, so that the generator works in a constant power interval; and when the short circuit is recovered, closing the upper / lower power tubes of the asymmetric half-bridge excitation control circuit according to the relationship between UL and a preset threshold value in a grading manner, and triggering a negative-pressure follow-current mode of a main excitation winding of the generator controller to quickly extinguish the field. The method can adapt to different generators without adjusting hardware circuit parameters, has no motor ablation risk during short circuit, has transient voltage less than 350V after short circuit recovery, has no power supply interruption in the whole process, has response delay less than 1ms, and greatly improves the safety and robustness of an aviation power supply and distribution system.

There is provided a system and methods to determine an improved solution to a Mixed Integer Problem (MIP) using a quantum-assisted MIP solver. The methods are performed by a digital processor in communication with a quantum processor. Methods include: selecting at least one feasible solution determined by an MIP solver, determining a first sub-problem of the MIP based on the at least one feasible solution; casting the first sub-problem as Binary Quadratic Models (BQMs); solving the BQMs using the quantum processor to generate sample solutions; determining a second sub-problem based on at least the sample solutions, and obtaining a current solution to the MIP by evaluating the second sub-problem; and updating an incumbent solution if the current solution improves over the current incumbent solution. The quantum-assisted MIP solver uses hybrid crossover and mutation heuristics to improve the convergence time and accuracy of solutions obtained using Branch-and-Cut solvers.

An analog electronic component for control of an aerosol delivery device is provided. The aerosol delivery device includes a heating element, a reservoir that retains aerosol precursor composition, and an analog electronic component that in response to user input, and independent of a digital processor, is configured to direct a constant current to the heating element and thereby cause the heating element to activate and vaporize components of the aerosol precursor composition in response to user input, and a user input interface through which the user input is receivable.

The invention relates to the technical field of microwave remote sensing, in particular to a Ku, Ka and W three-frequency-band meteorological radar multi-source joint detection system and method and a storage medium, and the system comprises an antenna feeder subsystem, a main control computer, an integrated digital processor, a Ku / Ka integrated radio frequency machine, a Ku-frequency-band power amplifier, a Ka-frequency-band power amplifier, a W-frequency-band transmitter, a W-frequency-band power amplifier, a W-frequency-band receiver and a servo mechanism. The system is designed according to a working mode and working parameters of a main control computer, realizes multiple functions such as Ku / Ka / W single-frequency-band independent working or multi-frequency-band simultaneous working and the like, and has co-polarization and cross-polarization echo signal receiving capability; by controlling the servo mechanism, two modes of fixed-point detection and conical scanning detection are realized, and detection requirements of different meteorological elements are met; the detection capabilities of three frequency bands of Ku, Ka and W are integrated in the system, the detection mode is flexibly configured according to weather conditions and detection requirements, the system has the multi-frequency-band, multi-polarization and multi-element integrated detection capability, and the detection efficiency of the meteorological radar is improved.

The invention discloses a smart home multi-device linkage power utilization control method based on MOS tubes, and belongs to the technical field of smart home control. The digital processor is used as a core, the built-in numerical control module and the data processing unit are matched, the on-off state of the MOS tube is accurately regulated and controlled in combination with a program control algorithm, fine management of power utilization parameters of intelligent household equipment is achieved, the limitation that traditional control response is lagged and poor in adaptability is broken through, rated parameters and real-time requirements of the equipment are dynamically matched, and the power utilization efficiency is improved. The optimal operation of equipment is guaranteed to prolong the service life, invalid energy consumption is reduced, a high-precision foundation is laid for multi-equipment cooperative linkage, the stability and energy efficiency of a system are improved, multi-scene linkage logic is preset by means of a logic state machine, and rapid switching and reliable execution of multi-scene linkage are realized by matching with an application selection switch of an MOS tube array structure. Scene requirements are automatically adapted, and through independent loop control, fault detection and standby loop design, the problems that linkage switching is tedious and the fault influence is large are solved.

Embodiments of the present invention provide a method, system, devices and software which provide customized, clinically relevant designs, e.g. treatment plans / solutions for at least single tooth replacement therapy in real-time as needed to enable immediate confirmation of the validity and execution of patient-specific treatment solutions.A Machine Learning algorithm is used in a method or system for computer implementation of automatic restoration design. The restoration design includes the design of restorative elements such as crowns and abutments. Software is provided for carrying out the methods when executed on a digital processor. Manufacturing of the restorative elements is also included.

The present patent document provides a design of an efficient hybrid quantum classical computing system capable of information processing based on both quantum computing using different quantum states of qubits and classical digital computing using a digital processor including one or more graphics processing unit (GPU) processors.

The application relates to a kind of OFDM-based broadband millimeter wave relay system hybrid beamforming design method, comprising: calculating the receiving signal of target node under the condition that each node is all digital processor;The receiving signal is processed using minimum mean square error criterion in target node, and MMSE matrix is calculated;Using the equivalence between maximizing sum rate and minimum weighted mean square error algorithm, the maximum sum rate problem is converted into minimum weighted mean square error problem according to MMSE matrix;Deep unfolding neural network is used to solve the minimum weighted mean square error problem, and all digital processor of each node is obtained;Each node's all digital processor is decomposed based on least square decomposition algorithm, and hybrid beamforming matrix of each node is calculated, the complexity of the algorithm is greatly reduced, and the running time of the system can be effectively improved.

The thermodynamic computing platform samples multivariate distributions (e.g., multivariate Gaussian distributions) using a network of coupled analog unit cells controlled by a digital processor. The analog unit cells are capacitively, resistively, and / or inductively coupled to each other. Each analog unit cell contains an adjustable resistor, capacitor, inductor, current source, and / or voltage source. The digital processor sets initial values ​​for these components. These values, or input parameters, represent the multivariate distribution. The network of coupled analog unit cells is then evolved through a series of time steps until thermal equilibrium is reached. As the network evolves, the digital processor samples voltages at nodes in the network at each time step. These voltages represent samples of the multivariate distribution.

A high-voltage (HV) power supply device outputs an output voltage based on a control signal generated by dual analog / digital feedback loops. The control signal is determined at least in part by an error amplifier that receives a measurement signal attenuated proportionally to the output voltage and an output signal from a digital-to-analog converter (DAC). The ADC also receives the measurement signal and transmits it in digitized form to a digital processor. The digital processor calculates a digital DAC data signal based on the measurement signal and a digital setpoint input signal corresponding to a setpoint voltage value desired to be output from the high-voltage source. The DAC receives the DAC data signal and converts it into a DAC output signal that is transmitted to the error amplifier.

The invention relates to a system for program control using a digital processor, and more particularly to a system for automatically generating reports about the state of thermal vacuum and manufacturing systems. The technical result, which consists in more timely generation of reports about the state of thermal vacuum and manufacturing systems, is achieved in that the present system for automatically generating reports about the state of thermal vacuum and manufacturing systems comprises a host computer interconnected with a control unit that transmits control signals to monitoring and measuring devices and a data processing unit, wherein the monitoring and measuring devices transmit data to a data collection unit, which transmits data to the data processing unit, which transmits data to the control unit, which transmits data to the host computer, and the monitoring and measuring devices include a validation device, a device for measuring the amount of aerosol particles in the air, a device for remotely recording temperature and relative humidity values, a device for monitoring the parameters of controlled environment rooms, and a module for generating a report about a set of production equipment, wherein the data collection unit is connected to a database, which is connected to the data processing unit.

The invention discloses an ultra-wideband transient multi-electromagnetic physical quantity synchronous measurement method and system, and the method comprises the steps: designing an electric field sensor based on a monopole rod-shaped electrically small antenna principle, and designing a magnetic field sensor based on a Faraday's law of electromagnetic induction; designing a voltage sensor based on a self-integration mode, and designing a current sensor based on a broadband Rogowski coil; based on a digital sampling technology of an FPGA, a digital processor is designed, sampling data collected by an electric field sensor, a magnetic field sensor, a voltage sensor and a current sensor are collected through the digital processor, the sampling data are transmitted to an upper computer through a QSFP module, and the sampling data are processed and displayed through the upper computer. The scheme can be effectively applied to application scenes of transient electromagnetic environment online monitoring, fault diagnosis, radiation source accurate positioning and the like of high-voltage power equipment.

Embodiments of the present disclosure include techniques for moving data between system components using buffers. A digital processor stores data generated in response to a series of commands in a first buffer. A command is received and has a reference to the second buffer. The data processor tracks a last location where the data result is stored in the first buffer. When the buffer area is filled with the data result, the remaining data is automatically stored in the second buffer area. Downstream equipment may empty the full buffer. The client may receive an indication that the buffer is empty, and then send a command with a reference to the empty buffer.

Embodiments of the present disclosure include techniques for moving data between electronic system components using buffers. A digital processor stores data generated in response to a series of commands in a first buffer. Commands are received with a reference to a second buffer. The digital processor tracks the last location that a data result was stored in the first buffer. When a data result fills the buffer, the remaining data is automatically stored in the second buffer. Downstream devices may empty full buffers. A client may receive an indication that a buffer is empty and subsequently send commands with a reference to empty buffer.

This method is implemented within a digital processor by: a) searching an internal register (R1, R2, R3, . . . R(n)) of the processor which content (b0, b1, b2, . . . b(n)) changes over time; b) extracting at a given time n bits from the register, n≥1; c) using the n bits extracted at step b) as bit(s) for forming a random number of N bits to be generated; d) reiterating (250) steps a) to c) until obtaining the N bits of the random number; and e) providing the random number to an application circuit or software. In order to increase randomness, the method further comprises a selection (240), by a random of pseudo-random process, of the n bits of the register which will be extracted, and / or a selection (230), by a random of pseudo-random process, of one register among a plurality of internal registers (R1, R2, R3, . . . R(n)) of the processor that may be potentially searched and selection of the n bits from the selected register, in particular a selection, by a random of pseudo-random process, of at least one of the bits of the selected register.

The embodiment disclose a wearable augmented reality eyewear system including a frame supporting left and right transparent lenses. A plurality of outward-facing cameras mounted on the frame have overlapping fields of view for capturing real-time images of the environment. A plurality of inward-facing cameras integrated in the frame or lenses detect pupil size, pupil dilation, and gaze direction using infrared imaging. A digital processor analyzes gaze direction and fixation based on virtual grid coordinates, initiates an object or person recognition routine using images from the outward-facing cameras, and compares detected features with records in a database. At least one lens includes an AR projection system embedded therein and configured to superimpose data about the recognized object or person in the user's field of view. An audio speaker positioned near the user's ear outputs related audio. A wireless communication module enables real-time data exchange with a cloud-based platform.

The invention discloses a nonlinear secondary channel modeling method with extremely low additional operand, and belongs to the field of active control of vibration noise. The method aims at solving the problems that in active control over strong response objects such as a vibration source, secondary channel nonlinearity causes insufficient modeling precision, and an existing method is large in additional calculation amount. The method comprises the following steps: firstly, determining a target frequency, selecting N kinds of sinusoidal signals with gradual increase amplitudes to identify a secondary channel in an off-line manner, and obtaining N groups of pulse response sequences; constructing an M-row N-column two-dimensional array storage sequence; during control, a round instruction is built in a digital processor to round the output to obtain an index number, and a corresponding secondary channel coefficient is called from an array so as to provide a precise model for a self-adaptive algorithm. The method is high in modeling precision and low in additional operand, guarantees the real-time performance and control stability of the system, and is suitable for a vibration noise active control scene of a filtering least mean square (FxLMS) algorithm.

Power amplifier circuitry is disclosed having an inverse Class-D amplifier functioning as a power amplifier and self-biasing circuitry generating gate bias voltages for switching type power transistors within the power amplifier. The self-biasing circuitry includes a low-dropout regulator that generates and applies a gate bias voltage in response to a feedback current scaled according to the power amplifier's operating current. A current-based digital-to-analog converter is configured to generate the reference current based on a received digital value. Additionally, a digital processor is configured to generate the digital value in response to the gate bias voltage. The power amplifier circuitry enhances performance and efficiency while ensuring precise control over power transistors'operation, offering advantages for various applications requiring radio frequency signal amplification.

The utility model discloses PCM equipment, which belongs to the technical field of telecommunication, comprises an input interface, a signal amplifier, a sampling hold circuit, a signal conditioning circuit, an ADC (analog to digital converter) module, a clock generator, a power module, a digital processor, a memory, an Ethernet controller and a remote communication module, and solves the technical problems of sampling synchronization and high-precision sampling of the PCM equipment. According to the utility model, the tracking sampling holding circuit formed by the AD8250 amplifier and the AD503 is adopted, so that the accuracy and the stability of signals during high-frequency sampling can be ensured. The perfect alignment of time sequences among the modules in the system is ensured, and the problem of long-distance low-power-consumption data transmission is solved.

The application relates to the technical field of digital processors, in particular to a reducer control system based on an opportunity constraint, which comprises a dynamic window module, a temperature cooling module, a lubricating pressure module, a gear meshing module and an optimization control module.In the application, reducer torque and rotating speed data are collected, the difference value of adjacent time points is calculated, the state transition probability is estimated in combination with a Markov chain model, a transition time window and an error range are set, the control parameters are dynamically adjusted, the reducer state change is fed back in real time, the real-time performance and adaptability of the control system are improved, the temperature data interval matching and trend judgment avoid over-temperature failure, the stability is ensured, the lubricating oil pressure and the cooling correction result are combined and compared, the lubrication is ensured to be appropriate, wear and failure are avoided, gear vibration and temperature data are analyzed through a probability density function, the gear meshing state is adjusted, and the system robustness and operation efficiency are improved.

The embodiments disclose an underwater video light system including a chip-on-board LED light configured to project multiple-colored LED light arrays in an underwater environment from a chip-on-board LED module, at least one colored LED light array from a group consisting of a blue light LED array, bluish green light LED array, and green light LED array, a wide-angle coupled to the chip-on-board LED light configured to project the chip-on-board LED light in a wide angle illumination in the underwater environment, at least one digital processor controller coupled to the chip-on-board LED light configured to regulate power transmission to the chip-on-board LED light module, a rechargeable battery pack, and an LED display coupled to the chip-on-board LED light configured to display operating settings and color selections.

A DSI3 slave device (120, 120') for a vehicle (100) is proposed, comprising: a digital processor (122, 122'); at least one analog circuit element (128, 128', C1, C1'); a DSI3 transceiver (124, 124') configured to receive a signal transmitted by a DSI3 master device (140), convert the received signal into a digital signal, and output the digital signal to the digital processor (122, 122'); and a reset pulse decoder (126, 126') configured to output a reset signal to the digital processor (122, 122') in response to a reset pulse in the received or the digital signal.

The invention discloses a multi-waveform adjustable electrotome current generation circuit and a control method. The multi-waveform adjustable electrotome current generation circuit comprises a digital processor, an optocoupler isolation module, a push-pull amplification module, an electrotome waveform generation module and a voltage-to-current source circuit, the digital processor is used for generating two paths of PWM control signals; the optical coupler isolation module is used for receiving and isolating the two paths of PWM control signals; the push-pull amplification module is used for amplifying the two paths of isolated PWM signals; the electrotome waveform generation module is used for carrying out filtering and direct current bias on the amplified PWM signal to generate an electrotome voltage waveform; and the voltage-to-current source circuit is used for converting the voltage waveform of the electrotome into a current signal with the same waveform and outputting the current signal to the electrotome. The device has the advantages of being simple in hardware structure, low in cost and capable of achieving output of various waveforms.

1. The name of the design product: energy storage cabin level digital centralized processor. 2. The use of the design product: digital processor unit for controlling energy storage system. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view.

The utility model relates to the field of boarding trestle, disclose a kind of boarding trestle control circuit, including DSP digital processor module, FPGA logic processor module, SDRAM data storage module, FLASH program storage module, LDO power supply voltage stabilizing module, analog-digital conversion module, switching value signal input-output module and communication module;The DSP digital processor module is equipped with EMIF interface and storage interface, is connected with FPGA logic processor module, SDRAM data storage module, FLASH program storage module respectively;The FPGA logic processor module is equipped with EMIF interface, SPI interface, RS communication interface, RS-232 communication interface and switching value interface.The utility model in the present application, the problem of traditional circuit structure dispersion is solved by integrated design, and the core function module such as DSP digital processor module, FPGA logic processor module is integrated to single circuit board, and the peripheral components and circuit connection are reduced from the root, not only the control box volume is reduced, and control cost is reduced.

The embodiments disclose an apparatus including a broadcasting network platform configured to provide free viewer services accessed by members, at least one server with at least one digital processor coupled to the broadcasting network platform, at least one database coupled to the at least one server, communication connectivity devices coupled to the at least one server, a network computer coupled to the at least one server, a free TV.net mobile app coupled to the network computer, a podcast recording device coupled to the at least one database configured to record a podcast program, a syndication (RSS) feed device coupled to the podcast recording device configured to convert the podcast into universally transferable electronic formats for multiple electronic formatted devices, at least one artificial intelligence device coupled to the at least one server, and at least one translation device coupled to the communication connectivity devices.

This application belongs to the field of radar digital processor testing technology, specifically relating to a radar digital processor testing system, including a computer and a differential VAG converter, wherein the differential VAG converter is connected to a digital radar processor; the computer integrates: an interface driver module; a video acquisition board with a Mini PCIe interface, connected to the interface driver module and the differential VAG converter; a fiber optic bus board, a 1553B bus board, an ARINC429 bus board, a multi-protocol serial bus board, and a discrete signal board with a Mini PCIe interface, all connected to the interface driver module and the digital radar processor; a video acquisition module connected to the interface driver module; an interface communication module, an interface data processing module, and an internal bus testing module connected to the interface channel module; and a comprehensive display and control simulation module connected to the interface data processing module and the video acquisition module.

The in-vehicle Ethernet physical layer (PHY) transceiver (32) includes an analog front end (FE-46) and a digital processor (44). The FE is configured to receive analog Ethernet signals via a physical Ethernet link (36) while the Ethernet PHY transceiver is operating in the vehicle (24), and is configured to convert the received analog Ethernet signals into digital signals. The digital processor is configured to: maintain one or more noise distributions (84) that characterize noise signals of corresponding predefined noise types that are expected to disrupt the received analog Ethernet signals; classify actual noise signals present in the digital signals into one of the noise types using the noise distributions; and apply noise mitigation operations selected in response to the given noise type in response to determining that the actual noise signal matches a given noise type among the predefined noise types.

The application discloses a true random number generator, which comprises a random number collecting unit and a random number generating unit. The random number collecting unit comprises a high-pressure-resistant closed transparent liquid pool, which contains a mixture of particles in Brownian motion; and a high-speed microscopic imaging device, which periodically takes pictures of a section inside the mixture to obtain multiple frames of pictures. The random number generating unit comprises a digital processor, which processes the multiple frames of pictures to obtain a preliminary random number string A0; and a postprocessor, which processes A0 to obtain a random number sequence.

The invention relates to the technical field of integrated circuit testability design, in particular to a testability design method based on a multi-frequency-division clock high-speed digital processor, which comprises the following steps of: acquiring a circuit to be tested, carrying out preprocessing and DFT (Discrete Fourier Transform) design on the circuit to be tested, and introducing an OCC module based on a three-way clock synchronization circuit, and carrying out testability design on the block-level circuit and the top-level circuit in sequence. The invention provides a testability design method combining SCAN CHAIN and LBIST, an EDT compression mechanism is adopted, a three-way clock synchronization circuit is used, high-coverage-rate fault testing is carried out on a chip based on a test vector generated by ATPG, under the condition that resources are limited, the test efficiency is improved, and the test efficiency is improved. According to the invention, the fault diagnosis and test of the multi-working-mode, multi-frequency-division clock and clock multi-phase high-speed digital signal processor under the asynchronous clock are carried out, the test cost is reduced, a reference is provided for the fault test of the high-speed digital signal processor, and the chip yield is improved.