A novel apparatus for and a method of
noise and spurious tones suppression in a digital RF processor (DRP). The invention is well suited for use in highly integrated
system on a
chip (SoC) radio solutions that incorporate a very large amount of digital
logic circuitry. The
noise suppression scheme eliminates the
noise caused by various on
chip interference sources transmitted through electromagnetic, power, ground and substrate paths. The
noise suppression scheme permits an all digital PLL (ADPLL) to operate in such a way to avoid generating the spurs that would normally be generated from the injection pulling effect of interfering sources on the
chip. The frequency reference
clock is retimed to be synchronous to the RF oscillator
clock and used to drive the entire digital
logic circuitry of the DRP. This ensures that the different
clock edges throughout the
system will not exhibit mutual drift. A method of improving the resolution quality of a
time to digital converter within the ADPLL is also taught. The method dithers the reference clock by passing it through a
delay circuit that is controlled by a sigma-
delta modulator. The dithered reference clock reduces the affect on the
phase noise at the output of the ADPLL due to ill-behaved quantization of the TDC timing
estimation.