1296 results about "Propagation delay" patented technology

System(s) and method(s) for compensation of propagation delay offsets of wireless signals. Compensation is accomplished through determination of an effective wireless signal propagation delay that accounts for signal path delay and propagation delay over the air. Such determination is based at least in part on statistical analysis of accurate location estimates of reference positions throughout a coverage sector or cell, and location estimates of the reference positions generated through time-of-flight (TOF) measurements of wireless signals. Determination of propagation or signal path delay offset also is attained iteratively based at least in part on reference location estimates and TOF location estimates. High-accuracy location estimates such as those obtained through global navigation satellite systems are employed as reference location estimates. Position of probes or wireless beacons, deployed throughout a sector or cell, also are employed as reference locations. Compensation of propagation delay offset improves accuracy of conventional TOF location estimates and radio network performance.

The invention relates to methods for reporting on downlink timings by a mobile terminal in a mobile communication system. In order to allow for an aggregation access point to obtain information on propagation delay differences of downlink transmissions on aggregated serving cells, the invention suggests the mobile terminal to report timing information based on reception time difference information for a the target/reference cell. The mobile terminal performs measurements relating to transmission and/or reception time differences on the target/reference cell, and reports same to the eNodeB. The eNodeB compares the measurement result to a predefined maximum propagation delay time difference. Alternatively, the mobile terminal performs the measurements, compares same to the predefined maximum propagation delay time difference and then report the comparison result to the eNodeB.

Embodiments of the invention enable the synchronization of clocks across packet switched networks, such as the Internet, sufficient to drive a jitter buffer and other quality-of-service related buffering. Packet time stamps referenced to a local clock create a phase offset signal. A shortest-delay offset generator uses a moving-window filter to select the samples of the phase offset signal having the shortest network propagation delay within the window. This shortest network propagation delay filter minimizes the effect of network jitter under the assumption that queuing delays account for most of the network jitter. The addition of this filtered phase offset signal to a free-running local clock creates a time reference that is synchronized to the remote clock at the source thus allowing for the transport of audio, video, and other time-sensitive real-time signals with minimal latency.

Disclosed is method and apparatus for packaging multilayered integrated circuit (IC) chips, on which logic circuits and/or memory arrays are disposed and interconnected in a novel way permitting the addressing (i.e. selection) of the logic circuits and/or arrays on these IC chip layers using a minimum number of connections and with the shortest propagation delays.

A method and apparatus is disclosed for adjusting at least one of a supply voltage and a clocking frequency applied to digital circuitry of a computing device, wherein the digital circuitry comprises a critical path circuit. A propagation delay frequency representing a propagation delay of the critical path circuit is generated, and a frequency error signal is generated representing a difference between a reference frequency and the propagation delay frequency. At least one of the supply voltage and the clocking frequency is adjusted in response to the frequency error signal.

A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.

An apparatus and method for measuring and compensating for delay between a main base station and a remote base station interconnected by an optical cable. The main base station inserts a test pattern into an overhead part of an SDH frame to transmit the SDH frame to the remote base station, receives the SDH frame looped back by the remote base station to detect the test pattern, and measures propagation delay according to the test pattern. At least one frame alignment word (FAW) is detected at a predetermined position in the received SDH frame, and a delay error is calculated according to FAW detection information. The measured propagation delay with the delay error is compensated and produces propagation delay caused by the optical cable. A modulator/demodulator (MODEM) compensates for delay of a baseband signal to be transmitted to the remote base station.

A test signal comprising a periodic waveform, such as a triangular waveform and sawtooth waveform, is used for propagation delay matching in a transceiver front-end. The test signal is separately fed to the envelope path and the RF path. At the power amplifier stage, a phase modulator is used to obtain the envelope signal and the phase modulated RF signal for demodulation by an IQ demodulator. At the output end of the IQ demodulator, the I-signal is measured while the delay block is adjusted in order to vary the propagation delay. When the propagation delay matching is correct, the peak-to-peak value of the I-signal is a minimum. Preferably, during calibration using the test signal, the transmitter RF power amplifier is disabled so that no spurious signals will be sent. The transmitter can be an EDGE polar transmitter, a non-EDGE transmitter or a EER polar transmitter.

A technique is described for improving packet performance in an access network. The access network comprises a Head End and a plurality of nodes. The access network further includes at least one shared-access upstream channel used by the first plurality of nodes to communicate with the Head End. Propagation delay data associated with at least a portion of the plurality of nodes using the at least one upstream channel is obtained. The propagation delay data is then used to dynamically adjust the lookahead time value associated with the generating of MAP messages for the at least one upstream channel.

Techniques for correcting time synchronization inaccuracy caused by asymmetric delays on a communication link. Time synchronization according to the present techniques includes determining an asymmetry in a propagation delay on a communication link used by a first device and a second device to exchange timing information and incorporating the asymmetry into a determination of a clock offset between the first and second devices.

PCT No. PCT/JP96/01123 Sec. 371 Date Apr. 23, 1998 Sec. 102(e) Date Apr. 23, 1998 PCT Filed Apr. 25, 1996 PCT Pub. No. WO96/34477 PCT Pub. Date Oct. 31, 1996It is objected to simplify a procedure concerning bandwidth acquisition. Bandwidth acquiring means 809 of a second transmitting apparatus 814 acquires a bandwidth which was used by a first transmitting apparatus 806 by using a propagation delay identifier 804 read from first transmitting apparatus 806 and a maximum transmission data size 805 after stopping transmission of first transmitting apparatus 806. Each apparatus is composed so that transmission is started using this bandwidth and because returning and re-acquisition are not accompanied when the transmission is switched, necessary procedure can be simplified. Further, it is possible to effectively use the bandwidth by using a propagation delay identifier.

A clocking system and method in a point-to-point bus configuration overcomes the limitations of conventional approaches. In one embodiment, the present invention ensures the same phase relationship for the write clock in the write direction for all data transfers between modules, and similarly the same phase relationship for the read clock in the read direction for all data transfers between modules, regardless of module location. In another embodiment, on a given module, all transfers of data between a data buffer and a memory device in both read and write directions are clocked by a read clock signal and a write clock signal that have the same phase relationship and have the same propagation delay as the data bus between the buffer and the memory device.

A system, apparatus, and method for determining the distance between two objects using an indirect propagation delay measurement is disclosed. A frequency hopping scheme (such as the Bluetooth™ technology) is used to measure the relative phase offset of the received signal between the various frequencies. For a given distance between the objects, the phase offset vs. frequency curve is a straight line with the slope dependent upon the measured distance. After the phase of the received signals is detected, the data is plotted on a curve and the slope is calculated.

A method of processing and validating transactions on a multi-chain network including receiving first and second pluralities of transactions, recording the first and second pluralities of transactions to first and second blocks on a first blockchain in a multi-chain network, publishing the first and second plurality of transactions to a first managed topic associated with the multi-chain network on a first messaging server, defining a first published transactions, and transmitting the first published transactions to a first subscriber, defining a first transmitted transaction. Receipt of the first transmitted transaction initiates generation of a first merged block comprising the first published transactions and recording of the first merged block to a second blockchain on the multi-chain network. The first blockchain has a parameter difference from the second blockchain selected from the group consisting of block generation time, transaction throughput, transaction latency, stale block rate, block propagation delay and consensus algorithm used.

For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.

An Ethernet architecture is provided for connecting a computer system or other network entity to a dedicated Ethernet network medium. The network interface enables the transmission and receipt of data by striping individual Ethernet frames across a plurality of logical channels and may thus operate at substantially the sum of the individual channel rates. Each channel may be conveyed by a separate conductor (e.g., in a bundle) or the channels may be carried simultaneously on a shared medium (e.g., an electrical or optical conductor that employs a form of multiplexing). On a sending station, a distributor within the sender's network interface receives Ethernet frames (e.g., from a MAC) and distributes frame bytes in a round-robin fashion on the plurality of channels. Each “mini-frame” is separately framed and encoded for transmission across its channel. On a receiving station, the receiver's network interface includes a collector for collecting the multiple mini-frames (e.g., after decoding) and reconstructing the frame's byte stream (e.g., for transfer to the receiver's MAC). The first and last bytes of each frame and mini-frame are marked for ease of recognition. Multiple unique idle symbols may be employed for transmission during inter-packet gaps to facilitate the collector's synchronization of the multiple channels and/or enhance error detection. A maximum channel skew is specified, and each received channel may be buffered with an elasticity that is proportional to the maximum skew so that significant propagation delay may be encountered between channels without disrupting communications.