982 results about "Clock rate" patented technology

The invention relates to the technical field of synchronization in data communication, and provides a PTP protocol-based chip-level hardware timestamp generation method and system, and the method comprises the steps: 1, receiving a synchronization message and a delay request message from a main clock, carrying out the evaluation of a physical layer signal, and recording a first hardware timestamp; 2, responding to the received delay request message, generating and sending a delay response message, acquiring bidirectional transmission delay data by exchanging the delay request and the delay response message, and calculating clock skew in combination with the first hardware timestamp and the bidirectional transmission delay data; 3, adjusting the local clock frequency according to the clock skew; 4, after the synchronization is completed, associating the second hardware timestamp with the corresponding data message, and storing the associated data in a buffer area in the chip; and 5, generating standardized timestamp information, and outputting the standardized timestamp information through a chip interface. And high-precision time synchronization and timestamp generation are realized.

Embodiments pertain to reducing power consumption in a computing system comprising one or more deterministic processors. A controller generates a plurality of control signals for a voltage regulator to regulate a supply voltage of a respective one of the one or more deterministic processors. A power management module determines an initial profile for power consumption and performance of an algorithm executed on the respective deterministic processor having an initial value for the supply voltage and an initial value for a clock frequency. The power management module further determines a target profile for power consumption and performance of the algorithm executed on the respective deterministic processor. The controller modifies the plurality of control signals based on the initial profile and the target profile. The respective deterministic processor executes the algorithm while the supply voltage is dynamically modified by the voltage regulator based on the modified plurality of control signals.

The invention discloses a single-chip microcomputer hierarchical dormancy control method based on dynamic power consumption prediction, and relates to the technical field of single-chip microcomputer low power consumption control, and the method specifically comprises the steps: building a mapping relation between a load current and a clock frequency; setting a dynamic dormancy threshold value; constructing a dynamic power consumption prediction model; a dormancy strategy is designed, module-level power consumption management and single-chip microcomputer function-based power consumption management are adopted, the callable frequency or the maximum operation duration of each function is distributed according to task priorities and battery residual energy consumption, and single-chip microcomputer peripherals are triggered through events and are independently awakened; and executing the sleep strategy, automatically awakening the single chip microcomputer according to a preset awakening condition, and realizing abnormity positioning and processing based on threshold comparison and power consumption monitoring in the process of executing the sleep strategy. According to the invention, module-level power consumption management and single-chip microcomputer function-based power consumption management are realized, the limitation of traditional global dormancy is broken, the need of overall reset during wakeup is avoided, and the response speed is improved while the energy consumption is reduced.

The invention relates to the technical field of microcontrollers, and provides an MCU information protection method and device, electronic equipment and a readable storage medium, and the method comprises the steps: checking a storage access request according to an access control list; wherein the access control list comprises an authorized storage area and an authorized operation type corresponding to the authorized storage area; the storage access request is used for accessing a target storage area of the MCU; according to the debugging secret key, an interface debugging request is checked, and the interface debugging request is used for debugging a target debugging interface of the MCU; identifying a target code instruction of the MCU, and performing pre-execution verification and dynamic monitoring on the target code instruction; adjusting the clock frequency and the clock phase of the MCU according to the load change information and the power consumption change information of the MCU; and implementing encryption measures on the target data transmission channel of the MCU by using the encryption algorithm. According to the technical scheme provided by one or more embodiments of the invention, the data security and the anti-attack capability of the MCU can be improved.

A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

The invention provides an image enhancement system and method and a medium. The system comprises (N-1) row cache FIFO (First In First Out) which are connected in series, N row cache registers, a Demosaic module, a G component cache FIFO and a G component cache register. According to the invention, by reasonably controlling the read-write of the row cache FIFO and the register, at least five pixel points are output all the time under the condition that any number of pixel data is transmitted for each row of image data of each clock, so that the calculation requirement of the Demosaic algorithm is met. Under the condition of balancing and optimizing the combinational logic series to be executed in each clock period and the occupation of the total register, in the pipeline design of the Demosaic algorithm, the finiteness of hardware internal resources and the time sequence convergence problem of high clock frequency are fully considered, and by combining the combinational logic series optimization and the pipeline series optimization, the time sequence convergence problem of the high clock frequency is fully solved. In this way, better occupation of various resources of the FPGA is achieved, and efficient calculation is achieved. Based on the calculation strategy provided by the invention, the image enhancement process is finally realized, and the high-quality color display image is obtained.

The invention discloses a power consumption control method and device for a power distribution network monitoring control chip and a storage medium, and the method comprises the steps: carrying out the clock domain division of the power distribution network monitoring control chip, and obtaining a target clock domain; obtaining current load data and historical load data of the target clock domain; according to the historical load data, trend prediction processing is carried out by using an autoregressive moving average model to obtain predicted load data; according to the predicted load data and the power consumption state of the control chip, performing action evaluation processing by using preset reinforcement learning to obtain a state action function value; calculating a to-be-adjusted clock frequency and a to-be-adjusted voltage according to the current load data; determining a predicted clock frequency and a predicted voltage according to the state action function value; and performing power consumption control on the target clock domain according to the target clock frequency and the target voltage to obtain a power consumption control result. The power consumption control is realized, and the resource utilization rate and the control efficiency are improved. The method can be widely applied to the technical field of electric power engineering.

The invention provides a novel clock control method and system based on FPGA, and relates to the technical field of signal processing. The system provided by the invention comprises: a VCXO voltage-controlled crystal oscillator, a digital-to-analog converter, a PLL phase-locked loop module, a DDMTD measurement module and an adaptive clock control module. The phase-locked loop is implemented, a phase detection algorithm and a clock control algorithm are executed based on a single FPGA chip, and the hardware design complexity is low. The invention uses a digital dual-mixing time difference method (DDMTD) to measure and obtain a clock phase detection result, and cooperates with a dynamic PID clock control algorithm to quickly adjust the local clock frequency, so as to realize the fast tracking and locking of the frequency and phase between the local clock and the clock source. The dynamic PID clock control algorithm of the invention dynamically adjusts the parameter P of the PID algorithm in real time according to the state, the clock frequency deviation and the clock phase difference, so that the algorithm has the advantages of stronger locking ability, shorter convergence time and faster response.

A circuit system includes a circuit board including a plurality of integrated circuit (IC) chips. The circuit board is configured to be immersed in a two-phase cooling fluid. The circuit system includes a controller. The controller is configured to, in a control process: obtain temperature data indicative of respective internal temperatures of the plurality of IC chips, predict respective future internal temperatures of the plurality of IC chips based on the respective internal temperatures, and adjust clock frequencies and power supply voltages of the plurality of the IC chips such that the predicted respective future internal temperatures are within a target temperature range. A clock frequency of a first IC chip of the plurality of IC chips is adjusted to be different from a clock frequency of a second IC chip of the plurality of IC chips.

The invention relates to the technical field of chip testing, and discloses a clock reset system-level verification method and device based on general verification methodology, and the method comprises the steps: firstly analyzing a clock topological relation defined in a system control unit architecture document, and generating a clock reset information table; on the basis of the information table, an executable verification environment component and a virtual interface component are automatically generated through a script, the verification environment component comprises an excitation forwarding and processing component and can generate clock and reset signals matched with framework definition, and the virtual interface component can generate actual clock and reset waveforms; and finally, constructing a verification platform based on the components, calling the excitation sequence in the parameterized test sequence library, and carrying out system-level clock reset verification on the digital chip. And meanwhile, the parameterized test sequence library supports flexible adjustment of a verification scene and ensures that a test case fits a clock frequency defined by an architecture document, and a reset mechanism can improve the efficiency, accuracy and reliability of digital chip clock reset system-level verification.

The invention discloses an IIR (Infinite Impulse Response) filter device and a filtering method thereof, and the IIR filter device comprises a head data module which stores current input data and two pieces of input historical data; the filtering module is used for storing output data of each stage through a first position, corresponding to each stage of filtering, of the intermediate data module, exchanging addresses of the first position and a second position, reading current input data and two pieces of input historical data from a specified position through the calculation module, and outputting the data; two pieces of output historical data are read from the intermediate data module and stored in the tail data module, data are output after filtering, and lower-level filtering is triggered; the tail data module is used for storing the output data of the level of filtering as the input data of the lower level of filtering when any level of filtering is completed; wherein the designated position of the first-stage filtering is a head data module, and the designated positions of the other-stage filtering are tail data modules. According to the method, the data reading and writing time is shortened, the calculation pipeline is prevented from being interrupted, the required data storage is reduced by half, and the required clock frequency is reduced.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

The invention relates to a method for realizing multi-channel ADC (Analog to Digital Converter) data synchronization processing based on an FPGA (Field Programmable Gate Array), which comprises the following steps that: the FPGA receives a clock frequency generated by an external clock generator and takes the clock frequency as a working clock of the FPGA; a plurality of groups of same-frequency clocks and same-phase clocks are generated in the FPGA and are respectively used as working clocks of the ADC chips; the FPGA receives sampling data of each ADC, an enable signal is set, and when the enable signal is effective, digital down-conversion, decimation filtering and FIR filtering are carried out on each sampling data; and after FIR filtering is completed, another enable signal ENend is generated, and data are further stored or transmitted to an upper computer. According to the method and the device for realizing the multi-channel ADC data synchronous processing based on the FPGA, the processor and the computer readable storage medium thereof, synchronous start and stop of the processing flow are controlled through the enable signals ENstart and ENend, synchronous processing of the multi-channel ADC data is ensured, accuracy and effectiveness are improved, and the method and the device have a wide application range.

According to the task scheduling and resource management system and method provided by the invention, full-link automatic management from peripheral event triggering to resource dynamic allocation and recovery is realized through close cooperation of the peripheral collaborative network, the dynamic power management module, the task scheduling module, the self-adaptive clock module and the exception monitoring unit. Compared with the prior art, the system not only can perform hardware-level scheduling in real time according to task priorities and system loads, but also can improve energy efficiency through regionalized power supply and clock frequency adjustment, supports rapid recovery and storage of task contexts, has a perfect fault monitoring and isolation mechanism, and is high in practicability. Therefore, the real-time performance, the energy consumption efficiency and the operation reliability of the system are obviously improved.

Scheduling and clock management for real-time system quality of service (QoS) is disclosed. In an implementations, a resource manager determines a target work rate based on respective job deadlines of a plurality of jobs on a processing platform. Determining the target work rate can include ordering the plurality of jobs based on the respective deadlines, determining an amount of work required to reach each of the respective deadlines, identifying one deadline among the respective deadlines as a most constraining deadline based on the amount of work required to reach that one deadline, and determining the target work rate based on the most constraining deadline. The resource manager adjusts a clock rate of the processing platform based on at least the target work rate.

The invention provides a time synchronization method based on an IEEE 1588 protocol, and relates to the technical field of time synchronization. Comprising the following steps: firstly, establishing a network-based master-slave clock model to characterize a clock frequency; secondly, acquiring a timestamp set of master and slave clocks of the current round, and calculating average transmission delay and time offset; thirdly, a clock synchronization equation of Kalman filtering is built based on a clock model, time offset and drift serve as input, an optimal time offset value is obtained, and a local clock is adjusted to complete synchronization of the current round. Then, a new timestamp set is obtained for the next round, the average transmission delay and the time offset are calculated, and the optimal offset value is determined through a Kalman filtering equation; meanwhile, the number of cycles is calculated according to the offset value and the receiving timestamp, and frequency compensation is carried out on the slave clock. According to the invention, the problem of low time synchronization precision in the prior art is effectively solved.

The invention relates to a method for awakening electronic equipment, which comprises the following steps that: when the electronic equipment is in a dormant state, a subsystem receives a first awakening event; in response to determining that the first wake-up event belongs to the subsystem external wake-up event, the subsystem sets the clock frequency of a first sub-module of the subsystem from a current first frequency value to a second frequency value, the first frequency value is the running frequency set when the subsystem is in a dormant state, and the second frequency value is the highest running frequency allowed by the subsystem; the first sub-module of the subsystem is configured to control the temporary operation frequency of the subsystem; the subsystem analyzes the first wake-up event and sends a related first message to the main system; in response to a response to the first message returned by the main system, the subsystem sets the clock frequency of the first sub-module as a first frequency value; and in response to determining that all clock frequencies of the first sub-module and other sub-modules of the subsystem are set as the first frequency value, the subsystem enters a dormant state.

The present application discloses a data decoding method and apparatus, an electronic device, and a storage medium. The method comprises: acquiring the clock rate of a single-channel clock; on the basis of the clock rate of the single-channel clock, sampling, at rising edges and falling edges of the single-channel clock, a data stream formed using Manchester encoding, and obtaining a plurality of pieces of sampling data; and decoding each piece of sampling data, and obtaining decoded data of the data stream. According to the data decoding method provided by embodiments of the present application, clock resources required to be occupied when the Manchester-encoded data is decoded can be reduced while improving the decoding efficiency.

The invention provides a processor chip with adjustable power consumption, which is integrated with a plurality of functional cores and a plurality of routers, all the routers are mutually connected to form an on-chip network, all the functional cores are mounted on the on-chip network to realize mutual communication, and the chip further comprises a power consumption management module, all the functional cores and all the routers are configured to be subjected to clock frequency adjustment by a power consumption management module, and the power consumption management module is used for adjusting the clock frequency of the processor chip based on a received frequency raising request from the functional cores and / or the routers; the clock frequency of the processor chip is adjusted based on a self-configured adjusting mechanism; wherein the power consumption management module is configured to support unified adjustment of clock frequencies of all the functional cores and / or all the routers, and independently adjust the clock frequencies of each functional core and each router; and the power consumption management module is mounted on the network-on-chip to realize communication with each router and each functional core.

The invention discloses a time service module and electronic equipment. The time service module comprises a programmable logic module, a main control module and a crystal oscillator module; the programmable logic module is connected with the crystal oscillator module, the crystal oscillator module outputs a clock frequency signal, and the programmable logic module outputs a first pulse signal according to the clock frequency signal; the programmable logic module comprises a source end logic gate unit, an output end logic gate unit and a counting unit, the source end logic gate unit is connected with a source pulse signal, the output end logic gate unit is connected with a first pulse signal, and the counting unit is connected with the source end logic gate unit and the output end logic gate unit; the counting unit outputs a first data signal according to the number of the switched-on logic gates in the source end logic gate unit and the number of the switched-on logic gates in the output end logic gate unit; the master control module calculates the phase difference between the first pulse signal and the source pulse signal according to the first data signal. The time service module provided by the invention has relatively high locking precision.

The invention provides a universal serial bus (USB) 2.0 host speed reduction bridge based on bidirectional protocol handshake and a prototype verification or hardware simulation acceleration platform, which are characterized in that a slow-speed side module runs at a slow clock frequency, is responsible for realizing a protocol layer of a USB protocol and a physical link layer function of the USB protocol, and communicates with a USB2.0 host controller in a chip design (DUT) to be tested; the original speed side module works under the original clock frequency, logic of a protocol layer of a USB protocol and a physical link layer of the USB protocol is achieved, communication with an external real USB2.0 slave end device is achieved through a USB2.0 PHY, data caching and synchronization are achieved through a data caching RAM, and the bridge control module overall plans the whole situation and accurately regulates and controls independent handshake of the USB2.0 protocol layers on the two sides under the original clock frequency. Through bidirectional protocol handshake on the two sides of the speed reduction bridge, data communication between a low-speed to-be-tested chip design (DUT) in a chip prototype verification platform and external standard-speed real USB slave equipment is achieved through the speed reduction bridge.

The invention relates to the field of precise motion control, in particular to a precise motion control method and system for a multi-axis linkage direct-drive-force tool tower crane. Comprising the following steps: acquiring a processing track, dispersing the processing track into a plurality of spatial motion units, and determining a target displacement for each motion axis; receiving a completion signal; and after determining that the motion axis participating in the current space motion unit completes the corresponding target displacement according to the completion signal, obtaining the completion time of each motion axis, and issuing the target displacement corresponding to the next space motion unit to each motion axis by taking the completion time of the motion axis with the longest completion time as a time reference. Therefore, each motion shaft is started to move the next space motion unit. The technical problems that the machining precision is reduced and the product quality is unqualified due to clock frequency drift and movement shaft synchronization deviation accumulation caused by gradual change of microcosmic physical characteristics in a system of a multi-shaft linkage direct-driving-force tool tower crane are solved.

The invention discloses an external plug-in card clock switching control method and device, a controller and a storage medium, and relates to the technical field of computer hardware, and the method comprises the steps: in the operation process of a storage device, collecting the operation information of an external plug-in card in real time, calculating the real-time rate of a link, and dynamically detecting the output state of a clock source; high-precision matching between the clock frequency and the link requirement is achieved, and if the relative deviation between the link clock rate and the link real-time rate exceeds the first preset threshold value, the clock switching instruction is sent to the clock source output switching module so that the clock source output switching module can be switched to the target clock source. Therefore, it is ensured that the relative deviation between the link real-time rate and the link clock rate output by the target clock source is within the first preset threshold value, waste of clock resources is reduced, and the overall energy consumption of the storage device is reduced.

The invention discloses an FPGA-oriented DSP layout optimization method for a CNN accelerator, and the method comprises the following steps: S1, DSP path information extraction: converting a designed netlist into graph representation, and carrying out data path DSP node recognition and data path DSP graph construction; and S2, data path driven DSP layout: distributing data path DSP nodes to specific positions on the FPGA according to the extracted data path DSP diagram. According to the method, a data path DSP graph is automatically extracted and constructed through DSP node classification based on a graph neural network (GCN) and an optimization algorithm of a minimum cost flow (MCF) model, and compact layout and cascade constraint optimization are combined, so that the time sequence performance and the calculation efficiency of the layout are greatly improved, meanwhile, the clock frequency and the throughput are remarkably improved, and the time sequence performance and the calculation efficiency of the layout are greatly improved. And a universal and efficient FPGA layout solution is provided for various CNN accelerator architectures.

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

The invention relates to the field of digital signal processing, in particular to a miniature digital transceiver module which comprises a signal processing board and a power clock board. The signal processing board and the power supply clock board are stacked and interconnected through a high-speed connector; the signal processing board integrates multiple ADC acquisition channels and DAC output channels, and is internally provided with an RFSOC chip to realize multichannel digital down-conversion, waveform generation and signal processing functions. The power supply clock board integrates a power supply conversion module and a clock frequency synthesizer, provides various power supply varieties for the module, and generates a time sequence, a sampling clock and a reference clock. The stacking design of the two board cards forms a high-integration digital transceiver module, thereby saving a large amount of space and improving the system integration. The scheme is obviously superior to a traditional design method in the aspects of volume, power consumption, performance and the like, and is particularly suitable for equipment sensitive to an outer envelope.

The invention provides a clock frequency monitoring circuit and method, and the circuit comprises a first multiplexer which selects and outputs a first clock signal; the second multiplexer is used for selectively outputting a second clock signal; the first counter is triggered based on the first enable signal and is used for counting the first clock signal progressively until the first clock signal progressively decreases to 0; the second counter is triggered based on the second enable signal, performs incremental counting on the second clock signal and outputs a count value; the count value comparison module is used for comparing the count value with a target set value and outputting a state indication signal according to a comparison result; the counter heavy load controller is used for generating a first enable signal and a second enable signal according to the first clock signal and the second clock signal, and triggering the count value comparison module to start working after the counting of the second counter is finished; and determining whether to restart the next round of monitoring according to the state indication signal. By using the scheme of the invention, monitoring of any clock frequency to be measured can be realized.

In one embodiment, a system includes a digitally controlled oscillator (DCO) to generate a local clock having a local clock frequency, and clock synchronization circuitry to receive from a device a signal indicative of a remote clock frequency, compare measures of the remote clock frequency and the local clock frequency; generate a digital control command based on the comparison; and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

The invention provides a clock frequency adjusting method and device, an image processor, equipment and a medium, and relates to the technical field of computers. The method comprises the following steps: receiving current counting information corresponding to at least one preset monitoring event related to the running state of the GPU; constructing a feature vector based on the current counting information; the feature vector is input into a pre-trained prediction model, the load sudden increase probability is obtained, the prediction model is obtained through training based on historical counting information corresponding to a preset monitoring event and load sudden increase labeling data, and the load sudden increase probability represents the probability that the operation load of the GPU is to be suddenly increased; and adjusting the current clock frequency of the GPU based on the load sudden increase probability. According to the scheme, the feature vector can be constructed based on the monitoring event counting information, the load sudden increase probability is obtained through the prediction model, dynamic adjustment of the clock frequency is achieved, and then the response efficiency and the adjustment accuracy of GPU clock frequency adjustment are improved.

Embodiments pertain to reducing power consumption in a computing system comprising one or more deterministic processors. A controller generates a plurality of control signals for a voltage regulator to regulate a supply voltage of a respective one of the one or more deterministic processors. A power management module determines an initial profile for power consumption and performance of an algorithm executed on the respective deterministic processor having an initial value for the supply voltage and an initial value for a clock frequency. The power management module further determines a target profile for power consumption and performance of the algorithm executed on the respective deterministic processor. The controller modifies the plurality of control signals based on the initial profile and the target profile. The respective deterministic processor executes the algorithm while the supply voltage is dynamically modified by the voltage regulator based on the modified plurality of control signals.