417 results about "Clock rate" patented technology

The invention relates to the technical field of chip testing, and discloses a clock reset system-level verification method and device based on general verification methodology, and the method comprises the steps: firstly analyzing a clock topological relation defined in a system control unit architecture document, and generating a clock reset information table; on the basis of the information table, an executable verification environment component and a virtual interface component are automatically generated through a script, the verification environment component comprises an excitation forwarding and processing component and can generate clock and reset signals matched with framework definition, and the virtual interface component can generate actual clock and reset waveforms; and finally, constructing a verification platform based on the components, calling the excitation sequence in the parameterized test sequence library, and carrying out system-level clock reset verification on the digital chip. And meanwhile, the parameterized test sequence library supports flexible adjustment of a verification scene and ensures that a test case fits a clock frequency defined by an architecture document, and a reset mechanism can improve the efficiency, accuracy and reliability of digital chip clock reset system-level verification.

According to the task scheduling and resource management system and method provided by the invention, full-link automatic management from peripheral event triggering to resource dynamic allocation and recovery is realized through close cooperation of the peripheral collaborative network, the dynamic power management module, the task scheduling module, the self-adaptive clock module and the exception monitoring unit. Compared with the prior art, the system not only can perform hardware-level scheduling in real time according to task priorities and system loads, but also can improve energy efficiency through regionalized power supply and clock frequency adjustment, supports rapid recovery and storage of task contexts, has a perfect fault monitoring and isolation mechanism, and is high in practicability. Therefore, the real-time performance, the energy consumption efficiency and the operation reliability of the system are obviously improved.

The invention provides a universal serial bus (USB) 2.0 host speed reduction bridge based on bidirectional protocol handshake and a prototype verification or hardware simulation acceleration platform, which are characterized in that a slow-speed side module runs at a slow clock frequency, is responsible for realizing a protocol layer of a USB protocol and a physical link layer function of the USB protocol, and communicates with a USB2.0 host controller in a chip design (DUT) to be tested; the original speed side module works under the original clock frequency, logic of a protocol layer of a USB protocol and a physical link layer of the USB protocol is achieved, communication with an external real USB2.0 slave end device is achieved through a USB2.0 PHY, data caching and synchronization are achieved through a data caching RAM, and the bridge control module overall plans the whole situation and accurately regulates and controls independent handshake of the USB2.0 protocol layers on the two sides under the original clock frequency. Through bidirectional protocol handshake on the two sides of the speed reduction bridge, data communication between a low-speed to-be-tested chip design (DUT) in a chip prototype verification platform and external standard-speed real USB slave equipment is achieved through the speed reduction bridge.

The invention relates to the field of precise motion control, in particular to a precise motion control method and system for a multi-axis linkage direct-drive-force tool tower crane. Comprising the following steps: acquiring a processing track, dispersing the processing track into a plurality of spatial motion units, and determining a target displacement for each motion axis; receiving a completion signal; and after determining that the motion axis participating in the current space motion unit completes the corresponding target displacement according to the completion signal, obtaining the completion time of each motion axis, and issuing the target displacement corresponding to the next space motion unit to each motion axis by taking the completion time of the motion axis with the longest completion time as a time reference. Therefore, each motion shaft is started to move the next space motion unit. The technical problems that the machining precision is reduced and the product quality is unqualified due to clock frequency drift and movement shaft synchronization deviation accumulation caused by gradual change of microcosmic physical characteristics in a system of a multi-shaft linkage direct-driving-force tool tower crane are solved.

The invention provides a clock frequency adjusting method and device, an image processor, equipment and a medium, and relates to the technical field of computers. The method comprises the following steps: receiving current counting information corresponding to at least one preset monitoring event related to the running state of the GPU; constructing a feature vector based on the current counting information; the feature vector is input into a pre-trained prediction model, the load sudden increase probability is obtained, the prediction model is obtained through training based on historical counting information corresponding to a preset monitoring event and load sudden increase labeling data, and the load sudden increase probability represents the probability that the operation load of the GPU is to be suddenly increased; and adjusting the current clock frequency of the GPU based on the load sudden increase probability. According to the scheme, the feature vector can be constructed based on the monitoring event counting information, the load sudden increase probability is obtained through the prediction model, dynamic adjustment of the clock frequency is achieved, and then the response efficiency and the adjustment accuracy of GPU clock frequency adjustment are improved.

The invention relates to the technical field of integrated circuits, and provides a dynamic voltage frequency configuration method, device, equipment and program product of a chip, and the method comprises the steps: for each chip in a sample set comprising a plurality of chips, determining a performance index based on a chip parameter and a preset test frequency; comparing the performance index of each chip with a preset limit value to determine the number of chips passing the test; based on the number of the chips passing the test and the total number of the chips in the sample set, determining the actual yield under the preset test frequency; comparing the actual yield with a target yield, and iteratively adjusting the preset test frequency until the target yield is met so as to obtain an effective clock frequency; a voltage frequency table is generated based on the effective clock frequency and the corresponding voltage. According to the method, the relationship between the effective clock frequency and the yield is fully reflected, the generated voltage frequency table can provide the optimal working parameter combination for the chip under the condition of ensuring the yield, and the performance and efficiency of chip design are improved.

The invention discloses a system reference clock frequency accuracy automatic calibration circuit and a calibration method thereof, and belongs to the technical field of frequency sources, the calibration circuit comprises a first crystal oscillator, a first power divider, a second power divider, a second crystal oscillator, an analog switch, a radio frequency switch, a detector, a comparator, an FPGA controller, a digital analog converter, an operational amplifier and a temperature sensor. When an external high-precision reference clock is accessed, the FPGA controller automatically switches a frequency measurement reference, performs high-precision frequency measurement on a 100MHz signal output by the first crystal oscillator, and judges whether calibration is needed or not according to frequency offset; if calibration is needed, the output voltage of the digital-to-analog converter is adjusted, the Vc end of the first crystal oscillator is controlled after operational amplification, and frequency closed-loop adjustment is achieved. According to the method, the crystal oscillator does not need to be disassembled, calibration is rapidly completed on site, and system availability and long-term frequency stability are remarkably improved.

The invention provides a 200GE service data transmission method based on 224G high-speed SerDes, a chip and a communication system, and the method comprises the steps that a PCS sending module carries out PCS sending processing on obtained upstream data to obtain first PCS data; the PCS sending module sends first PCS data to the PMA sending module through the rate increasing module according to the first PCS clock rate and the first PCS data bit width; the rate increasing module determines first clock information according to the first PMA data bit width, the first PMA clock rate, the first PCS clock rate, the first PCS data bit width and the set bandwidth so as to increase the first PCS clock rate; the PCS sending module sends first PCS data according to the first PMA data bit width and the improved first PCS clock rate; the PMA sending module processes the first PCS data and sends the first serial data. The method can be applied to the fields of internet access and related services, the alignment mark insertion process is avoided so as to improve the sending rate of the PCS layer, and the PMA state frame is introduced so as to accelerate link convergence and improve link stability.

The present invention relates to the field of time synchronization, and relates to a precise clock synchronization parameter tracking method based on an augmented Kalman neural network. In the method, for a multi-hop network scenario where an ambient temperature changes and a link transmission delay is asymmetric, taking into account the impact of an accumulated asymmetric link transmission delay in a multi-hop network on clock synchronization accuracy, a multi-hop network clock observation equation containing an accumulated asymmetric link delay is derived, and on the basis of a quadratic polynomial model of a temperature and a clock frequency offset, a recursive state equation of the clock frequency offset and a temperature change is established; the evolution processes of an accumulated asymmetric delay and an unknown temperature coefficient are modeled as a first-order linear difference equation, and the accumulated asymmetric delay and the unknown temperature coefficient are augmented to a clock parameter tracking state space model; and an augmented Kalman neural network algorithm is used to realize joint tracking of a clock phase offset and a clock frequency offset of a slave node. This method employs a hybrid data-model-driven approach to perform joint tracking of the clock phase offset and frequency offset, thereby improving accuracy and robustness of clock parameter tracking.

The invention discloses a power line communication signal sending and receiving method and device based on a semi-parallel architecture, and belongs to the technical field of power system communication. The method comprises the following steps: obtaining a sending signal comprising a plurality of sub-signals, dynamically determining the number R of parallel processing units according to a transmission data rate and a clock frequency, phase adjustment, frequency domain transformation, linear combination and filtering processing are carried out through R parallel processing units in the DCT module, the matrix module and the multi-phase filter module in sequence, and finally processed signals are serialized and sent to a power line channel; and the receiving process reversely executes corresponding processing. Therefore, by implementing the method and the device, the problem that the transmission rate and the communication stability of the system are difficult to effectively improve while low resource consumption and low power consumption are ensured in the prior art can be solved.

The invention provides a control instruction time sequence synchronization method and device of a multi-node industrial control system. The control instruction time sequence synchronization method comprises the following steps: a control node calculates an initial time offset through a calibration frame, loops back a test frame to measure link transmission delay, and compensates a local clock of an execution node to realize initial alignment; periodically broadcasting a reference clock, calculating an accumulated drift amount in real time by an execution node, and adjusting a local clock frequency when the accumulated drift amount exceeds a threshold value; sending a control instruction based on a synchronization period starting moment, synchronizing a trigger signal to enable an execution node to sample data at the same time, and reading the data by a period ending boundary. According to the control instruction time sequence synchronization method, the initial synchronization precision is + / -10ns, the accumulated drift distance is controlled within + / -10ns, the total time sequence deviation is smaller than 100ns, system errors are effectively eliminated, the problem of crystal oscillator deviation is solved, the method can be compatible with an industrial bus, the hardware cost is reduced, and the multi-axis cooperative control precision and stability are greatly improved.

The present disclosure discloses an audio synchronization method for a USB device, a USB device, a storage medium and a communication system. The audio synchronization method for a USB device includes: obtaining an SOF clock calculated by the USB device, the SOF clock calculated by the USB device being obtained by simulating an SOF interrupt through software and recording a timestamp of the SOF interrupt; obtaining a target clock frequency of the USB device based on a clock frequency of a USB host, an SOF clock of the USB host and the SOF clock calculated by the USB device; and adjusting a clock frequency of the USB device based on the target clock frequency of the USB device.

A method of synchronizing a network side time sensitive network (TSN) converter (NW-TT) module within a user plane function (UPF) in a communication network with a master clock (GM) in the 5G time domain of the communication network is described. The method comprises the step of adjusting the clock frequency of an N3 interface to enable the N3 interface to be synchronized with the clock of a GM. The method includes generating one or more pulses on a pin of the N3 interface. The method includes detecting the one or more pulses on a pin of the NW-TT module. The method includes determining a time offset value (Offset NW-TT) between the N3 interface and the NW-TT module. The method includes adjusting a time or clock frequency of the NW-TT module using a determined time offset value (Offset NW-TT), thereby enabling time synchronization of the NW-TT module and the GM.

The invention discloses a chip internal reference clock frequency adjusting device and a chip. The chip internal reference clock frequency adjusting device comprises a system clock generating circuit; a system non-volatile memory circuit; the enable register is used for enabling the backup function of the backup register; the backup register is used for backing up an IRC frequency modulation control word currently used by an internal IRC clock source of the system clock generation circuit when the backup function of the backup register is enabled and a deep low power consumption mode request instruction is received; the alignment module is connected with the enable register, the backup register, the system non-volatile storage circuit and the system clock generation circuit and is used for aligning the system non-volatile storage circuit before the backup function of the backup register is enabled, the system receives a deep low-power-consumption wake-up request and the initialization of the system non-volatile storage circuit is finished; and IRC frequency modulation control words backed up by the backup register are selected to control the starting frequency of an internal IRC clock source of the system clock generation circuit. According to the device, the on-chip internal reference clock source is quickly adjusted, and the system wake-up time is shortened.

To suppress current consumption of a processor from exceeding an upper limit when each of a plurality of cores variably controls a clock frequency and a power supply voltage.SOLUTION: In a processor comprising a plurality of cores including floating-point units, a frequency / voltage control unit provided corresponding to each core supplies the corresponding core with a clock having a variable frequency and a power-supply voltage having a variable voltage. An instruction issuance control unit provided in each core controls the issuance of floating-point operation instructions to the floating-point unit, and reduces the issuance frequency of floating-point operation instructions to the floating-point unit when the current frequency value is greater than a reference frequency value or when the current power-supply voltage value is greater than a reference power-supply voltage value. This makes it possible to prevent the current consumption of the processor from exceeding an upper limit.SELECTED DRAWING: Figure 2

Network elements and methods of use, including a transmitter comprising a client-side input, signal and clock conditioning blocks, a modulation block, and antennas. The client-side input receives baseband signals having client data. The signal conditioning block adjusts signal characteristics of the baseband signals to generate intermediate signals. The clock conditioning block receives a first clock signal having a first clock frequency and adjusts signal characteristics of the first clock signal to generate a second clock signal having a harmonic frequency of the first clock frequency. The modulation block modulates the intermediate signals onto the second clock signal to generate antenna feed signals. The antennas generate radiated signals based on the antenna feed signals and couple the radiated signals into hollow waveguides. The radiated signals are radiated electromagnetic waves configured for coherent detection with a transmission frequency in a range between 300 Gigahertz (GHz) and 10 Terahertz (THz).

To provide a semiconductor device circuit configured to switch glitchfree between a plurality of independent Ethernet clock sources for operating a network interface. The semiconductor device comprises a clock provision unit comprising at least a first circuit branch configured to receive a first clock signal from a first clock source associated with a first network interface, and a second circuit branch configured to receive a second clock signal from a second clock source associated with a second network interface, the second clock source having a different clock rate than the first clock source.

The invention relates to the technical field of automatic detection, in particular to a multi-channel synchronous measurement analyzer for rotary transformers and a control method, and the analyzer synchronously controls a plurality of slave acquisition mother set modules to perform signal acquisition on a plurality of rotary transformers through a master acquisition mother set module; a corresponding FPGA unit in the acquisition sub-board module synchronously controls a plurality of analog-to-digital conversion units to perform signal acquisition; in the collecting process, the FPGA unit conducts multiple times of phase deviation measurement according to analog signals input by the analog-to-digital conversion unit and digital signals output by the analog-to-digital conversion unit, and corresponding parameters in the RC filters are dynamically adjusted based on the multiple times of measurement results. And meanwhile, the inter-board synchronization module dynamically adjusts the calibration period, and adjusts the calibration period again after a plurality of times of calibration period adjustment, and is also used for adjusting the clock frequency of the corresponding FPGA unit. According to the invention, signal acquisition can be carried out on multiple rotary transformers at the same time, and the test efficiency is improved while the measurement precision is ensured.

The invention provides a microprocessor architecture, a clock signal generation method and a storage medium, and is applied to the technical field of computers, the microprocessor architecture comprises a control unit, a clock signal source and a function unit, and the clock signal source comprises a basic clock unit and a frequency modulation clock unit. The frequency modulation clock unit comprises a first gating unit and at least two parallel initial signal generation units, the control unit configures first configuration information and first gating information, and the basic clock unit generates a basic clock signal; each initial signal generation unit generates a respective corresponding initial clock signal according to the first configuration information and the basic clock signal, and the first gating unit determines a target clock signal in each initial clock signal according to the first gating information and outputs the target clock signal to the functional unit, so that the functional unit operates based on the target clock signal. The clock signal source provided by the invention can effectively simplify the adjustment process of the clock frequency, improve the adjustment efficiency of the clock frequency, and meet the actual application requirements.

The invention discloses a hardware acceleration method and system for a ZSTD data compression algorithm based on an FPGA. Unified hardware implementation and collaborative optimization are carried out on three key links of LZ77 character matching, Huffman coding and finite state entropy coding in the ZSTD data compression algorithm. According to the system, a multi-channel parallel LZ77 character matching hardware architecture is adopted, and character matching is executed on continuous positions in a plurality of parallel windows at the same time. A modular design and a deep pipeline structure are adopted, and a buffer and pipeline mechanism is introduced among modules such as an LZ77 matching module, a Huffman coding module and a finite state entropy coding module. The 375MB / s compression throughput can be achieved under the 100MHz clock frequency, the compression speed is remarkably increased while the compression ratio is guaranteed, and the method is suitable for scenes with high requirements for compression performance of data centers, edge computing and embedded systems and has high practicability and popularization value.

Systems and methods are provided for dynamically changing the operating clock frequency of a circuit. Control circuitry determines a first workload value for a circuit operating at a first clock frequency. Control circuitry then detect a second workload value for the circuit, which is less than the first workload value. When the control circuitry detects the second workload value, the control circuitry calculates a second clock frequency which is greater than the first clock frequency. The control circuitry then causes the circuit to operate at the second clock frequency.

The invention provides a chip testing method and device and a medium, and the method comprises the following steps: determining an intermediate performance value of each target clock domain according to the clock frequency and predicted performance value of each target clock domain of a to-be-tested chip; determining a minimum value in the plurality of intermediate performance values as a target performance value; performing a performance test on the to-be-tested chip to obtain an actual performance value of a target clock domain; and if the actual performance value is not less than the target performance value, determining that the to-be-tested chip passes the test. According to the chip test method provided by the invention, whether the to-be-tested chip passes the test can be known only by performing the performance test on the target performance value. In this way, the number of performance values needing to be subjected to performance testing is greatly reduced, and therefore the number of times of data simulation and consumption of analysis resources are reduced.

The sink device according to an embodiment of the present disclosure comprises a memory configured to store a mapping table, an external device interface configured to receive a video signal from a source device through HDMI (High-Definition Multimedia Interface) standard and a controller configured to obtain a horizontal total value, a vertical total value, and an output frequency based on the video signal, obtain a pixel clock frequency mapped to the horizontal total value, the vertical total value, and the output frequency from the mapping table, and output the video signal based on the obtained pixel clock frequency.

Aspects of the disclosure are directed to determination of clock frequencies under thermal constraint. In accordance with one aspect, the disclosure includes initializing a first clock frequency and a second clock frequency with a randomly selected initial first clock frequency and a randomly selected initial second clock frequency; computing a gradient increment parameter based on a first constituent power function evaluated at an updated first clock frequency and on a second constituent power function evaluated at an updated second clock frequency; and determining an updated performance metric using the gradient increment parameter at the updated first clock frequency and at the updated second clock frequency and with a learning rate parameter.

The application discloses a data processing acceleration method and device based on information security, equipment and medium, applied to the field of information transmission and information encryption, comprising: generating a target golden sequence based on target data and a corresponding encryption code; bilateral sampling is performed on the target golden sequence, and the obtained rising edge sampling data and falling edge sampling data are sent to a first-in first-out queue; the sampling data is sent to a local data splicing component based on a preset phase difference and a preset clock frequency; the local data splicing component receives the sampling data based on a preset first high-speed clock, splices the data, and obtains target splicing data; and the target splicing data is sent to a local decryption component based on a preset first high-speed clock, so that the local decryption component decrypts the target splicing data based on a preset second high-speed clock and the encryption code. In this way, the processing flow of data can be effectively accelerated while ensuring information security.

The invention relates to the technical field of electromagnetic compatibility (EMC) design of electronic circuits, in particular to a method suitable for a flow cytometer and capable of reducing interference of clock signals on EMC. The method comprises the steps that S100, clock circuit components are concentrated in a 5mm * 5mm area of the top layer of a PCB, routing is limited to a second layer through buried holes, and fundamental frequency is dynamically set; s200, laying copper in a key area for grounding, and adding a ground bounce suppression array to three layers; s300, arranging an upper ground copper layer and a lower ground copper layer by using a flexible circuit board; s400, covering the top circuit with a ferrite alloy cover, and welding and grounding; and S500, the flow velocity and the cell density are collected in real time, the clock frequency is dynamically adjusted, a frequency stabilization mechanism exists in an extreme scene, radiation is effectively reduced, and the detection precision and stability are improved. According to the method, the EMC interference of the clock signal of the flow cytometer is reduced from multiple dimensions of source inhibition, shielding protection, connection optimization and cooperative control.

The present disclosure relates to a clock deviation compensation circuit, a chip and an electronic device, the clock deviation compensation circuit comprising a reference channel and at least one compensation channel, the reference channel comprising an input buffer, K frequency division generating units, a first output selector, the compensation channel comprising a first decoder, a multi-path clock selector, K frequency division synchronization units, a second output selector. The clock deviation compensation circuit of the present disclosure can adaptively output a clock frequency, and the clock deviation compensation range is constant.

According to the frequency adjusting system of the chip device and the chip device, a metal structure integrated on a back-end metal layer, a rewiring layer or a bonding layer of a chip is used as a temperature sensitive element, and the resistance value of the metal structure continuously changes along with the temperature of the chip in real time. And the resistance change is directly converted into voltage change applied to the reference voltage end of the clock generator, so that the clock generator can immediately respond and output corresponding clock frequency. And the change of the clock frequency further feeds back the influence on the chip temperature to form closed-loop control. According to the embodiment of the invention, through pure hardware circuit design, a direct, continuous and self-adaptive mapping relation between the temperature and the frequency is constructed, and dependence on a preset discrete temperature-frequency gear is not needed, so that adjustment delay or precision loss caused by insufficient fine gear division is avoided. According to the scheme, stepless, real-time and full-adaptive dynamic frequency regulation in a real sense is realized, the control logic is simplified, the system complexity is reduced, and the regulation response speed and the overall energy efficiency are remarkably improved.

The invention discloses a chip clock frequency determination method and device, equipment, a medium and a product, and relates to the technical field of chips. The method comprises the following steps: acquiring first chip parameter groups corresponding to a plurality of chips respectively, wherein chip parameters are used for describing chip characteristics of the chips corresponding to the first chip parameter groups; obtaining a second chip parameter group corresponding to the virtual chip based on the association relationship between the at least two chip parameters determined by the first chip parameter group; and obtaining a clock frequency set based on the first chip parameter set and the second chip parameter set, wherein the clock frequency set is used for providing candidate clock frequencies for executing the task. By acquiring the chip parameter group corresponding to the virtual chip, the coverage range of the chip parameters corresponding to the test is expanded, and the candidate clock frequency of the task executed by the target chip is acquired based on the clock frequency set, so that the applicability of the clock frequency result in different chip application scenes is improved.

The invention discloses a Bluetooth chip without a crystal oscillator and a frequency offset estimation method and device thereof, and the method comprises the steps: searching an ID packet transmitted by host equipment in a query state in a mode of polling a frequency offset value in a paging scanning state; when an ID packet is received in the paging scanning state, a current first frequency offset value is output, and the current first frequency offset value is the frequency offset value of the currently received ID packet in the polling search mode; estimating according to a synchronization head in the ID packet to obtain a second frequency offset value, wherein the second frequency offset value is a frequency offset value of the crystal oscillator-free Bluetooth chip determined based on the synchronization head relative to the host device; and correcting the first frequency offset value by using the second frequency offset value to obtain a final frequency offset value, and performing frequency offset compensation on the crystal oscillator-free Bluetooth chip according to the final frequency offset value to align the clock frequency of the host equipment. In conclusion, in the Bluetooth chip without the crystal oscillator, it can be ensured that the clock of the Bluetooth chip is aligned with the clock of the external host equipment so as to normally transmit and receive data packets.