4530 results about "Clock rate" patented technology

Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).

In a system for distributing data, distribution device is configured to distribute timestamp, offset and source location information for a digital data stream to an execution device, and the execution device is configured to seek digital data corresponding to the received information. The execution device is further configured to execute the digital data relative to a clock rate maintained by the distribution device. Related methods include receiving timestamp, offset and source location information for the digital data stream and seeking digital data corresponding to the received offset and source location information.

One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, clock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller, and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

A method and apparatus is disclosed for adjusting at least one of a supply voltage and a clocking frequency applied to digital circuitry of a computing device, wherein the digital circuitry comprises a critical path circuit. A propagation delay frequency representing a propagation delay of the critical path circuit is generated, and a frequency error signal is generated representing a difference between a reference frequency and the propagation delay frequency. At least one of the supply voltage and the clocking frequency is adjusted in response to the frequency error signal.

Inter-system interference cross-produce P₁₂ is reduced in a phase-based TOF system by randomizing instantaneous phase and/or frequency within a capture interval (or detection integration period). In one aspect, the TOF clock system frequency preserves long-term clock frequency stability but intentionally includes random or pseudo-random clock noise. The noise ensures the generated clock signals are temporally imperfect and lack substantial perfect periodicity. A second aspect causes the TOF clock system to hop frequency, preferably pseudo-randomly. TOF system homodyning favors detection of optical energy whose frequency correlates to the time-varying frequency of the emitted optical energy. Thus, the varying spectral spacing of the emitted optical energy reduces likelihood that an adjacent TOF system at any given time will emit optical energy of an interfering frequency. At least one aspect is employed, both aspects being mutually complementary to reduce the cross-correlation product P₁₂ without substantially affecting TOF system performance.

Devices and methods of detecting a predetermined audio signal in audio signals are provided. A device includes a processor coupled to a clock signal generator, a power controller and an audio detector. The power controller controls a clock rate provided to the processor by the clock signal generator, to control the device to operate in a low power mode having a relatively low power consumption or in a normal power mode having a relatively high power consumption. The audio detector receives audio signals and detects, in the low power mode, probable presence of a predetermined audio signal in the audio signals. The power controller controls the device to switch from the low power mode to the normal power mode responsive to the detected presence of the predetermined audio signal by the audio detector.

A constant voltage/constant power AC adapter converts AC voltage to DC voltage to provide power to a plurality of loads. The adapter's output characteristic is approximately a constant voltage as long as the output current draw by the loads is less than a threshold (e.g. a safety threshold for the adapter). If, however, the power draw on the adapter is such that the output current exceeds the threshold, the adapter then decreases its output voltage to maintain the power draw at a safe level. One or more loads that draw power from the adapter may be adapted to detect a drop in the AC adapter's output voltage. When such a voltage drop is detected, that information tells the load that too much current is being drawn from the adapter and that the load should throttle back (e.g., reducing battery charge current, CPU clock frequency, display brightness, etc.).

A multi-carrier communication system such as an OFDM or DMT system has nodes which are allowed to dynamically change their receive and transmit symbol rates, and the number of carriers within their signals. Changing of the symbol rate is done by changing the clocking frequency of the nodes' iFFT and FFT processors, as well as their serializers and deserializers. The nodes have several ways of dynamically changing the number of carriers used. The selection of symbol rate and number of carriers can be optimized for a given channel based on explicit channel measurements, a priori knowledge of the channel, or past experience. Provision is made for accommodating legacy nodes that may have constraints in symbol rate or the number of carriers they can support. The receiver can determine the correct symbol rate and number of carriers through a priori knowledge, a first exchange of packets in a base mode that all nodes can understand, or an indication in the header of the data packet which is transmitted in a base mode of operation that all nodes can understand.

A dynamic power controller is provided that identifies a clock frequency requirement of a processor and determines a voltage requirement to support the clock frequency requirement. The dynamic power controller transitions the processor to a power state defined by the clock frequency requirement and the voltage requirement. In particular, a voltage level indicated by the voltage requirement is supplied to the processor and the frequency distribution indicated by the frequency requirement is provided to the clocks signals of the processor.

An RFID tag includes separate transmit and receive clocks. In at least one embodiment, the transmit clock frequency is adjusted based on an amount of power available to transmit a response signal to a reader.

The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g., 800). The present invention further provides a wide data rate range CDR circuit (300,700), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit (606,656,706) that operates over a wide range of clock and data rates (e.g., 800) to provide various phase correction step sizes (e.g., 800) at a fixed VCO clock frequency. The divider (606,656,706) and a finite state machine (FSM) (612,662,712) of the exemplary CDR circuit (600,650,700) are manually programmed based on the data rate (614,667). Alternately, the data rate may be detected from a recovered serial data stream (718) during CDR operations (on-the-fly) utilizing a frequency detection circuit (725) to automatically program the divider (706) and FSM (712) to provide CDR circuit operation at the nearest base clock rate (716).

A disk drive is disclosed that estimates a sinusoidal error in a wedge time period due to eccentricity in the disk rotating to generate eccentricity compensation values. During a write operation a head is positioned over a target data sector within a target track, a write clock frequency is set using an eccentricity compensation value corresponding to the target data sector, and data is written to the target data sector using the write clock frequency. In this manner, the eccentricity compensation value adjusts the write clock frequency to better optimize the linear bit density from the inner to outer diameter tracks.

In an OFDM packet communication receiver, the deterioration of received signal quality is suppressed, even when carrier frequency error and/or clock frequency error exists between a transmitter and a receiver, and/or phase noise and/or thermal noise is superimposed to a received signal in a receiver.

A duty cycle correction (DCC) circuit including first and second clock dividers for dividing ordinary and sub-input clocks. Optional first and second variable delay devices delay the divided clocks. First and second mixers mix an optionally delayed ordinary divided clock and sub-ordinary divided clock, or an ordinary divided clock and an optionally delayed sub-ordinary divided clock. A logic combination device is included to produce a clock at the same frequency as the ordinary and sub-input clocks, with a corrected duty cycle.