762 results about "Clock rate" patented technology

The invention relates to the technical field of synchronization in data communication, and provides a PTP protocol-based chip-level hardware timestamp generation method and system, and the method comprises the steps: 1, receiving a synchronization message and a delay request message from a main clock, carrying out the evaluation of a physical layer signal, and recording a first hardware timestamp; 2, responding to the received delay request message, generating and sending a delay response message, acquiring bidirectional transmission delay data by exchanging the delay request and the delay response message, and calculating clock skew in combination with the first hardware timestamp and the bidirectional transmission delay data; 3, adjusting the local clock frequency according to the clock skew; 4, after the synchronization is completed, associating the second hardware timestamp with the corresponding data message, and storing the associated data in a buffer area in the chip; and 5, generating standardized timestamp information, and outputting the standardized timestamp information through a chip interface. And high-precision time synchronization and timestamp generation are realized.

The invention discloses a single-chip microcomputer hierarchical dormancy control method based on dynamic power consumption prediction, and relates to the technical field of single-chip microcomputer low power consumption control, and the method specifically comprises the steps: building a mapping relation between a load current and a clock frequency; setting a dynamic dormancy threshold value; constructing a dynamic power consumption prediction model; a dormancy strategy is designed, module-level power consumption management and single-chip microcomputer function-based power consumption management are adopted, the callable frequency or the maximum operation duration of each function is distributed according to task priorities and battery residual energy consumption, and single-chip microcomputer peripherals are triggered through events and are independently awakened; and executing the sleep strategy, automatically awakening the single chip microcomputer according to a preset awakening condition, and realizing abnormity positioning and processing based on threshold comparison and power consumption monitoring in the process of executing the sleep strategy. According to the invention, module-level power consumption management and single-chip microcomputer function-based power consumption management are realized, the limitation of traditional global dormancy is broken, the need of overall reset during wakeup is avoided, and the response speed is improved while the energy consumption is reduced.

A circuit system includes a circuit board including a plurality of integrated circuit (IC) chips. The circuit board is configured to be immersed in a two-phase cooling fluid. The circuit system includes a controller. The controller is configured to, in a control process: obtain temperature data indicative of respective internal temperatures of the plurality of IC chips, predict respective future internal temperatures of the plurality of IC chips based on the respective internal temperatures, and adjust clock frequencies and power supply voltages of the plurality of the IC chips such that the predicted respective future internal temperatures are within a target temperature range. A clock frequency of a first IC chip of the plurality of IC chips is adjusted to be different from a clock frequency of a second IC chip of the plurality of IC chips.

The invention relates to the technical field of chip testing, and discloses a clock reset system-level verification method and device based on general verification methodology, and the method comprises the steps: firstly analyzing a clock topological relation defined in a system control unit architecture document, and generating a clock reset information table; on the basis of the information table, an executable verification environment component and a virtual interface component are automatically generated through a script, the verification environment component comprises an excitation forwarding and processing component and can generate clock and reset signals matched with framework definition, and the virtual interface component can generate actual clock and reset waveforms; and finally, constructing a verification platform based on the components, calling the excitation sequence in the parameterized test sequence library, and carrying out system-level clock reset verification on the digital chip. And meanwhile, the parameterized test sequence library supports flexible adjustment of a verification scene and ensures that a test case fits a clock frequency defined by an architecture document, and a reset mechanism can improve the efficiency, accuracy and reliability of digital chip clock reset system-level verification.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

The invention relates to a method for realizing multi-channel ADC (Analog to Digital Converter) data synchronization processing based on an FPGA (Field Programmable Gate Array), which comprises the following steps that: the FPGA receives a clock frequency generated by an external clock generator and takes the clock frequency as a working clock of the FPGA; a plurality of groups of same-frequency clocks and same-phase clocks are generated in the FPGA and are respectively used as working clocks of the ADC chips; the FPGA receives sampling data of each ADC, an enable signal is set, and when the enable signal is effective, digital down-conversion, decimation filtering and FIR filtering are carried out on each sampling data; and after FIR filtering is completed, another enable signal ENend is generated, and data are further stored or transmitted to an upper computer. According to the method and the device for realizing the multi-channel ADC data synchronous processing based on the FPGA, the processor and the computer readable storage medium thereof, synchronous start and stop of the processing flow are controlled through the enable signals ENstart and ENend, synchronous processing of the multi-channel ADC data is ensured, accuracy and effectiveness are improved, and the method and the device have a wide application range.

According to the task scheduling and resource management system and method provided by the invention, full-link automatic management from peripheral event triggering to resource dynamic allocation and recovery is realized through close cooperation of the peripheral collaborative network, the dynamic power management module, the task scheduling module, the self-adaptive clock module and the exception monitoring unit. Compared with the prior art, the system not only can perform hardware-level scheduling in real time according to task priorities and system loads, but also can improve energy efficiency through regionalized power supply and clock frequency adjustment, supports rapid recovery and storage of task contexts, has a perfect fault monitoring and isolation mechanism, and is high in practicability. Therefore, the real-time performance, the energy consumption efficiency and the operation reliability of the system are obviously improved.

The invention provides a time synchronization method based on an IEEE 1588 protocol, and relates to the technical field of time synchronization. Comprising the following steps: firstly, establishing a network-based master-slave clock model to characterize a clock frequency; secondly, acquiring a timestamp set of master and slave clocks of the current round, and calculating average transmission delay and time offset; thirdly, a clock synchronization equation of Kalman filtering is built based on a clock model, time offset and drift serve as input, an optimal time offset value is obtained, and a local clock is adjusted to complete synchronization of the current round. Then, a new timestamp set is obtained for the next round, the average transmission delay and the time offset are calculated, and the optimal offset value is determined through a Kalman filtering equation; meanwhile, the number of cycles is calculated according to the offset value and the receiving timestamp, and frequency compensation is carried out on the slave clock. According to the invention, the problem of low time synchronization precision in the prior art is effectively solved.

The invention relates to a method for awakening electronic equipment, which comprises the following steps that: when the electronic equipment is in a dormant state, a subsystem receives a first awakening event; in response to determining that the first wake-up event belongs to the subsystem external wake-up event, the subsystem sets the clock frequency of a first sub-module of the subsystem from a current first frequency value to a second frequency value, the first frequency value is the running frequency set when the subsystem is in a dormant state, and the second frequency value is the highest running frequency allowed by the subsystem; the first sub-module of the subsystem is configured to control the temporary operation frequency of the subsystem; the subsystem analyzes the first wake-up event and sends a related first message to the main system; in response to a response to the first message returned by the main system, the subsystem sets the clock frequency of the first sub-module as a first frequency value; and in response to determining that all clock frequencies of the first sub-module and other sub-modules of the subsystem are set as the first frequency value, the subsystem enters a dormant state.

The invention provides a processor chip with adjustable power consumption, which is integrated with a plurality of functional cores and a plurality of routers, all the routers are mutually connected to form an on-chip network, all the functional cores are mounted on the on-chip network to realize mutual communication, and the chip further comprises a power consumption management module, all the functional cores and all the routers are configured to be subjected to clock frequency adjustment by a power consumption management module, and the power consumption management module is used for adjusting the clock frequency of the processor chip based on a received frequency raising request from the functional cores and / or the routers; the clock frequency of the processor chip is adjusted based on a self-configured adjusting mechanism; wherein the power consumption management module is configured to support unified adjustment of clock frequencies of all the functional cores and / or all the routers, and independently adjust the clock frequencies of each functional core and each router; and the power consumption management module is mounted on the network-on-chip to realize communication with each router and each functional core.

The invention provides a universal serial bus (USB) 2.0 host speed reduction bridge based on bidirectional protocol handshake and a prototype verification or hardware simulation acceleration platform, which are characterized in that a slow-speed side module runs at a slow clock frequency, is responsible for realizing a protocol layer of a USB protocol and a physical link layer function of the USB protocol, and communicates with a USB2.0 host controller in a chip design (DUT) to be tested; the original speed side module works under the original clock frequency, logic of a protocol layer of a USB protocol and a physical link layer of the USB protocol is achieved, communication with an external real USB2.0 slave end device is achieved through a USB2.0 PHY, data caching and synchronization are achieved through a data caching RAM, and the bridge control module overall plans the whole situation and accurately regulates and controls independent handshake of the USB2.0 protocol layers on the two sides under the original clock frequency. Through bidirectional protocol handshake on the two sides of the speed reduction bridge, data communication between a low-speed to-be-tested chip design (DUT) in a chip prototype verification platform and external standard-speed real USB slave equipment is achieved through the speed reduction bridge.

The invention relates to the field of precise motion control, in particular to a precise motion control method and system for a multi-axis linkage direct-drive-force tool tower crane. Comprising the following steps: acquiring a processing track, dispersing the processing track into a plurality of spatial motion units, and determining a target displacement for each motion axis; receiving a completion signal; and after determining that the motion axis participating in the current space motion unit completes the corresponding target displacement according to the completion signal, obtaining the completion time of each motion axis, and issuing the target displacement corresponding to the next space motion unit to each motion axis by taking the completion time of the motion axis with the longest completion time as a time reference. Therefore, each motion shaft is started to move the next space motion unit. The technical problems that the machining precision is reduced and the product quality is unqualified due to clock frequency drift and movement shaft synchronization deviation accumulation caused by gradual change of microcosmic physical characteristics in a system of a multi-shaft linkage direct-driving-force tool tower crane are solved.

The invention discloses an external plug-in card clock switching control method and device, a controller and a storage medium, and relates to the technical field of computer hardware, and the method comprises the steps: in the operation process of a storage device, collecting the operation information of an external plug-in card in real time, calculating the real-time rate of a link, and dynamically detecting the output state of a clock source; high-precision matching between the clock frequency and the link requirement is achieved, and if the relative deviation between the link clock rate and the link real-time rate exceeds the first preset threshold value, the clock switching instruction is sent to the clock source output switching module so that the clock source output switching module can be switched to the target clock source. Therefore, it is ensured that the relative deviation between the link real-time rate and the link clock rate output by the target clock source is within the first preset threshold value, waste of clock resources is reduced, and the overall energy consumption of the storage device is reduced.

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

The invention provides a clock frequency adjusting method and device, an image processor, equipment and a medium, and relates to the technical field of computers. The method comprises the following steps: receiving current counting information corresponding to at least one preset monitoring event related to the running state of the GPU; constructing a feature vector based on the current counting information; the feature vector is input into a pre-trained prediction model, the load sudden increase probability is obtained, the prediction model is obtained through training based on historical counting information corresponding to a preset monitoring event and load sudden increase labeling data, and the load sudden increase probability represents the probability that the operation load of the GPU is to be suddenly increased; and adjusting the current clock frequency of the GPU based on the load sudden increase probability. According to the scheme, the feature vector can be constructed based on the monitoring event counting information, the load sudden increase probability is obtained through the prediction model, dynamic adjustment of the clock frequency is achieved, and then the response efficiency and the adjustment accuracy of GPU clock frequency adjustment are improved.

Embodiments pertain to reducing power consumption in a computing system comprising one or more deterministic processors. A controller generates a plurality of control signals for a voltage regulator to regulate a supply voltage of a respective one of the one or more deterministic processors. A power management module determines an initial profile for power consumption and performance of an algorithm executed on the respective deterministic processor having an initial value for the supply voltage and an initial value for a clock frequency. The power management module further determines a target profile for power consumption and performance of the algorithm executed on the respective deterministic processor. The controller modifies the plurality of control signals based on the initial profile and the target profile. The respective deterministic processor executes the algorithm while the supply voltage is dynamically modified by the voltage regulator based on the modified plurality of control signals.

The invention relates to the technical field of integrated circuits, and provides a dynamic voltage frequency configuration method, device, equipment and program product of a chip, and the method comprises the steps: for each chip in a sample set comprising a plurality of chips, determining a performance index based on a chip parameter and a preset test frequency; comparing the performance index of each chip with a preset limit value to determine the number of chips passing the test; based on the number of the chips passing the test and the total number of the chips in the sample set, determining the actual yield under the preset test frequency; comparing the actual yield with a target yield, and iteratively adjusting the preset test frequency until the target yield is met so as to obtain an effective clock frequency; a voltage frequency table is generated based on the effective clock frequency and the corresponding voltage. According to the method, the relationship between the effective clock frequency and the yield is fully reflected, the generated voltage frequency table can provide the optimal working parameter combination for the chip under the condition of ensuring the yield, and the performance and efficiency of chip design are improved.

The embodiment of the invention relates to the technical field of clock synchronization, and discloses a clock synchronization method and system, electronic equipment and a storage medium. The clock synchronization method comprises the steps that clock frequencies of a master chip and a slave chip are synchronized, and the master chip and the slave chip interact through an inter-chip communication channel; determining a clock calibration value, wherein the clock calibration value is used for representing a clock difference between the master chip and the slave chip; and according to the clock calibration value, carrying out clock calibration so as to synchronize the clocks of the master chip and the slave chip. The synchronization precision of the master chip and the slave chip is improved at least while additional interfaces are not introduced to the master chip and the slave chip.

The invention belongs to the technical field of clock synchronization. The invention provides an unmanned aerial vehicle communication clock synchronization compensation device and method based on GPS / Beidou second pulse. According to the embodiment of the invention, a second pulse signal and a UTC timestamp are obtained; after several rounds of counting and sliding filtering are carried out on the second pulse signal interval time, the actual frequency and nominal value deviation of the crystal oscillator is calculated; the actual frequency and nominal value deviation of the crystal oscillator are stored, and the crystal oscillator drift model is updated; and dynamically adjusting the output clock frequency according to the nominal value deviation, and compensating the crystal oscillator error to obtain a compensated clock signal. And the second pulse loss duration is monitored, and the crystal oscillator drift model is updated according to the nominal value deviation in the storage module so as to predict the future clock deviation. And within the period of validity of the pulse per second, the clock synchronization error is reduced to improve the synchronization precision. And under the condition of GPS / Beidou, the synchronization precision can be maintained longer than that of a single GPS / Beidou method. And frequency offset automatic compensation along with temperature change can be realized.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

The invention relates to the technical field of audio and video decoding, and relates to a low-power-consumption audio and video decoding system and method based on a plug-in product. The system comprises a main control unit which integrates a multi-core processor and a task scheduler and is used for distributing decoding tasks in real time and supporting dynamic frequency adjustment; the plug-in decoding module is connected with the main control unit through an expansion interface; the intelligent power consumption management module is connected with the main control unit and the plug-in decoding module, comprises a load prediction algorithm and a self-adaptive voltage regulation unit, and is used for dynamically regulating the working voltage and the clock frequency of the decoding module according to the task load; and the power supply management module supplies power to the main control unit, the plug-in decoding module and the intelligent power consumption management module. Independent upgrading of the decoder is realized through plug-in hardware modular design, and the problems of high energy consumption, low expansibility, large synchronization delay and the like in a traditional scheme are solved by combining an intelligent task allocation strategy and a self-adaptive voltage regulation technology.

A transmitter at a first location transmits the message at a symbol rate of the reference clock using a first carrier, whose phase is locked to a phase of the reference clock and whose frequency is a first integer times a frequency of the reference clock. It also transmits the message at the symbol rate of the reference clock using a second carrier, whose phase is locked to the phase of the reference clock and whose frequency is a second integer times the frequency of the reference clock. The second integer is unequal to the first integer. A receiver at a second location receives the message at the first carrier and at the second carrier, and accurately determines a time of a first phase difference between the first carrier and the second carrier. It determines a time of receiving the message from the time of the first phase difference.

The invention discloses a system reference clock frequency accuracy automatic calibration circuit and a calibration method thereof, and belongs to the technical field of frequency sources, the calibration circuit comprises a first crystal oscillator, a first power divider, a second power divider, a second crystal oscillator, an analog switch, a radio frequency switch, a detector, a comparator, an FPGA controller, a digital analog converter, an operational amplifier and a temperature sensor. When an external high-precision reference clock is accessed, the FPGA controller automatically switches a frequency measurement reference, performs high-precision frequency measurement on a 100MHz signal output by the first crystal oscillator, and judges whether calibration is needed or not according to frequency offset; if calibration is needed, the output voltage of the digital-to-analog converter is adjusted, the Vc end of the first crystal oscillator is controlled after operational amplification, and frequency closed-loop adjustment is achieved. According to the method, the crystal oscillator does not need to be disassembled, calibration is rapidly completed on site, and system availability and long-term frequency stability are remarkably improved.

The invention provides a chip testing method and device, and belongs to the technical field of chip testing. The method comprises the steps that an intermediate clock with the frequency the same as that of an input channel-associated clock in a test excitation signal is generated through a high-frequency clock signal, and the frequency of the high-frequency clock signal is larger than that of the input channel-associated clock; adjusting the phase of the intermediate clock according to the time sequence parameter of each tested chip, and generating a phase correction associated clock; and replacing the input associated clock based on the phase correction associated clock to update the test excitation signal so as to test each tested chip by using the updated test excitation signal. Independent time sequence compensation of each chip is achieved through high-frequency signal dynamic high-precision phase adjustment, the limitation of a traditional single time sequence parameter is broken through, and flexible consideration of the test rate and the test number is achieved. From the aspect of deployment, the design process and the file format of the original test system do not need to be modified, the compatibility is good, the universality and the deployment efficiency are improved, and the deployment cost is reduced.

The invention relates to the technical field of space optical communication and distance measurement, in particular to a distance measurement method and device based on a non-equal sampling digital phase discriminator and a storage medium. A non-equal sampling method is used for carrying out sampling and phase discrimination on data bit clocks on two asynchronous clock domains for sending and receiving GTX, and hardware resources required for processing all use an FPGA internal digital logic block; the clock processing rate and the GTX sending and receiving clock rate are kept in a non-integer multiple relationship, so that the measurement precision of the phase difference between the two clock rates is improved, and the purpose of improving the laser ranging precision on the basis of simplifying the hardware design of a ranging system is achieved.

A clock circuit, a receiver, and a passive optical communication network system are disclosed. The clock circuit is applied to a receiver in a passive optical communication network and is configured to adjust the clock frequency of an output clock signal based on a transmission protocol, the clock circuit comprises at least one clock path and a frequency divider, and the at least one clock path comprises a first clock path; wherein the first clock path receives a reference clock signal from the first phase-locked loop circuit and a control signal from the clock data recovery circuit, and interpolates a conversion signal of the reference clock signal by using the reference clock signal so as to output a multi-phase clock signal; and the frequency divider receives the multi-phase clock signal and performs frequency division on the multi-phase clock signal based on a preset frequency division value, and the preset frequency division value is determined based on a transmission protocol. The clock circuit can be compatible with fast clock switching schemes of data rates of different PON protocols, so that the adaptability and the locking performance of a receiver in a burst mode are improved.

To provide a battery management system capable of performing synchronization of a measurement timing of a battery in a plurality of devices as accurately as possible.SOLUTION: A device 10...1N includes an oscillator 29 that generates a second clock whose frequency can be controlled, and a time information generation part 30 generates second time information from the second clock generated by the oscillator 29. The device 10...1N generates a measurement timing of a battery from the second time information. When receiving a synchronization command from a controller 52, the device 10...1N compares the received first time information with the second time information, and controls the frequency of the oscillator 29 so as to eliminate the time difference from the compared difference. The device 10...1N controls the frequency of the second clock of the oscillator 29 to approach the frequency of the first clock of the controller 52.SELECTED DRAWING: Figure 1

The invention discloses a clock processing method and device, electronic equipment, a storage medium and a program product, and relates to the technical field of communication, and the method comprises the steps: building a cross-domain clock based on a main clock in a digital circuit; setting a first delay constraint for the cross-domain clock based on a preset delay threshold; the Gray code path is determined in the time sequence path corresponding to the cross-domain clock, and the first delay constraint is adjusted based on the clock frequency of the cross-domain clock to obtain the second delay constraint, so that the problems that the requirements of different types of time sequence paths on path constraints are often different, and if the constraints are not distinguished when the time sequence paths are designed, the time sequence paths cannot be designed are solved. The technical problem that the power consumption of the digital circuit is increased due to the fact that a design tool may add more buffers on a path or enhance the driving capability of the buffers is solved, and the technical effect of reducing the power consumption of the digital circuit to a certain extent on the premise of ensuring the time sequence requirement of the cross-clock domain is achieved.

The invention provides a 200GE service data transmission method based on 224G high-speed SerDes, a chip and a communication system, and the method comprises the steps that a PCS sending module carries out PCS sending processing on obtained upstream data to obtain first PCS data; the PCS sending module sends first PCS data to the PMA sending module through the rate increasing module according to the first PCS clock rate and the first PCS data bit width; the rate increasing module determines first clock information according to the first PMA data bit width, the first PMA clock rate, the first PCS clock rate, the first PCS data bit width and the set bandwidth so as to increase the first PCS clock rate; the PCS sending module sends first PCS data according to the first PMA data bit width and the improved first PCS clock rate; the PMA sending module processes the first PCS data and sends the first serial data. The method can be applied to the fields of internet access and related services, the alignment mark insertion process is avoided so as to improve the sending rate of the PCS layer, and the PMA state frame is introduced so as to accelerate link convergence and improve link stability.

The invention discloses an SERDES verification method and device, and the method comprises the steps: obtaining a protocol type and a configuration mode supported by a to-be-tested SERDES, generating a first compiling simulation script according to the protocol type, and enabling the script to comprise the clock frequency, the data rate, the parameter configuration of a coding mode, the generation rule of simulation excitation, and a result output path; based on the test requirement and the protocol type, a test top layer file and a file list are determined, and the file list comprises paths of the to-be-tested design file and the test excitation file; calling a script, executing first compiling simulation, and generating a waveform file and a log file; switching to a second protocol type, updating the test top layer file and the file list, and generating a second compiling simulation script; executing secondary compiling simulation to generate a waveform file and a log file corresponding to the second protocol; the log file is analyzed, the bit error rate, the function coverage rate and the time sequence violation are counted, and a comprehensive test report is generated. The method can accelerate the verification speed and reduce the development time.