126 results about "Decoder architecture" patented technology

A method for compressing / decompressing data, comprising the steps of translating a first representation of data to a second representation of the data and translating the second representation of the data to a third representation of the data.

A method and apparatus for providing plug-in media decoders. Embodiments provide a "plug-in" decoder architecture that allows software decoders to be transparently downloaded, along with media data. User applications are able to support new media types as long as the corresponding plug-in decoder is available with the media data. Persistent storage requirements are decreased because the downloaded decoder is transient, existing in application memory for the duration of execution of the user application. The architecture also supports use of plug-in decoders already installed in the user computer. One embodiment is implemented with object-based class files executed in a virtual machine to form a media application. A media data type is determined from incoming media data, and used to generate a class name for a corresponding codec (coder-decoder) object. A class path vector is searched, including the source location of the incoming media data, to determine the location of the codec class file for the given class name. When the desired codec class file is located, the virtual machine's class loader loads the class file for integration into the media application. If the codec class file is located across the network at the source location of the media data; the class loader downloads the codec class file from the network. Once the class file is loaded into the virtual machine, an instance of the codec class is created within the media application to decode / decompress the media data as appropriate for the media data type.

A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

A method and apparatus for providing plug-in media decoders. Embodiments provide a "plug-in" decoder architecture that allows software decoders to be transparently downloaded, along with media data. User applications are able to support new media types as long as the corresponding plug-in decoder is available with the media data. Persistent storage requirements are decreased because the downloaded decoder is transient, existing in application memory for the duration of execution of the user application. The architecture also supports use of plug-in decoders already installed in the user computer. One embodiment is implemented with object-based class files executed in a virtual machine to form a media application. A media data type is determined from incoming media data, and used to generate a class name for a corresponding codec (coder-decoder) object. A class path vector is searched, including the source location of the incoming media data, to determine the location of the codec class file for the given class name. When the desired codec class file is located, the virtual machine's class loader loads the class file for integration into the media application. If the codec class file is located across the network at the source location of the media data; the class loader downloads the codec class file from the network. Once the class file is loaded into the virtual machine, an instance of the codec class is created within the media application to decode / decompress the media data as appropriate for the media data type.

The present invention discloses a single unified decoder for performing both convolutional decoding and turbo decoding in the one architecture. The unified decoder can be partitioned dynamically to perform required decoding operations on varying numbers of data streams at different throughput rates. It also supports simultaneous decoding of voice (convolutional decoding) and data (turbo decoding) streams. This invention forms the basis of a decoder that can decode all of the standards for TDMA, IS-95, GSM, GPRS, EDGE, UMTS, and CDMA2000. Processors are stacked together and interconnected so that they can perform separately as separate decoders or in harmony as a single high speed decoder. The unified decoder architecture can support multiple data streams and multiple voice streams simultaneously. Furthermore, the decoder can be dynamically partitioned as required to decode voice streams for different standards.

A turbo decoder having two modes of operation decodes received information as per an N-state Radix-K trellis where N and K are integers equal to 1 or greater. The turbo decoder uses an in-line addressing technique that allows it to operate as a Serial Convolutional Code decoder in the first mode of operation and a Parallel Convolutional Code decoder in the second mode of operation. The decoder uses an in line addressing technique that allows it to use the same block of memory to store and retrieve states of the trellis as it processes received information. The turbo decoder can also operate as per an N-state Radix-K trellis where N is an integer equal to 2 or greater and K is an integer equal to 4 or greater.

Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

A concatenated equalizer / trellis decoding system for use in processing a High Definition Television signal. The re-encoded trellis decoder output, rather than the equalizer output, is used as an input to the feedback filter of the decision feedback equalizer. Hard or soft decision trellis decoding may be applied. In order to account for the latency associated with trellis decoding and the presence of twelve interleaved decoders, feedback from the trellis decoder to the equalizer is performed by replicating the trellis decoder and equalizer hardware in a module that can be cascaded in as many stages as needed to achieve the desired balance between complexity and performance. The present system offers an improvement of between 0.6 and 1.9 decibels. Cascading of two modules is usually sufficient to achieve most of the potential performance improvement.