60results about "Error correction/detection using convolutional codes" patented technology

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

This communication device may apply convolution precoding to a bit sequence, polar-encode the convolution-precoded bit sequence, and transmit same. When the size of a polar coder for convolution precoding is 2N, pre-determined values are mapped to last m bit indexes from among first N bit indexes in a bit sequence having the length of 2N, which is an input for the convolution precoding, and bit values of an information block are mapped to K bit indexes from among remaining (2N-m) bit indexes.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G and 6G. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality XR service or another low-delay service.

Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.

The present disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate than a 4G communication system such as LTE. An encoding method performed by a transmission device of a communication system according to an embodiment of the present disclosure may comprise the steps of: identifying at least one parameter related to a convolutional code associated with a polarization-adjusted convolutional (PAC) code; on the basis of the at least one parameter, identifying a parity check matrix for an input binary vector of a polar code associated with the PAC code; on the basis of the parity check matrix, encoding a polar code concatenated with an outer code; and transmitting a codeword vector generated on the basis of the encoding.

Methods, systems, and devices for wireless communications are described. A first device may transmit, to a second device, a bit sequence encoded with a convolutional encoder associated with a constraint length of four, five, six, or seven, and associated with a subset of polynomials of a polynomial set, wherein the polynomial set is selected from a group of polynomial sets, expressed with octal values, consisting of polynomial sets described herein. Additional aspects of the present disclosure are directed to techniques and methodologies used to search for polynomial sets that are usable for convolutional encoder-based wireless communications.

A method for encoding data, a method for decoding data, an encoder, and a decoder are disclosed. The decoder is designed to determine a convolutional coded message from two or more symbol sequences, each symbol sequence being associated with a different bit sequence according to an association rule and the convolutional coded message corresponding to a bit sequence associated with all symbol sequences according to a common association rule, and to decode the convolutional coded message.

The application discloses a convolution code parallel pipeline decoding acceleration system and method based on a memory-compute integrated architecture, comprising: a global data scheduling module, which is used for slicing convolution code data from a magnetic tape storage device according to a set rule and scheduling the data through a multi-level cache mechanism; a memory-compute integrated unit array, which is used for storing data tiles and intermediate results output from the global data scheduling module and performing convolution operation, path metric calculation and surviving path selection through a reconfigurable computing unit; a parallel pipeline controller, which is used for dynamically allocating decoding tasks and controlling the pipeline beat of the memory-compute integrated unit array; an adaptive resource configuration module, which is used for monitoring the system load in real time and dynamically adjusting data distribution strategies and computing resource scheduling; and a check and error correction unit, which is used for checking and correcting the decoding results output from the memory-compute integrated unit array and then outputting the results; the decoding acceleration system and method realize efficient and low-delay convolution code decoding.

A wireless communications device includes a receiver having a phase detector configured to extract frequency offset and provide a corresponding error signal generated based on a baseband version of a received radio frequency signal and an expected transmitted data signal. The receiver has a phase-locked loop configured to generate an error correction signal based on a phase of the error signal and a predicted instantaneous phase of the error signal. The receiver has a correction circuit configured to provide a corrected baseband version of the received radio frequency signal based on the baseband version of the received radio frequency signal and the error correction signal. The receiver may have a re-encoding-based processing circuit configured to provide the expected transmitted data signal based on a preliminarily decoded symbol.

The invention discloses a parallel stepped convolutional code space coupling coding and decoding (PSCBCC) method and device, belongs to the technical field of channel coding, and is suitable for a large-bandwidth communication scene. According to the method, a frame of data is divided into multiple groups of sub-data, parallel convolutional coding of three paths of input of current sub-data, interleaved previous sub-data and an interleaved previous check sequence is realized by utilizing a parallel coding unit, a current check sequence is generated, and the sub-data and the check sequence are respectively reserved to different subsequent moments to form asymmetric coupling; and during decoding, a parallel decoding unit is matched with a coding structure, and a plurality of groups of log-likelihood ratios are input to realize iterative updating. The throughput rate is improved through parallel processing, the bit error rate performance is enhanced through asymmetric coupling, multi-code-rate adaptation is supported, and the performance is superior to that of existing BCC and 4G / 5G standard codes.

A wireless device may receive a first code block of one or more code blocks associated with a transport block for the wireless device. The wireless device may output, using a neural network model associated with the wireless device, a set of low-density parity-check (LDPC) quantization values for a set of iterations of an LDPC decoding procedure for the first code block. In some examples, the set of LDPC quantization values may include respective LDPC quantization values for respective iterations of the set of iterations. The wireless device may perform one or more iterations of the LDPC decoding procedure for the first code block in accordance with one or more LDPC quantization values of the set of LDPC quantization values output using the neural network model.

To provide a method and apparatus for communicating a synchronization signal (SS) block that includes an SS block index in a physical broadcast channel (PBCH) payload.SOLUTION: In a wireless communication system, a UE receives, at different times separated by a time increment, a first synchronization signal (SS) block including a first codeword and a second SS block including a second codeword, each based at least in part on linear encoding of a PBCH payload. The UE determines, based at least in part on the time increment, one or more hypotheses, including a correct hypothesis, of combined decoding metrics for the first codeword and the second codeword, and decodes the first codeword based on each thereof. The UE determines the first codeword based at least in part on an error detection procedure such as CRC verification performed when decoding the first codeword based at least in part on the correct hypothesis.SELECTED DRAWING: Figure 4

An apparatus configured to apply a convolutional precoder with a time-varying polynomial to an information vector to generate a precoded vector, wherein coefficients of the time-varying polynomial are generated by a pseudo-random number generator (PRNG) using a radio network temporary identifier (RNTI) as an initialization seed, generate a polarization-adjusted convolution (PAC) codeword based on the precoded vector and transmit the PAC codeword.

Aspects of the disclosure provide for methods and systems for Sub-codebook based Trellis Coded Quantization for CSI Feedback. An aspect of the disclosure provides method executed by a receiver. The method includes receiving a signal from a transmitter, via a communication channel between the receiver and the transmitter. The method further includes estimating parameters associated with the channel based on the received signal. The method further includes obtaining phase information from the estimated parameters. The method further includes applying a trellis coded quantization (TCQ) scheme to the obtained phase information by mapping each sub-codebook index of a set of sub-codebook indices to output bits of each trellis branch making the distance between sub-codebooks maximally equal. The method further includes transmitting a channel state information (CSI) measurement feedback to the transmitter, the CSI measurement feedback based on the TCQ scheme and comprising one or more of: a beginning state, input bits to the TCQ scheme, and a sub-codebook index.

The invention relates to the technical field of channel coding and decoding. The invention discloses a pre-transformation method and device of a polarization adjustment convolutional code, a terminal and a storage medium, which can reduce the computation complexity of optimizing a convolution multiform and reduce the optimization difficulty of code redistribution of a PAC code. The pre-transformation method of the polarization adjustment convolutional code comprises the following steps: setting a first convolution formula and a plurality of to-be-processed formulas; a tree structure modeling mode is adopted to carry out convolution multi-mode modeling processing on the first convolution formula and the multiple to-be-processed formulas to obtain a target convolution polynomial of the polarization adjustment convolution code, the tree structure modeling mode sets a coefficient in a target to-be-processed formula as 0 or 1, and when the coefficient of the target to-be-processed formula is 0, the polarization adjustment convolution code is obtained. The to-be-processed formula corresponding to the target to-be-processed formula is not used for constructing the target convolutional polynomial, and the target to-be-processed formula is any to-be-processed formula in the multiple to-be-processed formulas.

In accordance with implementations, an apparatus obtains a first bit sequence of a first sequence length. The first bit sequence comprises a first portion of a first portion length and a second portion. The apparatus obtains a second bit sequence of a second sequence length generated from the first bit sequence. The apparatus encodes an input sequence to generate an encoded sequence. An ordering of the input sequence comprises the second portion, the second bit sequence, and the first portion. An encoder for the encoding comprises a state. An initial value of the state before the encoding is set according to the first portion. The apparatus transmits the encoded sequence.

The invention discloses a storage implementation method of a convolutional LDPC decoder without read-write conflicts, and belongs to the technical field of channel coding and decoding. In the prior art, a register-based scheme causes huge resource consumption due to network switching; memory-based schemes are faced with severe memory access conflicts. According to the method, a matrix-hardware collaborative design is adopted, a series of non-zero element position constraints are added in a random construction algorithm to generate a check matrix, and a parallel access process of a non-switched network is executed based on the matrix. In the process, during reading, an invalid path reads a default address to avoid using a read selection network; during writing, write enabling is controlled to avoid using a write routing network; and cross-level transmission conflicts are solved under a unified storage architecture through combinational logic. On the premise of ensuring high throughput and excellent error correction performance, storage access conflicts and a complex data exchange network are solved from the architecture level, and hardware resource consumption is remarkably reduced.

A device includes a receiver coupled with a link and including control logic, the control logic to receive data bits corresponding to a first set of data. The control logic may also perform a forward error correction (FEC) operation on the data bits to generate an error location responsive to receiving the data bits. The control logic may also perform a cyclic redundancy check (CRC) operation on the data bits to generate a first CRC value, wherein the CRC operation and FEC operation are performed concurrently. The control logic may determine a second CRC value after performing the FEC operation, the second CRC value based on the error location and generate a third CRC value corresponding to the first set of data responsive to performing the CRC operation and determining the second CRC value.

The application discloses a convolutional decoder, a decoding method and an electronic device, relates to the technical field of communication, and is used for reducing time overhead of convolutional code decoding. The application is used for decoding an encoded sequence, the encoded sequence is divided into P first sub-sequences, tail sequences of the P first sub-sequences are P second sub-sequences, and the convolutional decoder comprises the following steps: for first round decoding, P Viterbi decoders decode the P second sub-sequences respectively, and update cumulative score vectors of the P second sub-sequences; from second round decoding, a pth Viterbi decoder starts to perform cyclic decoding on the encoded sequence from a starting position of a pth first sub-sequence, and update cumulative score vectors of the P first sub-sequences; P comparators compare the cumulative score vectors of two sub-sequences with the same ending position in the last two rounds of decoding, and if the maximum probability state transition paths of the two sub-sequences with the same ending position are the same, the decoding sequence of the maximum probability state transition path is output.

Communication systems that utilize receivers for decoding short block length messages are disclosed. In many embodiments, the receiver includes an antenna for receiving encoded data, via RF signals, a demodulator for obtaining symbols from the RF signal, a demapper for generating symbol metrics, and a parallel list decoder. In several embodiments, the parallel list decoder processes multiple trellis stages simultaneously, enabling efficient decoding of the symbol metrics to obtain received, bits. In certain embodiments, the parallel list decoder divides the decoding trellis into segments, processes these segments independently, and combines them pairwise to form new segments. This parallel processing approach can allow for reduced decoding latency and improved efficiency in handling short block length messages. making it particularly suitable for applications requiring rapid data exchange and low-latency communication.

Methods, systems, and devices for wireless communications are described. A transmitting device may support shaping of bits in block encoding schemes and a probabilistic shaping framework to generate shaped bits that include both information bits and shaping bits, without conveying extra information (e.g., in addition to the shaped bits) to a receiving device. The transmitter may use a decoder such as a polar decoder (e.g., a modem configured for both coding and decoding) to determine a set of shaping bits based on the information bits. The transmitting deice may also map information bits to frozen bit locations of the polar code, and the shaping bits to information bit locations of the polar, such that the encoded (e. g., shaped) bits from the polar encoder satisfy a target probability distribution.

Techniques pertaining to binary convolutional code (BCC) low coding rate designs for next generation wireless local area networks (WLANs) are described. A processor of an apparatus (e.g., station (STA)) receives a string of input bits and codes the string of input bits. In coding the input bits, the processor encodes the input bits by a BCC encoder of the processor using a base code rate. The processor also repeats an output of the BCC encoder by a repetition circuit of the processor to result in an effective coding rate of the input bits that is lower than the base code rate.

An apparatus (20) includes a compressor (40), a memory (24), a decompressor (32) and a decoder (36). The compressor is configured to receive soft metrics of bits of a codeword of an Error Correction Code (ECC), and to convert a group of the soft metrics, which includes two or more soft metrics of bits associated with the same symbol, into a compressed representation (28). The memory is configured to store the compressed representation. The decompressor is configured to read the compressed representation from the memory and to decompress the compressed representation so as to produce decompressed soft metrics. The decoder is configured to decode the codeword using the decompressed soft metrics.

The application discloses a PAC code decoding method based on path splitting times and belongs to the field of wireless communication channel coding.The application comprises the following steps: obtaining an output value corresponding to a to-be-decoded bit from a channel and initializing a current decoding bit index;judging whether the current decoding bit index is in an index set;if yes, traversing a to-be-selected path list, performing convolution transformation, path metric value calculation and partial sum value calculation on each path, otherwise, performing a to-be-selected path list expansion operation;outputting a path arranged at the forefront in the to-be-selected path list as a decoding result and ending the decoding.The application can effectively improve the PAC code decoding performance and reduce the decoding time delay.

The present application relates to the technical field of communications. Provided in the embodiments of the present application are a coding method, a decoding method, a communication apparatus and a storage medium, which are used for reducing the convolutional coding complexity. The coding method specifically comprises: first, acquiring an information bit sequence; according to T component code generation polynomials, performing convolutional coding on the information bit sequence, so as to obtain T component code output bit sequences, T being an integer greater than 1; performing sub-block interleaving on an i-th component code output bit sequence, so as to obtain a sub-block interleaved output sequence, i being a non-negative integer less than T; and, according to the sub-block interleaved output sequence and the other component code output bit sequences excepting the i-th component code output bit sequence among the T component code output bit sequences, determining a coded bit sequence.

A method for encoding data, a method for decoding data, an encoder, and a decoder are shown. The decoder is configured to determine a convolutionally encoded message consisting of two or more symbol strings, where each of the symbol strings is assigned to different bit sequences according to an assignment rule, and the convolutionally encoded message corresponds to a bit sequence assigned to all symbol strings according to the common assignment rule, and to decode the convolutionally encoded message.

The invention discloses a method for preventing tampering of electric power internet of things sensing data of cascaded codes, and belongs to the field of data processing. According to the method, the characteristic advantages of cascade connection of the RS codes and the convolutional codes are fused, the grading strategy of triggering the RS codes on demand is adopted, the optimized convolutional decoding algorithm is matched, and on the premise that calculation and transmission expenses are not remarkably increased, the requirement of an electric power internet-of-things scene for real-time transmission and the core target of data reliability are considered. Meanwhile, the improved Viterbi algorithm is used, values of other branch metrics are rapidly calculated through symmetry and a logic relation, and therefore the convolutional code decoding efficiency is improved. Besides, an optimized search algorithm is used, and based on path measurement characteristics of Viterbi decoding, error positions are subjected to probability sorting and a search sequence is optimized, so that the efficiency of RS code decoding error correction is improved.

The invention discloses a stepped convolutional code (HSCBCC) coding and decoding method and device for high-speed large-bandwidth data transmission, and belongs to the technical field of communication channel coding. According to the coding method, a frame of data is divided into a plurality of groups of sub-data, a convolutional code coder is adopted to code a combined sequence of current sub-data and previous specific sub-data and a previous specific check sequence subjected to interleaving processing, and a current check sequence is generated; respectively retaining the current sub-data and the verification sequence to different subsequent moments as input; the decoding method comprises the following steps: iteratively processing channel information and extrinsic information of the corresponding sub-data and the check sequence, and outputting a decoding result. According to the invention, an asymmetric double-coupling structure is adopted, the bit error rate performance is superior to that of an existing space coupling coding scheme under the same resource consumption, and the method is adaptive to a multi-code-rate scene and is suitable for the technical field of large-bandwidth wireless communication or optical fiber communication.

To provide a method and an apparatus for receiving a PPDU on which BCC interleaving has been performed, in a multi-RU in a wireless LAN system.SOLUTION: Specifically, a receiving STA receives a PPDU including a data field from a transmitting STA and decodes the data field. The data field is received via a Multi-RU in which a first RU and a second RU are aggregated. The data field is generated based on a coded bit string included in a BCC interleaver block. The coded bit string is obtained by interleaving a data bit string based on first and second parameters. The data bit string is interleaved as the data bit string is entered into the BCC interleaver block in rows based on the first parameter and is read out in columns of the BCC interleaver block based on the second parameter.SELECTED DRAWING: Figure 26