31 results about "Majority logic" patented technology

A method for hard-decision channel decoding of tail-biting convolutional codes includes the step of receiving from a channel an input bit stream encoded by a tail-biting convolutional channel encoder. The encoder includes a number of memory elements and a rate. The input bit stream includes a series of symbols; each symbol includes a number of bits; the number of bits is related to the rate of the encoder. The method further includes the step of assuming a probability for each possible initial state of the encoder. The method further includes the step of decoding each symbol of the input bit stream using majority logic, with reference to a trellis structure corresponding to the encoder. The trellis structure represents: a number of states related to the number of memory elements of the encoder; a plurality of transitional branches; and a number of stages related to the number of symbols in the input bit stream.

The invention relates to a LDPC decoding method combining bit flipping (BF) and majority logic (MLG), belonging to the technical field of digital information transmission. The LDPC decoding method comprising the following steps of: (1) computing syndromes s of a check matrix of M rows and N columns, wherein s=(s1, s2, to sM), if the syndromes are all 0, and then carrying out step 4; (2) finding the most unreliable bit through a bit reliability measurement; (3) flipping and finding out the most unreliable bit; (4) when a largest iteration is achieved, carrying out step (5), and when all the syndromes are all 0, stopping decoding and outputting corresponding codons to complete decoding treatment, or else, repeating the steps of (1) to (3); and (5) sending the codons containing non 0 value in the syndromes to an MLG decoder for decoding, and finally outputting the codons decoded by the majority logic decoder to complete the decoding treatment. The invention utilizes the decoding method combining BF decoding and MLG without floating point arithmetic in the whole decoding process, reduces computation complexity and time delaying, and has favorable decoding performance.

The disclosed flash memory is provided with a majority logic circuit 3 and shift registers 6₁ to 6₃. Three out of the banks 2a to 2c of the memory respectively include management information areas KAs to store binary management information comprising power supply trimming data and bitline restoration data. During initialization of the flash memory, the majority logic circuit 3 performs error correction on management information bits retrieved from the management information areas KAs and outputs that information to a trimming/restoration data buffer 11, thus providing highly reliable management information very quickly. The shift registers 6₁ to 6₃ delay a control signal that is output from a control circuit 12 by a certain period of time before outputting the control signal to sense amplifiers 42 to 44. This delay makes it possible to make the operating currents of the banks 2a to 2d start to flow at different times and to suppress a peak current flowing in the flash memory.

A flip-flop circuit having a majority-logic circuit is disclosed. The circuit further includes multiple master latches for writing in corresponding input signals, and one slave latch having an input connected to an output of the majority-logic circuit and an output connected to the inputs of the majority-logic circuit. The majority logic-circuit has multiple inputs connected to respective outputs of the master latches. During the period in which the master latches do not write in the corresponding input signals, an output signal of the majority-logic circuit is supplied to respective inputs of the master latches.

The invention discloses a high-throughput and low-complexity hierarchy decoder suitable for a non-binary LDPC code and a decoding method of the decoder. The decoder comprises a relative addressing unit, a caching unit and a computing unit, wherein the relative addressing unit prestores an input address for each of the computing unit and the caching unit so that a redundant clock period is inexistent between tiers; the depth of the caching unit is 1 so that the delay is maximally lowered; the computing unit comprises 2p-1 basic computing units capable of accomplishing the updating of one tire in a clock unit and optimizing a key path of each module so as to improve the clock frequency. Furthermore, the decoding method disclosed by the invention is a hard decoding method based on majority logic so as to take a compromise on the decoding performance and the complexity; a most reliable message and a secondary reliable message are selected in the method, symbols and confidences thereof are input and output in a bit way, 2p messages are converted into the transmission of P messages, and the storage space is greatly lowered.

A novel majority logic circuit is disclosed to determine whether the majority of the inputs are a one, within a constant number of clock cycles, regardless of the number of inputs. The majority logic circuit according to the present invention includes a plurality of current mirror stages and an amplifier stage. For each input, one current mirror stage is used, which outputs either a current source if the input is a one, or a current sink if the input is a zero. The current sources of all the input current mirror stages are connected in parallel to the current source input node of the amplifier stage. The current sinks of all the input current mirror stages are connected in parallel to the current sink input node of the amplifier stage. The amplifier is a differential type, which outputs either a positive voltage or a zero voltage depending upon the majority of the inputs.

In one embodiment, a non-volatile memory device includes a plurality of protection bits denoting that an area of memory in the device must be protected from being erased or programmed. The memory device further includes a majority logic circuit for determining the logic state of the majority of the plurality of protection bits. Another embodiment includes a pattern generator for generating the logic levels to be stored in the plurality of protection bits.

A memory module includes a bridge controller having a first interface and a second interface. The first interface receives commands and data from a host and the second interface is coupled to one or more memory components. The bridge controller performs multiple-bit error detection and correction on data stored in the one or more memory components.

A system and method for determining soft read data for a group of cells in a nonvolatile flash memory are disclosed. An expected value representative of a plurality of stored values in a group of cells is obtained. A measured value representative of the plurality of stored values in the group of cells is obtained, based on a single read to the group of cells. A soft read data for the group of cells is determined based at least in part on the expected value and the measured value. The expected and measured values may include at least one of a number of 0s, a number of 1s, a ratio of 0s to 1s or a ratio of 1s to 0s. A reliability for a bit i may be obtained using a one-step majority logic decoder, and a threshold reliability may be used when determining the soft read data.

A signal demodulation method is disclosed, which includes: obtaining a complete transmission code word; calculating estimated values of three non-differential phases of the transmission code based on a majority logic; identifying a most unreliable phase among three non-differential phases and determining the other two reliable phases to obtain their determination values; calculating determination values of the rest two phases based on the two determined phases; and looking up in tables based on determination values of the four phases to obtain incoming bits. The demodulation method of the present invention is capable of sufficiently reducing the effect of noise on signal and effectively improving the signal demodulation performance.

The invention discloses a three-input majority logic device based on a TFET. The three-input majority logic device comprises a channel region, a source region, a drain region, a first gate oxide layer, a second gate oxide layer, a third gate oxide layer, a first metal gate electrode, a second metal gate electrode and a third metal gate electrode, wherein the channel region is of a T-shaped structure composed of a first rectangular block and a second rectangular block, and the source region is of a T-shaped structure composed of a third rectangular block and a fourth rectangular block. The drain region is of a T-shaped structure composed of a fifth rectangular block and a sixth rectangular block. The structure of the second gate oxide layer and the structure of the first gate oxide layer are bilaterally symmetrical relative to the center line of the second rectangular block in the vertical direction, and the structure of the second metal gate electrode and the structure of the first metal gate electrode are bilaterally symmetrical relative to the center line of the second rectangular block in the vertical direction; the third gate oxide layer is arranged on the upper end surface ofthe first rectangular block, and the third metal gate electrode is arranged on the upper end surface of the third gate oxide layer. The device has the advantages of compact structure, small area and low power consumption.

The invention relates to a circuit which is designed on the basis of a CMOS operational amplifier and is capable of achieving threshold logic, in particular to a threshold logic circuit based on the CMOS operational amplifier. The threshold logic circuit is only composed of an input resistor array, the operational amplifier and an inverter. The threshold value of the circuit is determined by reference voltage and input weight, weight of each input end is only relevant to a specific value of feedback resistance and input resistance, so that the reconfigurable performance is good, and different logic functions are achieved. In addition, a design method of the threshold logic circuit for achieving the logic function is introduced with implementation of a majority logic gate serving as an example and the correctness of the function of the circuit is verified through Cadence simulation. The threshold logic circuit based on the CMOS operational amplifier has the advantages of being simple in structure, good in reconfigurable performance and capable of serving as a basic unit to be applied to the fields of a neural network and the like.

The invention discloses a decimal full adder of quantum cellular automata. On the premise of not changing the logic function of the circuit, the QCA is optimized by combining the XOR logic operator with stronger expressive ability and the advanced carry structure of the full adder. The number of logic nodes and logic depth required by the decimal full adder, so as to optimize the area and delay of one-bit and multi-bit QCA decimal full adder circuits. Compared with the traditional full adder with the best performance, the quantum cellular automaton decimal full adder proposed by the present invention has excellent performance, and the delay and area are significantly improved, especially in the quantum cellular automaton 8-bit decimal full adder The optimization effect is more obvious, and the delay and area are increased by 27.6% and 53.4% ​​respectively. The invention greatly reduces the circuit cost, and at the same time enriches the circuit research method in circuit design. The invention provides a new research idea for arithmetic circuit design based on majority logic and XOR logic, and has strong practical significance for the development of circuit design.

The invention discloses a nano-magnetic logic multiple-selection logic gate circuit based on a magnetoelectric effect clock control method. The logic gate circuit comprises a first input end, a second input end, a third input end, an intermediate operation circuit, a first output end, a second phase inverter and a second output end, the intermediate operation circuit comprises a plurality of first phase inverters, a first two-input AND gate, a second two-input AND gate, a third two-input AND gate and a three-input OR gate. The intermediate operation circuit is connected with the input end, the output end of the intermediate operation circuit is connected with the three input OR gates, the three input OR gates are connected with the second phase inverter in series, and the output end of the second phase inverter serves as the second output end. The invention designs a clock control scheme based on a magnetoelectric effect on the basis of a majority logic gate circuit. Compared with other known clock control schemes, the clock control scheme can further reduce circuit power consumption and improve circuit speed, and the circuit is simple in structure and easy to prepare. Meanwhile, the clock control scheme is not only suitable for a majority logic gate circuit, but also can be applied to other NML circuits.

A logic gate with a neuron circuit which is used in electronic logic circuits, enables the arithmetic inputs to give output signal over the threshold value depending on a set threshold value according to the used AND, OR and MAJORITY logic gates, and enables to realize the logic processes by adjusting the triggering threshold value.