7 results about "Majority logic" patented technology

The invention discloses a graph mapping method based on precise synthesis, and the method comprises the steps: constructing a precise synthesis structure library based on NPN equivalence classes, and inputting the precise synthesis structure library into a Boolean network; k-Cut cutting enumeration is carried out on the input Boolean network, a truth table is calculated, cutting is matched with a structure in a precise comprehensive structure library through Boolean matching, and rapid search is realized in combination with NPN classification; the overlay network is generated through multi-round mapping optimization, logic sharing nodes are mined in combination with structural hash, and the multi-round mapping optimization comprises delay-oriented mapping, global area topological optimization and local accurate area optimization; and a new target network is generated based on the optimized overlay network, redundant nodes are removed, and final network construction is completed. According to the method, manual intervention is not needed through full-process automatic mapping and a redundancy removal mechanism, the labor cost of a technical mapping link in chip design is remarkably reduced, and the method is particularly suitable for efficient design of complex circuits and emerging majority of logic base technologies.

Apparatus and method for an attack resistant hardware accelerator. For example, one embodiment comprises an attack-resistant masked HMAC-SHA-2 accelerator with: (a) multiplexer-based implementations of masked choose (Ch) logic and majority (Maj) logic with implicit masked-domain non-linear computations; (b) Secure Binary to arithmetic (BtoA) conversion logic integrated within a masked carry-save-adder gate; and (c) an area-efficient arithmetic-to-Binary (AtoB) mask conversion circuit using a secure masked sparse-tree adder.

The application discloses a graph mapping method based on exact synthesis, comprising: constructing an exact synthesis structure library based on NPN equivalence class, and inputting a Boolean network; performing k-Cut cutting enumeration on the input Boolean network and calculating a truth table, matching the cutting with a structure in the exact synthesis structure library through Boolean matching, and realizing fast searching in combination with NPN classification; generating a cover network through multi-round mapping optimization, and mining a logic shared node in combination with structure hashing, wherein the multi-round mapping optimization comprises delay-oriented mapping, global area topology optimization and local exact area optimization; generating a new target network based on the optimized cover network, removing redundant nodes and completing final network construction. Through the automatic mapping and redundant removal mechanism of the whole process, the application does not need manual intervention, significantly reduces the manual cost of the technical mapping link in chip design, and is especially suitable for efficient design of complex circuits and emerging majority logic base technologies.

The invention belongs to the technical field of integrated circuit design, and particularly relates to an in-memory floating-point number calculation circuit and method based on a spin-orbit moment magnetic random access memory, and the circuit comprises a row decoder, a writing circuit, an SOT-MRAM array, a sensing amplifier SA, a control module, a column selection unit, a shifter and a rounding circuit. When the floating-point number multiplication circuit is used for carrying out floating-point number multiplication, an exclusive-OR gate is further constructed through a majority of logic gates constructed in the storage array, and the adder and the multiplier respectively carry out floating-point number sign bit exclusive-OR operation, exponent bit addition operation and mantissa multiplication operation. The mantissa bit normalization and rounding operations are respectively completed by an array external shifter and a rounding circuit, and adders and multipliers with different bits can be constructed in the storage array according to the type of the floating-point number. The method and the device can support calculation of multiple types of floating-point numbers and effectively reduce power consumption of floating-point number calculation.

A majority logic device 1 comprises a nonmagnetic semiconductor layer 10 comprising a material which, upon irradiation of light having at least two mutually different polarization states, generates electron spin waves having different phases depending on the polarization states. The nonmagnetic semiconductor layer 10 comprises three or more input sections for inputting optical signals and at least one output section for outputting the result of interference of the electron spin waves. The length of the projection of the distance between adjacent input sections as projected in the oscillating direction of the electron spin waves is an integer multiple of the wavelength of the electron spin waves.

This application discloses a reference signal generation circuit and its reading method for time-domain readout, relating to the field of integrated circuit technology. The circuit includes: a majority of logic gates, several reference generation column circuits, and several data column circuits. Each reference generation column circuit is equipped with a corresponding first sensing amplifier; each data column circuit is equipped with a corresponding multi-column selector, a second sensing amplifier, and a data register. The reference signal generation circuit of this application can be directly applied to time-domain readout. Combined with the reading method of this application, it can accurately read time-domain signals even when the detectability margin of the difference signal in the voltage or current domain is continuously decreasing, thereby realizing memory readout signals and improving reliability.

The invention provides an in-memory full adder and adder implementation method based on a nonvolatile semiconductor memory array, input and output of the in-memory full adder implementation method are both storage states of different storage units, and charge and discharge detection input is performed on a parasitic capacitor on a global source electrode lead when the storage units are started. The sensitive amplifier is used for making logic judgment to finish writing; multiple-input majority MAJORITY and odd-even PARITY logics can be realized in an array at a time, carry output is generated through the MAJORITY logics, standard sum is generated through the PARITY logics, and the carry output and the standard sum are combined to form an in-memory full adder; the multi-bit in-memory traveling wave carry adder is constructed by cascading a plurality of full adders, taking the carry output of each full adder except the highest bit as the carry input of a higher full adder and taking the carry output of the highest bit full adder as the highest bit of an addition result. The method is few in operation steps and high in running speed, logic time overhead and logic comprehensive difficulty are reduced, and calculation efficiency is improved.