25 results about "Triple modular redundancy" patented technology

The invention provides a high-reliability on-orbit reconstruction method for large satellite-borne software, which is characterized in that a BootLoader program solidified on a PROM (programmable read-only memory) is designed with a function of reconstructing any software at a low speed by using a bus, so that the BootLoader program serves as the most fundamental guarantee for the reliability of a reconstruction scheme; a high-speed self-reconfiguration function is designed for the satellite-borne software, so that the high-speed channel self-reconfiguration software can be utilized after the satellite-borne software is started in a normal process; security mode software which is small in size and can exist on an MRAM in a triple modular redundancy mode is constructed, and the main function of the security mode software is to complete high-speed reconstruction of satellite-borne software. And when self-reconfiguration of the satellite-borne software fails and the satellite-borne software cannot be normally started, a special instruction is sent to the BootLoader to start the security mode software, so that high-speed reconfiguration of the satellite-borne software can be continued. The whole satellite-borne software can be reconstructed in a measurement and control arc section through a high-speed channel. Compared with a mode that a comprehensive electronic system spends several measurement and control arc segments to collect data and then distributes the data at a low speed through a bus channel, the method has the advantages that the required time is greatly shortened, and the reliability is high.

The application discloses a fault-tolerant implementation method of a star sensor storage system against single event upsets, and solves the short board of the existing star sensor storage system against single event upsets and the technical problem that the processor internal FLASH capacity is insufficient to implement triple modular redundancy and the like.The method comprises three parts of power-on loading fault-tolerant reading, external SRAM star table dynamic refreshing and internal FLASH data automatic repairing.The ECC error processing is accurate and efficient, and is suitable for the hardware characteristics.The hardware parameters of 32 bytes corresponding to 10 bits of ECC and 32 byte error positioning granularity are adapted, single-bit error is only recorded and not switched to backup, the data accuracy is guaranteed by relying on hardware error correction, double-bit error is temporarily switched to backup reading, the error correction efficiency and data reading fluency are considered, and the real-time operation requirement of the star sensor is met.The application greatly improves the reliability of the star sensor in long-term operation in orbit, and effectively reduces the failure rate in orbit and operation and maintenance cost.

The invention discloses an intelligent driving Linux system multi-mode dynamic adjustment method based on a multi-core processor, relates to the technical field of intelligent driving, and aims to solve the problems that in existing intelligent driving system multi-core scheduling, calculation power and power consumption are difficult to balance, real-time performance is insufficient, reliability is limited, and performance is reduced due to resource competition. The real-time performance is guaranteed by adopting a Linux system, multi-core distribution is optimized through task CPU affinity configuration, three dynamic switching modes of low power consumption, triple modular redundancy and high performance are designed, and on-demand distribution of computing power, dynamic optimization of power consumption and rapid fault tolerance are realized in combination with a module dependency analysis and partition scheduling strategy. According to the method, the real-time response capability, the endurance performance and the reliability of the intelligent driving system are remarkably improved, the resource waste is reduced, and the method is suitable for various multi-core processor vehicle-mounted intelligent driving platforms.

The invention provides a high-reliability heterogeneous computing device for satellite-borne intelligent computing cooperative processing, which comprises a hardware layer and a system software layer, and is characterized in that the hardware layer adopts a heterogeneous fusion architecture of CPU + GPU + FPGA to realize cooperative computing processing for intelligent satellite-borne tasks; the system software layer adopts a three-layer fault-tolerant system comprising an intelligent computing-oriented operating system bottom layer, an operating system service layer and an operating system application layer; wherein the bottom layer of the operating system is based on a hierarchical multi-stage hybrid redundancy strategy, and on-orbit self-repairing of a core file of the operating system is realized by dynamically refreshing a hybrid triple modular redundancy design; the operating system service layer adopts a lightweight virtualization multi-dimensional error isolation technology and an intelligent dynamic check point frequency strategy to realize independent operation and check point recovery of satellite-borne applications; and the operating system application layer realizes autonomous detection and hierarchical recovery by establishing a full-life-cycle management mechanism of a satellite-borne application program.

The application discloses a general circuit part redundancy reinforcing method and system based on HITS, and the method comprises the following steps: generating a node relation matrix according to the connection relation between nodes; performing HITS iteration on the node relation matrix to obtain the HITS value of the node; sorting the nodes in descending order based on the HITS value, selecting the first number of nodes as the nodes to be reinforced; the first number is determined by the finally determined reinforcing proportion; and performing partial three-mode redundancy reinforcement on the nodes to be reinforced. Through the technical scheme, the additional resource consumption can be effectively reduced under the high reliability requirement.

The application provides an anti-single event upset processing method for avionics, which comprises the following steps: step one, defining and initializing a configurable hierarchical check data structure; step two, entering a loop task and obtaining to-be-written data; step three, writing the to-be-written data and a correction detection mode into the data structure; and step four, when the data needs to be read, reading to-be-read data from the data structure in groups. Compared with a traditional triple modular redundancy scheme, the application reduces storage occupation by more than 60%, solves the problem of high cost of directly using Hamming code for real-time correction and detection of memory data in an aviation device, and reduces resource consumption of encoding and decoding while having correction and detection capability, thereby meeting high requirements of the aviation device on real-time performance and resource efficiency.

This invention belongs to the field of triple mode redundancy (TMR) technology, and particularly relates to a selective TMR conversion method and system based on two-stage decoupling. The method includes acquiring the Verilog design code to be converted and parsing the circuit signals; calculating the dynamic activity of each circuit signal, dividing the circuit signals into critical and non-critical circuit signals, and forming a list of critical circuit signals; reading the list of critical circuit signals, traversing each assignment statement in the Verilog design code to be converted, and identifying whether the current circuit signal is a critical circuit signal; performing TMR operation on the identified critical circuit signals, and using logical assignment to make the replica signals track the original signals in real time for the identified non-critical circuit signals, thus completing the selective TMR conversion. This invention completely decouples the two stages of dynamic activity analysis of circuit signals and selective conversion of source code, and performs true / pseudo-TMR splitting processing.

The application provides a dual-Flash-based satellite-borne network operating system guarantee method, adopts a main Flash memory and a backup Flash memory to store a boot program Uboot and a micro system ONIE, and constructs an image array to store a network operating system NOS; the guarantee method comprises dual-Flash partition planning, Uboot main-backup cooperation and single particle effect repair, Uboot environment variable main-backup checking and repair, ONIE system main-backup backup and integrity checking repair, and SSD hard disk reliability guarantee and single particle effect repair. The purpose of low cost and high reliable operation of the satellite-borne network operating system is achieved. The method can be used in combination with a traditional three-mode redundancy scheme, and can also be used as a backup reliability guarantee scheme after failure of a three-mode redundancy chip.

The invention provides a CPU / FPGA high-reliability loading method and device based on triple modular redundancy, and relates to the field of electrical digital data processing.The method comprises the steps that multiple loading files are configured for a CPU and / or an FPGA, and the loading files are stored in at least one set of hot backup memories and at least one set of cold backup memories respectively; wherein the hot backup memory and the cold backup memory both adopt a triple modular redundancy design; in response to power-on of the CPU or the FPGA, reading the loading files from the hot backup memory in sequence, and judging final data from the read loading files according to a preset judgment mode to serve as the loading files of the CPU or the FPGA; whether the CPU or the FPGA is successfully loaded or not is judged, and if the CPU or the FPGA fails to be loaded, the corresponding loading process is executed again; and if the CPU or the FPGA is successfully loaded, the corresponding loading process does not need to be executed. According to the invention, rapid and reliable switching of multiple modes in different working states is realized, and the system continuity requirement in an extreme environment is met.

This invention discloses a redundant architecture method for a UAV flight control system, relating to the field of UAV control technology. It includes redundant design for four layers: flight sensor system, redundant flight control computer system, bus communication system, and actuator system. The bus communication system employs a three-bus redundant architecture consisting of a 1553B dual-bus, FlexRay bus, and CAN bus. The redundant flight control computer system features automatic switching between three modes: triple-mode redundancy, dual-mode redundancy, and single-mode redundancy, and possesses online fault channel repair and reconnection capabilities. The actuator system includes aerodynamic control surface segment redundancy, servo electrical dual-path redundancy, and dual-path access redundancy via the CAN bus main path and RS422 backup path. This invention, using the aforementioned redundant architecture method for a UAV flight control system, achieves long-endurance, highly reliable flight control with no awareness of single faults, return capability in the event of dual faults, and no degradation due to bus faults.

The invention belongs to the technical field of computers, and provides a self-adaptive memory protection method and device for dynamically adjusting triple modular redundancy voting frequency, a management structural body is created and initialized for key data, and the management structural body comprises three data copy pointers and three data copies for managing the key data; monitoring system state parameters related to the key data in real time or periodically, wherein the system state parameters comprise a system load rate and a historical error rate of data inconsistency of the management structure body in historical voting; dynamically adjusting a voting frequency strategy for executing two-out-of-three voting operation on the three data copies according to the monitored system state parameters; and executing corresponding two-out-of-three voting operation on the three data copies according to the voting frequency strategy. According to the method, the voting frequency of triple modular redundancy can be dynamically adjusted according to the system load and the historical error rate, so that the system performance is remarkably optimized and the power consumption is reduced while the reliability of the memory is ensured.

The application discloses an anti-radiation three-mode redundant latch, and belongs to the field of anti-radiation design of special integrated circuits. The application designs a novel main-stage latch and a novel redundant voting circuit, which comprises a first transistor-stage voting circuit, a second transistor-stage voting circuit and a protection gate circuit. The application reinforces the main-stage latch and the voting circuit from the circuit structure, enhances the resistance of the main-stage latch to SNU and DNU, reduces the influence of SNU of the voting circuit itself on the output result, and enhances the stability of the three-mode redundant system. The total number of MOS tubes of the redundant voting circuit of the application is only 30% of the total number of MOS tubes of the full three-mode redundant voting circuit, effectively reduces the area cost of the three-mode redundant system, and is more suitable for the anti-radiation design of super large scale integrated circuits.

The present application relates to the technical field of embedded flash memory data reading, and discloses a read data path of an eFLASH controller and a functional safety design method of a read Cache, three groups of Datapath+Cache are arranged in the FLASH controller to realize three-mode redundancy and heterogeneous redundancy, and Cross modules are used to realize hierarchical redundancy and circuit recombination; a CPU realizes module configuration through an APB, and the CPU or other Master accesses a Flash Memory through AXI via the Cache and the Data_path. The read data path of the eFLASH controller and the functional safety design method of the read Cache realize three-mode redundancy, hierarchical redundancy and heterogeneous redundancy in combination, adopt hierarchical circuit recombination design, and adopt the functional safety design of the front four-stage register+inverter, so that the data path can be flexibly configured, the composite redundancy design of the read data path of the eFLASH controller and the read prefetch Cache is realized, the whole scheme is more reliable, more efficient and more flexible, the eFLASH reading efficiency can be effectively improved, and the functional safety requirement of the vehicle is met.

The invention belongs to the technical field of semiconductors and integrated circuits, and particularly relates to an agile soft error optimization method based on reinforcement learning. The method comprises the following steps: a data generation step: generating a large number of virtual circuit samples according to characteristics and design constraints of circuit reinforcement to obtain a high-quality data set for model training; a model training step: training the model by adopting a reinforcement learning algorithm, so that the model gradually learns a universal reinforcement strategy in the reinforcement process of a large number of virtual circuits; and a model deployment step: deploying the trained reinforcement learning model for circuit reinforcement reasoning, and for a to-be-reinforced circuit, rapidly predicting a design index by a system in a reasoning process based on an agent model so as to support an efficient reinforcement decision. The method has high expansibility, high efficiency and good universality, can be widely applied to fault-tolerant reinforcement design of various high-reliability circuit structures, such as triple modular redundancy and other schemes, and can meet the circuit soft error protection requirements under multiple scenes and multiple constraints.

The invention discloses an FPGA triple modular redundancy method and device based on a data area and electronic equipment, and relates to the technical field of digital system fault tolerance, and the method comprises the steps: abstracting a circuit netlist into a directed graph; specifying a reinforcement object; for each reinforcement object, starting from the reinforcement object, carrying out retrograde search traversal in the reverse direction of signal transmission, and combining data paths formed by found nodes and cross nodes into a data area of the reinforcement object; merging the data areas with the cross nodes; and performing triple modular redundancy on the basis of the merged data area. On the basis of the circuit netlist, the circuit netlist is abstracted into a digraph form, and triple modular redundancy design is performed in a targeted manner by searching for data paths, dividing data areas and finding out parts which have great influence on the sequential logic circuit, so that the overhead can be saved, and the security reinforcement effect can be improved.

This invention belongs to the field of computer technology and proposes an adaptive memory protection method and apparatus for dynamically adjusting the voting frequency of triple modular redundancy (TMR). It involves creating and initializing a management structure for critical data, which includes three data copy pointers to manage three copies of the critical data. The method monitors system status parameters related to the critical data in real time or periodically, including system load rate and the historical error rate of data inconsistencies in historical voting. Based on the monitored system status parameters, it dynamically adjusts the voting frequency strategy for performing a two-out-of-three voting operation on the three data copies. Following the voting frequency strategy, it performs the corresponding two-out-of-three voting operation on the three data copies. This invention can dynamically adjust the voting frequency of TMR based on system load and historical error rate, thereby significantly optimizing system performance and reducing power consumption while ensuring memory reliability.

This invention discloses an on-chip network device configuration method and circuit, belonging to the field of digital integrated circuits. The configuration method includes: using a custom protocol and transmitting data according to a packet format; classifying the configuration and configuration status reading of the on-chip network device into four basic operations: configuration write request operation, configuration write response operation, configuration read request operation, and configuration read response operation; defining four basic event packets: configuration write request event packet, configuration write response event packet, configuration read request event packet, and configuration read response event packet, corresponding to the four basic operations respectively; encoding the control information, address information, and data information to be transmitted in a unified format to form a complete event packet, which is then segmented into micro-chips by the on-chip network circuit and transmitted sequentially. This invention ensures the reliability of the on-chip network device configuration method and circuit through triple modulo redundancy, parity checking, and a request-based timeout retransmission mechanism.

The application discloses a kind of dynamic three-mode redundancy circuit design methods based on circuit sensitivity, it is related to integrated circuit reliability design technical field, the method is first by the single event upset injection simulation to target circuit, the sensitivity of each circuit module is quantitatively evaluated and classified, distinguish high sensitive module and low sensitive module.Subsequently, high sensitive module is reinforced using static three-mode redundancy structure;For low sensitive module, it is replaced by a kind of dynamic controllable three-mode redundancy structure, the structure includes a main module and two clock-controlled clock circuit controlled controllable redundancy module of clock gating.The start-stop of redundancy module is controlled by constructing the clock gating path based on latch, and the synchronous control signal generated by the path is used to drive output selection circuit, the fast, error-free switching between single-mode energy-saving mode and three-mode redundancy mode is realized.The application ensures high reliability of system, significantly reduces dynamic power consumption and hardware overhead.

The application belongs to the technical field of three-mode redundancy recovery strategy, and particularly relates to a hierarchical abnormal recovery method and system for three-mode redundancy. The method comprises the following steps: obtaining fault signals of each key module in a to-be-monitored processor; analyzing the fault signals to obtain fault information, wherein the fault information comprises a fault type and a physical position where the fault occurs; obtaining a fault level of the current fault signal based on the fault information and in combination with a preset judgment rule; mapping different fault levels to different recovery mechanisms; and recovering the key module in the to-be-monitored processor according to the recovery mechanism corresponding to the current fault level. The application introduces a configurable multi-level fault judgment and a multi-layer recovery path, integrates module importance, fault scale, time sequence and timeout strategy into a unified strategy set, so that the system can select a recovery path with the minimum cost, the minimum influence range and the highest success rate for recovery when facing different fault intensities.

A configurable fault-tolerant satellite service software task scheduling system based on a multi-core processor is statically configured into a low-power mode, a three-mode redundancy mode or a high-performance mode through at least three processors, and is dynamically configured by mode switching according to a satellite running state and a task demand; the application can fully utilize the advantages of the multi-core processor in various scenes; the application is low in cost, does not need additional hardware to realize arbitration, and is convenient for troubleshooting and debugging; the application is flexible in function, and can dynamically configure a working mode according to a satellite running state and a remote control instruction.

The invention discloses an FPGA (Field Programmable Gate Array) on-orbit block reconstruction method based on triple modular redundancy. The method comprises the following steps: firstly, segmenting a configuration file of a baseband processing firmware FPGA module into a plurality of small blocks of reconstruction data on the ground; secondly, selecting a reconstruction channel on the ground, assigning an area address of the Flash chip, and erasing the assigned area of the Flash chip by the Flash control module; then, the ground sends reconstruction data to the reconstruction data receiving management module through a selected reconstruction channel, and the Flash control module writes the data into a designated area of each Flash chip; and finally, the Flash control module receives and reads the reconstruction data of the designated area on each Flash chip, and after three-mode comparison, a configuration file is sent to the baseband processing firmware FPGA module for program configuration. According to the method, the data blocks to be transmitted are flexibly selected according to task requirements or real-time changes, fault-tolerant block reconstruction of the system is realized, and the efficiency of subsequent reconstruction work is improved.

The invention provides a BRAM single event upset relieving method for an FPGA, belongs to the technical field of complex electronic hardware airworthiness, and particularly relates to a BRAM data content encoding method adopting a specific encoding mode during BRAM data writing. When data of the BRAM are read out, error data correction is achieved through a supervision vector and a data error vector related to a calculation and coding mode, so that the single event upset phenomenon of the BRAM can be detected, BRAM resources are saved compared with a triple modular redundancy mitigation measure, additional hardware circuits are saved compared with a refreshing method, and the cost is reduced. Compared with the similar common Hamming ECC coding mode, the FPGA logic levels realized by the method are fewer, the mitigation measure realized by the method supports fault injection and white-box testing, and the security of the FPGA is effectively enhanced in the civil aviation FPGA development process.

The invention discloses a triple modular redundancy computer parallel operation method based on memory replication. The method comprises the steps that three computers of a computer are all set to be in a thermal fault-tolerant working mode; setting the computer A to be in a forced on-duty mode; respectively powering up the computer B and the computer C to complete synchronization with the control period of the computer A; setting operation parameters of the three computers of the computer; the three computers start corresponding parallel operation on the program area and the data area according to the program area setting mark, the data area setting mark and the control period mark; and carrying out parallel data interaction among the three computers through a high-speed bus among the three computers, calculating the length and the cumulative sum of the parallel data, if the length and the cumulative sum of the parallel data of the three computers are consistent, carrying out parallel data write-back, and carrying out internal exchange on a write-back completion mark after write-back is completed. After the three-machine exchange marks are completed, the three machines are recovered from the stop control mode to the normal working mode; and after it is judged that parallel operation is completed through telemetering and data comparison is consistent, the three-machine working mode is switched into an autonomous on-duty mode.