53 results about "Triple modular redundancy" patented technology

The invention provides a vehicle load estimation method and system based on a parallel hybrid architecture, and belongs to the technical field of vehicle load regulation and control. Comprising the steps of obtaining vehicle composite data in real time based on a multi-modal sensor and executing preprocessing; inputting the preprocessed vehicle composite data into a parallel hybrid architecture to predict a load motion state and a load compensation value; carrying out dynamic load separation on the predicted value of the parallel hybrid architecture by adopting an improved EEMD algorithm; fusing the separation result based on federated Kalman filtering to obtain an estimated value of the vehicle load; and the estimated value is verified based on a triple modular redundancy architecture, and then whether a vehicle load fault recovery process is triggered or not is determined. According to the method, through multi-source data fusion and parallel hybrid architecture modeling, a physical equation is combined with machine learning, and high-precision estimation under a static working condition and adaptive optimization of a dynamic working condition can be realized while the cost and hardware dependence are reduced.

The invention discloses a low-cost soft error reinforcement method based on an approximate triple modular redundancy unit. The method comprises the following steps: establishing an approximate library: establishing an approximate gate unit for a basic gate unit of a to-be-reinforced circuit, and integrally establishing an approximate gate unit library; software modeling: acquiring basic information of each standard gate unit in the circuit, and evaluating the performance of the circuit according to a soft error propagation physical model so as to perform software modeling; and approximate reinforcement: selecting a gate unit in a to-be-reinforced circuit in a semi-directional manner based on improved dynamic adjustment NSGA-II to replace the gate unit with an approximate gate unit in an approximate library, simulating circuit performance indexes through an estimator, performing multi-target optimization solution, obtaining an optimal compromise of area, power consumption and soft error rate through iteration, and giving an approximate reinforcement scheme. The method has high efficiency, practicability and universality, can be used for guiding low-cost soft-error-tolerant approximate reinforcement of various high-reliability structures such as triple modular redundancy (TMR) and the like, and can adapt to multi-scene and multi-requirement circuit reinforcement design.

The invention relates to the technical field of fire safety. The building fire safety intelligent monitoring method and system are provided, and the method comprises the steps: carrying out registration authentication and communication resource configuration on multi-mode fire fighting equipment, and generating an equipment registration center database; dynamically allocating communication resources by using a two-dimensional priority arbitration mechanism, and generating a hierarchical transmission queue; carrying out anti-interruption transmission on the monitoring data through a triple modular redundancy transmission network, and generating a multi-path transmission state report; acquiring the multi-source data transmitted by the hierarchical transmission queue, performing space-time alignment and knowledge graph association processing on the multi-source data transmitted to the edge gateway, and outputting a structured security situation report; the structured security situation report is converted into a control instruction, so that the data loss risk of a high-risk area is reduced, the supporting capacity of multi-source data for fire-fighting command decision is improved, and the problems of linkage control resource mismatching and insufficient response are reduced.

The invention provides a high-reliability on-orbit reconstruction method for large satellite-borne software, which is characterized in that a BootLoader program solidified on a PROM (programmable read-only memory) is designed with a function of reconstructing any software at a low speed by using a bus, so that the BootLoader program serves as the most fundamental guarantee for the reliability of a reconstruction scheme; a high-speed self-reconfiguration function is designed for the satellite-borne software, so that the high-speed channel self-reconfiguration software can be utilized after the satellite-borne software is started in a normal process; security mode software which is small in size and can exist on an MRAM in a triple modular redundancy mode is constructed, and the main function of the security mode software is to complete high-speed reconstruction of satellite-borne software. And when self-reconfiguration of the satellite-borne software fails and the satellite-borne software cannot be normally started, a special instruction is sent to the BootLoader to start the security mode software, so that high-speed reconfiguration of the satellite-borne software can be continued. The whole satellite-borne software can be reconstructed in a measurement and control arc section through a high-speed channel. Compared with a mode that a comprehensive electronic system spends several measurement and control arc segments to collect data and then distributes the data at a low speed through a bus channel, the method has the advantages that the required time is greatly shortened, and the reliability is high.

The invention discloses a low-cost satellite-borne core circuit, an operation method and an electronic device, and belongs to the field of satellite communication circuit design, the low-cost satellite-borne core circuit comprises an embedded MCU, a peripheral circuit and embedded MCU software, the peripheral circuit is connected with the embedded MCU, and the embedded MCU software is loaded and operated by the MCU. According to the invention, based on a new generation of vehicle-gauge-level embedded MCU and peripheral components, the cost of components applied to low-orbit satellite-borne products is greatly reduced; according to the circuit design, multiple redundancy reinforcement technical means such as MCU processor redundancy backup, external interface circuit redundancy backup, software program storage redundancy backup and software triple modular redundancy reinforcement are adopted, and the operation reliability of a core circuit in a low-orbit satellite-borne environment is ensured.

The invention discloses an FPGA (Field Programmable Gate Array) self-excitation signal detection method and device based on a signal feedback loop, and the method comprises the steps: firstly, reading a received FPGA hardware description language code file, and integrating all modules in an FPGA code to form an overall code file from top to bottom; secondly, mapping the overall code file of the FPGA into a signal transmission network according to a transmission relationship among signals in the overall code file of the FPGA; and thirdly, searching all signal feedback loops in the signal transmission network, calculating signal feedback probabilities, selecting and recording the signal feedback loops of which the signal feedback probabilities are greater than a set threshold, and extracting signals in the signal feedback loops as self-excitation signals to be output. According to the method, the self-excitation signal in the FPGA design and the occurrence probability of the self-excitation signal can be effectively detected, the method is easy to use and low in investment cost, and the requirement for self-excitation signal detection when the triple modular redundancy design is carried out can be well met.

The application discloses a fault-tolerant implementation method of a star sensor storage system against single event upsets, and solves the short board of the existing star sensor storage system against single event upsets and the technical problem that the processor internal FLASH capacity is insufficient to implement triple modular redundancy and the like.The method comprises three parts of power-on loading fault-tolerant reading, external SRAM star table dynamic refreshing and internal FLASH data automatic repairing.The ECC error processing is accurate and efficient, and is suitable for the hardware characteristics.The hardware parameters of 32 bytes corresponding to 10 bits of ECC and 32 byte error positioning granularity are adapted, single-bit error is only recorded and not switched to backup, the data accuracy is guaranteed by relying on hardware error correction, double-bit error is temporarily switched to backup reading, the error correction efficiency and data reading fluency are considered, and the real-time operation requirement of the star sensor is met.The application greatly improves the reliability of the star sensor in long-term operation in orbit, and effectively reduces the failure rate in orbit and operation and maintenance cost.

The invention discloses a triple modular redundancy method based on redundancy backup and FPGA (Field Programmable Gate Array) control. Three groups of data lines are expanded on the FPGA to be connected with the Norflash, and three groups of data are read at the same time to perform triple modular redundancy calculation. The FPGA controls the four Norflash to write data at the same time during writing, and the FPGA chip selects the Norflash to output according to a logic sequence during reading, and determines whether to perform triple modular redundancy operation by judging the state of the Norflash. And sending the wrong sector number and the wrong Norflash number to the SOC chip through a serial port and a corresponding protocol, then sending the wrong sector number and the wrong Norflash number to the ground through the SOC chip, and after an instruction from the ground is received, carrying out error correction on the Norflash according to the instruction. According to the method, the influence of the radiation effect on the low-orbit satellite in the space is overcome, the cost is reduced to a certain extent, the speed and the efficiency are ensured, and meanwhile, the problems that under the condition that only three Norflash pieces exist, one Norflash piece breaks down, so that resources of the other two Norflash pieces are wasted, and data reading based on triple modular redundancy cannot be achieved are solved in a redundant backup mode.

The invention discloses an intelligent driving Linux system multi-mode dynamic adjustment method based on a multi-core processor, relates to the technical field of intelligent driving, and aims to solve the problems that in existing intelligent driving system multi-core scheduling, calculation power and power consumption are difficult to balance, real-time performance is insufficient, reliability is limited, and performance is reduced due to resource competition. The real-time performance is guaranteed by adopting a Linux system, multi-core distribution is optimized through task CPU affinity configuration, three dynamic switching modes of low power consumption, triple modular redundancy and high performance are designed, and on-demand distribution of computing power, dynamic optimization of power consumption and rapid fault tolerance are realized in combination with a module dependency analysis and partition scheduling strategy. According to the method, the real-time response capability, the endurance performance and the reliability of the intelligent driving system are remarkably improved, the resource waste is reduced, and the method is suitable for various multi-core processor vehicle-mounted intelligent driving platforms.

The invention provides a high-reliability heterogeneous computing device for satellite-borne intelligent computing cooperative processing, which comprises a hardware layer and a system software layer, and is characterized in that the hardware layer adopts a heterogeneous fusion architecture of CPU + GPU + FPGA to realize cooperative computing processing for intelligent satellite-borne tasks; the system software layer adopts a three-layer fault-tolerant system comprising an intelligent computing-oriented operating system bottom layer, an operating system service layer and an operating system application layer; wherein the bottom layer of the operating system is based on a hierarchical multi-stage hybrid redundancy strategy, and on-orbit self-repairing of a core file of the operating system is realized by dynamically refreshing a hybrid triple modular redundancy design; the operating system service layer adopts a lightweight virtualization multi-dimensional error isolation technology and an intelligent dynamic check point frequency strategy to realize independent operation and check point recovery of satellite-borne applications; and the operating system application layer realizes autonomous detection and hierarchical recovery by establishing a full-life-cycle management mechanism of a satellite-borne application program.

The invention relates to a three-mode trigger layout, a chip and a method for resisting single event upset, and the method comprises the steps: adjusting and designing the layout of a circuit layout of a three-mode redundancy circuit, placing three-mode redundancy trigger units in a staggered manner, isolating the trigger through an internal module, and carrying out the protection ring reinforcement of a voter disposed at the center of the three-mode redundancy trigger units. The external interference is isolated to reduce the probability of voting failure, the multi-bit flipping probability is reduced to ensure the safety of three-copy data by utilizing the modes of overall centralized layout, staggered arrangement of trigger units and protection ring reinforcement of the voter, the interconnection is minimized to reduce the time sequence mismatch problem, and the voting efficiency is improved. Meanwhile, the influence of external interference on the voter is isolated, so that the probability of voting failure is reduced, the bottleneck of traditional layout design is broken through finally, the inherent technical defects of multi-bit flipping, time sequence mismatching and the like induced by particle tracks are solved from the physical level, and a more practical and effective reinforcing scheme is provided for the triple modular redundancy trigger.

The application discloses a general circuit part redundancy reinforcing method and system based on HITS, and the method comprises the following steps: generating a node relation matrix according to the connection relation between nodes; performing HITS iteration on the node relation matrix to obtain the HITS value of the node; sorting the nodes in descending order based on the HITS value, selecting the first number of nodes as the nodes to be reinforced; the first number is determined by the finally determined reinforcing proportion; and performing partial three-mode redundancy reinforcement on the nodes to be reinforced. Through the technical scheme, the additional resource consumption can be effectively reduced under the high reliability requirement.

The invention belongs to the technical field of integrated circuits, and particularly relates to a triple modular redundancy implementation method based on a shell script. Comprising the following steps: S1, constructing triple modular redundancy of clock and reset, synthesizing by using a DC tool, and outputting a file required by a script; s2, a shell script is used for processing files needed by the script, and three files are obtained; s3, creating a triple modular redundancy module; s4, processing the netlist file corresponding to the sub-level module of the current level in parallel; s5, modifying instantiation ports of all sub-level modules in the netlist file corresponding to the mother-level module of the current level; s6, taking the higher level as the current level and returning to the step S4 until the mother level module of the current level is the top level module; s7, checking whether the clock and reset signals of the top-layer module are consistent with instantiated port signals of the clock and reset of the sublevel module of the top-layer module or not, and if yes, outputting a triple-modular redundancy netlist; otherwise, returning to the step S1; the chip development cycle is shortened, and readability and maintainability are high.

The application provides an anti-single event upset processing method for avionics, which comprises the following steps: step one, defining and initializing a configurable hierarchical check data structure; step two, entering a loop task and obtaining to-be-written data; step three, writing the to-be-written data and a correction detection mode into the data structure; and step four, when the data needs to be read, reading to-be-read data from the data structure in groups. Compared with a traditional triple modular redundancy scheme, the application reduces storage occupation by more than 60%, solves the problem of high cost of directly using Hamming code for real-time correction and detection of memory data in an aviation device, and reduces resource consumption of encoding and decoding while having correction and detection capability, thereby meeting high requirements of the aviation device on real-time performance and resource efficiency.

The invention discloses a multi-task modular hierarchical regulation and control system based on a multi-core CPU architecture, which relates to the technical field of power generation control, and comprises a domestic multi-core CPU hardware basic module adopting a Feiteng or Peng architecture, a triple modular redundancy design and a 24-bit AD signal acquisition module based on a domestic operating system; the multi-task hierarchical scheduling core module is used for five-level priority division, a core binding and dynamic migration strategy and an improved round-robin algorithm; the modular function adaptation interface module supports hot plug, parameter self-matching and dual-path redundancy switching; the running state monitoring and feedback module is used for evaluating the health state in a weighted fusion manner; and an open development support module, dual-mode configuration and an encapsulation algorithm support third-party development and version management. According to the method, DCS autonomous controllability and efficient and balanced multi-task scheduling are realized, the operation monitoring and operation and maintenance intelligent level is improved, and safe and efficient operation of a unit is guaranteed.

This invention belongs to the field of triple mode redundancy (TMR) technology, and particularly relates to a selective TMR conversion method and system based on two-stage decoupling. The method includes acquiring the Verilog design code to be converted and parsing the circuit signals; calculating the dynamic activity of each circuit signal, dividing the circuit signals into critical and non-critical circuit signals, and forming a list of critical circuit signals; reading the list of critical circuit signals, traversing each assignment statement in the Verilog design code to be converted, and identifying whether the current circuit signal is a critical circuit signal; performing TMR operation on the identified critical circuit signals, and using logical assignment to make the replica signals track the original signals in real time for the identified non-critical circuit signals, thus completing the selective TMR conversion. This invention completely decouples the two stages of dynamic activity analysis of circuit signals and selective conversion of source code, and performs true / pseudo-TMR splitting processing.

The present invention discloses a polar code decoding device for space use, comprising: a data receiving and distribution module and M parallel decoding modules. The decoding modules operate in parallel to improve throughput, and each independent decoding module is composed of a decoding process control module, a judgment and sorting module, an LLR update module, and a coding update module. The present invention saves logic and storage resources by reusing the LLR calculation module in the LLR update module and reusing the storage space for LLR intermediate values ​​and coding intermediate values. It uses a parallel bubble algorithm and a binary insertion algorithm for frozen bits and information bits, respectively, to save sorting time. It uses a pipeline operation and judgment selection calculation method to shorten LLR processing delay. It uses a method of recording index values ​​and a reverse CRC algorithm, eliminating the need for path replication. It adopts a "triple modular redundancy + dynamic refresh" design to adapt to space environments. It has the characteristics of low resource usage, low processing delay, high operating frequency, and strong tolerance to space environments.

The application provides a dual-Flash-based satellite-borne network operating system guarantee method, adopts a main Flash memory and a backup Flash memory to store a boot program Uboot and a micro system ONIE, and constructs an image array to store a network operating system NOS; the guarantee method comprises dual-Flash partition planning, Uboot main-backup cooperation and single particle effect repair, Uboot environment variable main-backup checking and repair, ONIE system main-backup backup and integrity checking repair, and SSD hard disk reliability guarantee and single particle effect repair. The purpose of low cost and high reliable operation of the satellite-borne network operating system is achieved. The method can be used in combination with a traditional three-mode redundancy scheme, and can also be used as a backup reliability guarantee scheme after failure of a three-mode redundancy chip.

The invention provides a CPU / FPGA high-reliability loading method and device based on triple modular redundancy, and relates to the field of electrical digital data processing.The method comprises the steps that multiple loading files are configured for a CPU and / or an FPGA, and the loading files are stored in at least one set of hot backup memories and at least one set of cold backup memories respectively; wherein the hot backup memory and the cold backup memory both adopt a triple modular redundancy design; in response to power-on of the CPU or the FPGA, reading the loading files from the hot backup memory in sequence, and judging final data from the read loading files according to a preset judgment mode to serve as the loading files of the CPU or the FPGA; whether the CPU or the FPGA is successfully loaded or not is judged, and if the CPU or the FPGA fails to be loaded, the corresponding loading process is executed again; and if the CPU or the FPGA is successfully loaded, the corresponding loading process does not need to be executed. According to the invention, rapid and reliable switching of multiple modes in different working states is realized, and the system continuity requirement in an extreme environment is met.

The selective three-mode redundancy method based on the improved KL algorithm can take into account the anti-SEU capability and the hardware overhead after redundancy, compared with the full three-mode redundancy method, the selective three-mode redundancy can save a large amount of additional overhead, and meanwhile, the circuit anti-single particle reliability requirement can be met.

The invention discloses a triple modular redundant DO system and a diagnosis method, and belongs to the field of process control. The system comprises a triple modular DO system, a first redundancy module, a second redundancy module and a third redundancy module, the first redundancy module comprises a switch AK and a switch AK1, the second redundancy module comprises a switch BK and a switch BK1, and the third redundancy module comprises a switch CK and a switch CK1. The invention supports the diagnosis of the switch and the control signal. According to the device applying the method, each module supports independent replacement, and a conditional 3-2.1. 0 degradation mode is supported. According to the scheme, high reliability of system operation is ensured, high availability is achieved, and therefore high use value is achieved.

This invention discloses a redundant architecture method for a UAV flight control system, relating to the field of UAV control technology. It includes redundant design for four layers: flight sensor system, redundant flight control computer system, bus communication system, and actuator system. The bus communication system employs a three-bus redundant architecture consisting of a 1553B dual-bus, FlexRay bus, and CAN bus. The redundant flight control computer system features automatic switching between three modes: triple-mode redundancy, dual-mode redundancy, and single-mode redundancy, and possesses online fault channel repair and reconnection capabilities. The actuator system includes aerodynamic control surface segment redundancy, servo electrical dual-path redundancy, and dual-path access redundancy via the CAN bus main path and RS422 backup path. This invention, using the aforementioned redundant architecture method for a UAV flight control system, achieves long-endurance, highly reliable flight control with no awareness of single faults, return capability in the event of dual faults, and no degradation due to bus faults.

The invention belongs to the technical field of computers, and provides a self-adaptive memory protection method and device for dynamically adjusting triple modular redundancy voting frequency, a management structural body is created and initialized for key data, and the management structural body comprises three data copy pointers and three data copies for managing the key data; monitoring system state parameters related to the key data in real time or periodically, wherein the system state parameters comprise a system load rate and a historical error rate of data inconsistency of the management structure body in historical voting; dynamically adjusting a voting frequency strategy for executing two-out-of-three voting operation on the three data copies according to the monitored system state parameters; and executing corresponding two-out-of-three voting operation on the three data copies according to the voting frequency strategy. According to the method, the voting frequency of triple modular redundancy can be dynamically adjusted according to the system load and the historical error rate, so that the system performance is remarkably optimized and the power consumption is reduced while the reliability of the memory is ensured.

The application discloses an anti-radiation three-mode redundant latch, and belongs to the field of anti-radiation design of special integrated circuits. The application designs a novel main-stage latch and a novel redundant voting circuit, which comprises a first transistor-stage voting circuit, a second transistor-stage voting circuit and a protection gate circuit. The application reinforces the main-stage latch and the voting circuit from the circuit structure, enhances the resistance of the main-stage latch to SNU and DNU, reduces the influence of SNU of the voting circuit itself on the output result, and enhances the stability of the three-mode redundant system. The total number of MOS tubes of the redundant voting circuit of the application is only 30% of the total number of MOS tubes of the full three-mode redundant voting circuit, effectively reduces the area cost of the three-mode redundant system, and is more suitable for the anti-radiation design of super large scale integrated circuits.

The present application relates to the technical field of embedded flash memory data reading, and discloses a read data path of an eFLASH controller and a functional safety design method of a read Cache, three groups of Datapath+Cache are arranged in the FLASH controller to realize three-mode redundancy and heterogeneous redundancy, and Cross modules are used to realize hierarchical redundancy and circuit recombination; a CPU realizes module configuration through an APB, and the CPU or other Master accesses a Flash Memory through AXI via the Cache and the Data_path. The read data path of the eFLASH controller and the functional safety design method of the read Cache realize three-mode redundancy, hierarchical redundancy and heterogeneous redundancy in combination, adopt hierarchical circuit recombination design, and adopt the functional safety design of the front four-stage register+inverter, so that the data path can be flexibly configured, the composite redundancy design of the read data path of the eFLASH controller and the read prefetch Cache is realized, the whole scheme is more reliable, more efficient and more flexible, the eFLASH reading efficiency can be effectively improved, and the functional safety requirement of the vehicle is met.

The invention provides a satellite-borne network operating system guarantee method based on double Flash, which comprises the following steps of: storing a boot program Uboot and a microsystem ONIE by adopting a main Flash memory and a standby Flash memory, and constructing a mirror image array to store a network operating system NOS; the guarantee method comprises the steps of dual-Flash partition planning, Uboot main and standby cooperation and single event effect repair, Uboot environment variable main and standby verification and repair, ONIE system main and standby backup and integrity verification and repair and SSD reliability guarantee and single event effect repair. And the purposes of low cost and high-reliability operation of the satellite-borne network operation system are achieved. The method can be mixed with a traditional triple-modular redundancy scheme for use, and can also be used as a standby reliability guarantee scheme after the triple-modular redundancy chip fails.

An exemplary fault-tolerant computing system includes a secondary processor configured to execute with a primary processor from a common program store in a delay lock-step manner, a comparator in a stored data and write-back path to detect a fault based on comparing a primary processor state and a secondary processor state, and allowing a write-back path delay that aborts execution when a fault is detected prior to write-back of invalid data. Auxiliary processor execution and main processor storage data and write back may be delayed by a predetermined number of cycles, allowing fault detection prior to writing invalid data. The storage data and write-back path may include a triple module redundancy configured to delay a level of most data only through the storage data and write-back path. Some embodiments may forward data from the storage data path delay stage to a write-back stage or memory if the load data address matches the address of data in the storage data path delay stage.

The invention belongs to the technical field of semiconductors and integrated circuits, and particularly relates to an agile soft error optimization method based on reinforcement learning. The method comprises the following steps: a data generation step: generating a large number of virtual circuit samples according to characteristics and design constraints of circuit reinforcement to obtain a high-quality data set for model training; a model training step: training the model by adopting a reinforcement learning algorithm, so that the model gradually learns a universal reinforcement strategy in the reinforcement process of a large number of virtual circuits; and a model deployment step: deploying the trained reinforcement learning model for circuit reinforcement reasoning, and for a to-be-reinforced circuit, rapidly predicting a design index by a system in a reasoning process based on an agent model so as to support an efficient reinforcement decision. The method has high expansibility, high efficiency and good universality, can be widely applied to fault-tolerant reinforcement design of various high-reliability circuit structures, such as triple modular redundancy and other schemes, and can meet the circuit soft error protection requirements under multiple scenes and multiple constraints.

This invention discloses a method and apparatus for detecting self-oscillation signals in FPGAs based on signal feedback loops. The method includes: first, reading the received FPGA hardware description language code file and integrating the various modules in the FPGA code to form a top-down overall code file; second, mapping the overall FPGA code file into a signal transmission network based on the transmission relationships between various signals in the overall code file; third, finding all signal feedback loops in the signal transmission network and calculating the signal feedback probability, selecting and recording signal feedback loops with a signal feedback probability greater than a set threshold, and extracting the signals in the signal feedback loops as self-oscillation signals for output. This invention can effectively detect self-oscillation signals and their occurrence probabilities in FPGA designs. It is simple to use, requires minimal investment, and can well meet the needs of self-oscillation signal detection when conducting triple-modular redundancy designs.