78 results about "Digital signal processor" patented technology

Technology is disclosed for an optical receiver. The optical receiver may include an optical and digital signal processing (ODSP) device. The ODSP device may include a photodiode operable to convert an optical signal to an electrical signal; a digital signal processor operable to generate a digital signal based on the electrical signal; a quantization component operable to generate a quantized output signal based on the digital signal; and a processing device. The processing device may be operable to measure one or more signal statistics of the digital signal; and identify one or more quantization thresholds, wherein the one or more quantization thresholds are computed based on the one or more signal statistics.

The invention relates to a method and an apparatus for improving the intelligibility of a group of persons engaged in conversation, each person in the group being able at times to be a speaker and at times to be a listener. The persons are situated at two or more positions P. For this purpose, a system (1) is used comprising: two or more directional microphones M which are directed towards the positions P; two or more directional loudspeakers L which are likewise directed towards the positions P; and a digital signal processor DSP which is capable of processing and forwarding acoustic signals in real time. Each microphone M continuously receives acoustic signals Ai and forwards them to the DSP. The DSP identifies, in real time, a speech signal Si1 from each acoustic signal Ai and generates therefrom a processed speech signal aSi1. The DSP transmits the processed speech signal aSi1 to one or more other loudspeakers L. The DSP detects later-arriving speech signals Si2, Si3 having the same characteristics as reflections of the speech signal Si1, and generates therefrom, in real time, processed reflected signals aSi2, aSi3, which the DSP transmits to another loudspeaker L within a predetermined time window (4) having a duration of at most 40 ms.

This invention provides a car seat headrest speaker, including a microcontroller, a digital signal processor, a power amplifier chip, and two pins. The power amplifier chip is connected to a speaker and the digital signal processor; the digital signal processor is connected to the microcontroller; and the microcontroller has a Bluetooth transceiver. The speaker is detachably connected to the car seat headrest. The two pins connect to the vehicle's infotainment system, through which the microcontroller receives CAN protocol signals and controls the Bluetooth transceiver to enter TWS pairing mode based on the CAN protocol signals. This invention achieves multi-scenario speaker use through a detachable design and utilizes physical pins to transmit CAN bus signals to activate TWS pairing, solving the problems of existing car audio systems being non-detachable and limited in use scenarios. While ensuring driving safety, it enhances the auditory immersion and interactive experience for drivers and passengers.

This invention discloses a method for porting a digital signal processor (DSP) assembler based on a processor architecture description, comprising the following steps: S1. Based on the processor architecture description, a lexical analysis and syntax analysis part of the assembler is constructed to realize the parsing of special assembly instructions; S2. Taking the parsed instruction data or instruction binary code as input, dynamic encoding and decoding of instructions are implemented according to the instruction definition, thereby realizing the conversion between the object file and the assembly file. This DSP assembler porting method further improves the performance of the assembler and automates the porting process, adapting it to the digital signal processor architecture. It also provides support for single instruction multiple data, very long instruction words, and instruction validity checks. While ensuring that the program execution result meets expectations, it greatly reduces the number of clock cycles required for execution, possesses universality, and meets the needs of rapid processor architecture updates.

This invention relates to a system and method for calibrating energy meters, designed to enhance the accuracy of electrical power measurements. The system incorporates a computing device with specialized calibration software, interfaced with multiple energy meters via a network switch. Each energy meter is equipped with a CPU and DSP, facilitating precise phase angle measurements. A configurable three-phase reference source, connected via power cables, supplies standard calibration signals to the meters. The DSP measures phase angles based on calibration commands triggered by control signals received by the CPU. These measurements are then transmitted to the computing device, which calculates necessary offset corrections. The corrections are subsequently communicated back to the CPU for adjustment of the energy meters' analog-to-digital converter settings, thereby ensuring the meters' outputs are accurately aligned with calibrated standards. This system provides a robust framework for reliable, high-precision energy meter calibration.

The utility model discloses a kind of multi-channel signal detection system and optical module, comprising: digital signal processor and control module;Digital signal processor includes: at least two signal level output ports;Control module includes at least two interrupt input interface and drain open circuit output interface;Wherein, signal level output port and interrupt input interface one-to-one correspondence;Each signal level output port is connected with corresponding interrupt input interface, for the output level of each signal level output port, as the input level of each interrupt input interface;Control module is used to according to the input level of each interrupt input interface, drain open circuit output interface exports instruction signal.So that control module can simultaneously according to the input level of received multiple interrupt input interface, drain open circuit output interface carries out the output of instruction signal, reduce the circuit complexity, so that multi-channel signal detection can be simultaneously supported, improve level response efficiency.

A device includes digital signal processors (DSPs) and analog crossbars in communication with the DSPs. The analog crossbars are operable to dynamically adjust equalization settings based on real-time feedback from DSPs, physical media-dependent (PMD) devices, or environmental sensors. Equalization adjustments optimize signal quality by compensating for traffic conditions, environmental changes, or signal degradation. The crossbars support predictive equalization using machine learning algorithms to preemptively adjust signal properties, ensuring performance across dynamic network environments. Diagnostics and logging capabilities monitor and refine equalization performance, while auxiliary in-band channels provide low-power pathways to reduce energy consumption. These features enable efficient, high-speed data transmission with enhanced reliability and adaptability in modern networking systems.

The application discloses a signal processing combination performance verification system based on DSP communication test, relates to the real-time test technical field of a digital signal processor, and specifically comprises: a homomorphism copying module, a slot injection module and a performance judgment module; the dynamic configuration parameters of a current DSP operation core are captured in real time through hardware sniffing of a bus, and the dynamic configuration parameters are mirrored to shadow registers; a peek unit is used to identify the bubble period of a pipeline through prediction logic; at the moment when the main computing unit is in a waiting period, the operation of the shadow register group is enabled by hardware, a preset characteristic test vector is input into a computing engine, and a shadow operation is completed; the real-time data flow of a main path and the reference data flow of a shadow path are compared in time domain and frequency domain by a hardware comparison array, the second derivative of a response time delay is calculated, a comprehensive performance factor is output, online verification of the combination performance of a DSP signal processing is realized, fault types can be accurately distinguished, and the reliability and maintainability of the system are improved.

A device includes a plurality of digital signal processors (DSPs) and analog crossbars in communication with the DSPs. The DSPs and crossbars dynamically adjust power consumption based on traffic load and / or a signal quality, leveraging traffic prediction models to optimize resource allocation. The system supports features such as powering down unused lanes, asymmetrically deactivating transmission or receiving lanes, and preemptively scaling resources during predicted traffic increases. Dynamic voltage and frequency scaling (DVFS) optimizes power usage based on link utilization and traffic priority, minimizing latency impacts during transitions. The switch controller integrates traffic prioritization algorithms, including weighted round-robin (WRR), to allocate power and bandwidth efficiently to high-priority traffic flows. Redundant crossbars handle overflow traffic or failover scenarios, transitioning between standby and active states dynamically.

According to one embodiment, a receiver device includes: a plurality of converters each configured to sample a digital value from an analog signal, each digital value being sampled at different timing; and a digital signal processor configured to calibrate offsets of the digital values. The plurality of converters include a first converter and a second converter. The digital signal processor is configured to: calibrate a first offset caused in the first converter and a second offset caused in the second converter, in a first operation using a first analog signal; and calibrate a third offset that is caused commonly in the first converter for which the first offset is calibrated and the second converter for which the second offset is calibrated, in a second operation using a second analog signal.

This invention provides a method and system for directional sound generation from a loudspeaker based on offline simulation and feedforward control, relating to the field of electroacoustic technology. The method includes: based on the feedforward compensation database, in the online implementation phase, performing frequency decomposition on the input audio signal using a digital signal processor and querying the database to obtain compensation parameters corresponding to each frequency component, thereby obtaining a real-time inverse compensation signal; using the real-time inverse compensation signal, synchronously driving the main loudspeaker and auxiliary loudspeaker, causing the compensated sound wave radiated by the auxiliary loudspeaker to destructively interfere with the sound wave behind the main loudspeaker, forming an acoustic quiet zone. This invention combines offline simulation to construct a precise database with online feedforward query for real-time compensation, ensuring accuracy and efficiency throughout the entire process from data foundation to acoustic quiet zone formation.

The present invention relates to the technical field of audio processing. Disclosed are a phase correction system and method for audio signals, and a device and a medium. The system comprises: an application processor, which is used for acquiring, for any microphone to be subjected to phase correction, a microphone identifier of said microphone, determining a microphone input pin identifier on the basis of the microphone identifier and a preset mapping relationship, and sending the microphone input pin identifier to a digital signal processor, wherein the preset mapping relationship is used for reflecting the correspondence between the microphone identifier and the corresponding microphone input pin identifier; and the digital signal processor, which is used for acquiring the microphone input pin identifier from the application processor, determining a storage space, where an audio signal picked up by the microphone corresponding to the microphone input pin identifier is located, and correcting the audio signal in the storage space. The system can complete phase correction of audio signals picked up by a microphone.

A multi-channel amplifier system for power supplies with specific power output ratings. The system includes first and second output channels, each containing a power amplifier, an adjustable voltage limiter, and an adjustable impedance circuit. A constraint controller with predefined partial power settings is able to adjust the voltage or impedance based on specific constraint patterns. Power distribution balance between output channels is regulated by a multi-contact switch. Real-time data of the output channels is acquired by a sensing system including temperature, current, and voltage sensors, allowing dynamic adjustments within predefined ranges. The system also integrates an input signal digital signal processor (DSP) compressor or limiter that works in conjunction with a microcontroller to limit audio signals based on specified thresholds. This innovative design enables efficient and adaptive power distribution without the need for a graphical user interface, making it ideal for various audio applications.

A system and method for an audio system for a vehicle comprises a main unit configured to communicate audio signals via at least one bus, wherein the at least one bus comprises a first master bus, the first master bus comprising a first plurality of nodes; a first master transceiver corresponding to a node of the first plurality of nodes; a control unit, the control unit being configured to generate control signals for coordinating at least some of the audio signals; a digital signal processor (DSP) associated with the control unit and the first master transceiver; and a second master transceiver corresponding to a starting node of a second plurality of nodes encompassed by a second master bus, the second plurality of nodes being connected to the first plurality of nodes via the node.

This application provides a digital signal processing device, communication equipment, and optical communication system, relating to the field of electronic technology, for improving the scalability of DSP chips and supporting product flexibility. The digital signal processing device includes at least one die, each die comprising: a digital signal processor, a switch, N first digital-to-analog converters, M second digital-to-analog converters, and a digital preprocessing circuit; N is a positive integer. The N output terminals of the digital signal processor are respectively connected to the N first terminals of the switch, and the N output terminals of the digital signal processor are also respectively connected to the N input terminals of the digital preprocessing circuit. The N first output terminals of the digital preprocessing circuit are respectively connected to the N second terminals of the switch, and the N second output terminals of the digital preprocessing circuit are respectively connected to the input terminals of the M second digital-to-analog converters. The N third terminals of the switch are respectively connected to the input terminals of the N first digital-to-analog converters.

The invention relates to a method for acoustic interaction between a vehicle and a user, wherein the vehicle, in response to an action (1) performed by the user, outputs a sound response (2) via acoustic output means, wherein the sound response (2) is artificially generated from the musical patterns inherent in a piece of music (3), which are identified by an analysis of the piece of music (3) using artificial intelligence. The method according to the invention is characterized in that - the piece of music (3) is analyzed by a processing cascade (4), comprising at least one interacting digital signal processor algorithm and a suitable pre-trained machine learning model, which divides the piece of music (3) into music snippets (5) corresponding to individual temporal sections of the piece of music (3), and assigns metadata (6) to the music snippets (5), describing music-characterizing properties of the respective music snippet (5); - the music snippets (5) are stored in a snippet database (7); - for various actions (1) that can be performed by the user, at least one sound response blueprint (8) is provided, containing a metadata specification; - the sound response blueprints (8) are applied to the music snippets (5) stored in the snippet database (7), whereby for each sound response (2) at least one music scheme is generated from at least one music snippet (5) depending on the metadata specification in order to generate the sound response (2) for the respective action (1); and - a corresponding sound response (2) is emitted when performing a respective action (1).

A device includes a plurality of digital signal processors (DSPs), analog crossbars in communication with the DSPs, and a switch controller. The switch controller facilitates control signals using in-band signaling within payload traffic or out-of-band signaling over a dedicated management interface. The system supports dynamic traffic prioritization based on real-time metrics, such as latency and traffic load, ensuring efficient resource allocation and seamless operation during congestion or reconfiguration. Redundant crossbars and failover mechanisms enhance fault tolerance, while granular backpressure selectively throttles traffic flows to prevent bottlenecks. Integrated diagnostic tools monitor performance and optimize traffic flow, enabling high-speed and reliable communication.

The present invention addresses the need to implement a side rearview mirror monitoring system that detects malfunctions caused by temperature changes, vibrations, and impacts. A side rearview mirror monitoring system is provided, comprising fiber optic sensors integrated into the rearview mirror assembly and connected to the Door Control Module (DCU).The DCU unit comprises at least the following elements: a) an optical interferometer that measures the light wave reflected by the fiber optic sensors located inside each side rearview mirror; b) a digital signal processor (DSP), whose main characteristic is the processing of digital signals at the physical level; and c) a reference fiber optic section, which is a segment or section of the fiber optic sensor embedded and sealed with epoxy paste inside the DCU module to prevent movement. Once the temperature, pressure, and vibration data is collected and processed, the system can use this information to correct errors in the position of the side rearview mirrors or detect impacts to them. If these events occur, a signal can be sent to the DCU module's actuator to fold the exterior mirror to prevent damage and / or adjust its position.In addition, the system can also send notifications regarding the operation of the rearview mirrors to the BCM module via a vehicle's CAN bus.

Systems and methods for seamless network communication reconfiguration, comprising a device that includes physical media dependent (PMD) devices, incorporating a digital signal processor (DSP) configured to handle both in-band and out-of-band communication traffic, a plurality of primary analog crossbars connected to the DSPs for routing operational data, and a set of redundant analog crossbars configured to establish auxiliary communication channels. The system includes a controller operable to dynamically activate the auxiliary communication channels during reconfiguration events, enabling a make-before-break protocol by transitioning traffic from primary channels to auxiliary channels. The redundant crossbars support out-of-band signaling to coordinate transitions and maintain system integrity. The auxiliary channels remain in a low-power state during steady operation, ensuring resource efficiency, while the controller monitors signal integrity and initiates reconfiguration upon detecting a fault or network event, maintaining uninterrupted traffic flow.

Disclosed is an integrated circuit (100) comprising a specific digital signal processor (DSP) (111) with an associated arithmetic logic unit (ALU) (112), and a dedicated safety device (120) for continuously monitoring the functional safety of this specific digital signal processor (111). The digital signal processor (111) triggers a predetermined safety mechanism (121), which causes the ALU (112) to execute one or more predefined test operations. The test results obtained are stored in a test result register (130). At specific times, the safety device (120) reads the contents of the test result register (130) and compares the contents with a predefined correct test result. In case of a deviation, an error message is generated.

The application discloses a matrix multiplication processing method and device for a digital signal processor and a medium, and relates to the field of vector processors. In the method, before a matrix multiplication operation is performed, a first matrix is stored in an array memory, and a second matrix and a third matrix are stored in a global shared storage, so that the first matrix is read only once when the matrix multiplication operation is performed, and the second matrix and the third matrix are shared by multiple cores, so that the memory access amount of the digital signal processor is low, and the bandwidth pressure of a double-rate synchronous dynamic random access memory is reduced. In addition, the application further provides a matrix multiplication processing device for a digital signal processor and a computer readable storage medium, which have the same or corresponding technical features and effects as the above-mentioned matrix multiplication processing method for a digital signal processor.

The application relates to the field of communication technology and discloses a programmable switch user call communication method and system, which comprises the following steps: acquiring an actual processing time interval of a digital signal processor in a programmable switch for voice data packets, determining a processing deviation of the digital signal processor based on the actual processing time interval, analyzing the processing deviation to determine whether the digital signal processor is in a performance decline mode, adjusting a routing priority of the digital signal processor if it is determined that the digital signal processor is in the performance decline mode, receiving a new call request, and allocating a digital signal processor for the new call request according to the real-time routing priority of the digital signal processor. The application combines real-time performance monitoring and dynamic resource scheduling, so that the whole system can better adapt to complex and changeable operation environments and improve the reliability of long-term operation.

This application provides an improved SAR analog-to-digital conversion method and system, belonging to the field of analog-to-digital conversion technology. The method includes: a successive approximation analog-to-digital converter, a multi-slope integrator, a time-to-digital converter, and a digital signal processor. The successive approximation analog-to-digital converter converts the input analog signal to obtain a first digital code and a residual voltage. The multi-slope integrator converts the residual voltage to obtain a time signal corresponding to the residual voltage. The time-to-digital converter counts the time signal to obtain a second digital code. The digital signal processor concatenates the first and second digital codes to obtain a digital signal corresponding to the analog signal. The improved SAR analog-to-digital conversion method and system provided by this application can meet the needs of high-precision measurement scenarios.

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for determining a bounding box for geometric correction. A bounding box engine may obtain an indication of a set of reprojection distortions. The bounding box engine may obtain an indication of a set of bounding box instructions. The bounding box engine may obtain either indication from at least one of a central processing unit (CPU) or a digital signal processor (DSP). The bounding box engine may determine a bounding box based on the set of reprojection distortions and the set of bounding box instructions. The bounding box engine may output an indication of the determined bounding box. The bounding box engine may output the indication to at least one of a graphics processing unit (GPU) or a geometric correction engine.

This invention discloses an instruction stacking execution method and a digital signal processor. The method includes the following steps: First, executing a stacked instruction containing an immediate value in the program running on the DSP core; second, during the decoding of the instruction, identifying and marking multiple subsequent instructions as a stack group based on its immediate value; finally, triggering the stacked execution mode, scheduling the instructions within the stack group within a single DSP core, so that their fetch, decode, and execute operations overlap in time. This invention effectively improves the execution efficiency of a single-core DSP for multi-cycle instructions by flexibly triggering the pipeline parallelism of multiple instructions with a single instruction, solving the problem of fixed parallel instructions and inability to adapt to flexible parallel scheduling of batch instructions in existing technologies.

An apparatus and method for a receiver configured to perform timing recovery decoupling feedforward equalizer (FFE) adaptation. The receiver apparatus may include an analog front-end (AFE) device coupled to a time-interleaving (TI) interface. The TI interface is coupled in a timing recovery feedback loop to an FFE equalizer, a digital signal processor (DSP), a delay-timing loop (DTL) device, and a clock device, with the clock device feeding back to the TI interface. The DSP has an additional path to the FFE equalizer, which in turn has an additional path to the DTL device. The DTL loop is equipped with an interleaving-specific enable / disable vector Q[1:N] that can enable / disable the contribution of specific time-interleaving errors to the timing recovery loop, allowing the FFE adaptation process to be decoupled from the timing recovery loop.

A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

This invention relates to the field of automotive ball joints, and provides an intelligent ball joint based on optical tracking, comprising a ball pin, a ball pin seat, and a ball pin sleeve, and further comprising: a light source assembly that projects light onto the underside of the ball head of the ball pin; an optical tracking system built into the end of the ball head; the optical tracking system including an optical tracking sensor, which integrates an image acquisition system and a digital signal processor; the image acquisition system converting the received light signal into a digital image signal; and the digital signal processor comparing and analyzing consecutive frames of digital image signals to determine the type, direction, and position of the ball pin relative to the ball pin sleeve, and generating a corresponding motion state signal for output. The intelligent ball joint based on optical tracking described in this invention can simultaneously measure oscillation, rotation, and micro-displacement, accurately identify and provide real-time feedback on the relative motion relationship between the ball pin and the ball pin sleeve; and has strong anti-interference capabilities during the measurement process.