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8871 results about "Digital signal processor" patented technology

A digital signal processor (DSP) is a specialized microprocessor (or a SIP block), with its architecture optimized for the operational needs of digital signal processing. The goal of DSP is usually to measure, filter or compress continuous real-world analog signals. Most general-purpose microprocessors can also execute digital signal processing algorithms successfully, but may not be able to keep up with such processing continuously in real-time. Also, dedicated DSPs usually have better power efficiency, thus they are more suitable in portable devices such as mobile phones because of power consumption constraints. DSPs often use special memory architectures that are able to fetch multiple data or instructions at the same time.

Method of enhancing sound for hearing impaired individuals

A portable assistive listening system for enhancing sound for hearing impaired individuals includes a fully functional hearing aid and a separate handheld digital signal processing (DSP) device. The focus of the present invention is directed to the handheld DSP device and a unique method of processing incoming audio signals. The DSP device includes a programmable digital signal processor, a UWB transceiver for communicating with the hearing aid and/or other wireless audio sources, an LCD display, and a user input device (keypad). The handheld device is user programmable to apply different sound enhancement algorithms for enhancing sound signals received from the hearing aid and/or other audio source. The handheld device is capable of receiving audio signals from multiple sources, and gives the user control over selection of incoming sound sources and selective enhancement of sound. In the context of being user programmable, the digital signal processing device includes a software platform that provides for the ability of the user to select, or plug-in, desired enhancement algorithms for application to selected incoming audio signals. Specifically, the invention focuses on a method of buffering an incoming audio signal, and selectively replaying the buffered audio. The method further includes converting the replayed audio signal to text for display on the handheld DSP device.
Owner:BIONICA CORP

Microprocessors

A processor (100) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit (106), a program flow control unit (108), an address / data flow unit (110), a data computation unit (112), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit (104) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.
Owner:TEXAS INSTR INC

Assistive listening system with plug in enhancement platform and communication port to download user preferred processing algorithms

A portable assistive listening system for enhancing sound for hearing impaired individuals includes a fully functional hearing aid and a separate handheld digital signal processing (DSP) device. The focus of the present invention is directed to the handheld DSP device. The DSP device includes a programmable digital signal processor, a UWB transceiver for communicating with the hearing aid and/or other wireless audio sources, an LCD display, and a user input device (keypad). The handheld device is user programmable to apply different processing algorithms for processing sound signals received from the hearing aid or other audio source. The handheld device is capable of receiving audio signals from multiple sources, and gives the user control over selection of incoming sources and selective processing of sound. In the context of being user programmable, the digital signal processing device includes a software platform that provides for the ability of the user to select or “plug-in” desired processing algorithms for application to selected incoming audio channels and a communication port for the user to connect to a PC or other device to download preferred processing algorithms. The communication port provides the user with the ability to retrieve desirable processing algorithms from a database of available algorithms and download those algorithms directly into the device for use.
Owner:BIONICA CORP

Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system

InactiveUS7002591B1Efficient implementationIncrease in texture mapping hardware complexityCathode-ray tube indicators3D-image renderingPattern recognitionProcessing
A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics pipeline renders and prepares images for display at least in part in response to polygon vertex attribute data and texel color data stored as a texture images in an associated memory. An efficient texturing pipeline arrangement achieves a relatively low chip-footprint by utilizing a single texture coordinate / data processing unit that interleaves the processing of logical direct and indirect texture coordinate data and a texture lookup data feedback path for “recirculating” indirect texture lookup data retrieved from a single texture retrieval unit back to the texture coordinate / data processing unit. Versatile indirect texture referencing is achieved by using the same texture coordinate / data processing unit to transform the recirculated texture lookup data into offsets that may be added to the texture coordinates of a direct texture lookup. A generalized indirect texture API function is provided that supports defining at least four indirect texture referencing operations and allows for selectively associating one of at least eight different texture images with each indirect texture defined. Retrieved indirect texture lookup data is processed as multi-bit binary data triplets of three, four, five, or eight bits. The data triplets are multiplied by a 3×2 texture coordinate offset matrix before being optionally combined with regular non-indirect coordinate data or coordinate data from a previous cycle / stage of processing. Values of the offset matrix elements are variable and may be dynamically defined for each cycle / stage using selected constants. Two additional variable matrix configurations are also defined containing element values obtained from current direct texture coordinates. Circuitry for optionally biasing and scaling retrieved texture data is also provided.
Owner:NINTENDO CO LTD

Method for personalized television voice wake-up by voiceprint and voice identification

The invention discloses a method for personalized television voice wake-up by voiceprint and voice identification, particularly a method for performing identity confirmation on a television user through voiceprint identification and controlling a television to perform personalized voice wake-up through confirmed identity and a voice identification result of user voice, and relates to voiceprint identification and voice identification technologies. A composition system comprises a voice control system (1), an information storage unit (2) and a television main controller (3) which are connected through electric signals. The method has the characteristics of short training time, very high voiceprint and voice identification speed and high identification rate. Voiceprint and voice identification can be finished by only offline training and testing, identification results do not need to be sent to a cloud server, use is convenient, and the safety of family information is guaranteed. The method also can be applied to user-personalized automatic voice channel change of the television, can be transplanted to a common high-speed DSP (digital signal processor) or chip for operation, and can be widely applied to the related fields of smart homes.
Owner:SHANGHAI NORMAL UNIVERSITY

Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction

A digital data processor integrated circuit (1) includes a plurality of functionally identical first processor elements (6A) and a second processor element (5). The first processor elements are bidirectionally coupled to a first cache (12) via a crossbar switch matrix (8). The second processor element is coupled to a second cache (11). Each of the first cache and the second cache contain a two-way, set-associative cache memory that uses a least-recently-used (LRU) replacement algorithm and that operates with a use-as-fill mode to minimize a number of wait states said processor elements need experience before continuing execution after a cache-miss. An operation of each of the first processor elements and an operation of the second processor element are locked together during an execution of a single instruction read from the second cache. The instruction specifies, in a first portion that is coupled in common to each of the plurality of first processor elements, the operation of each of the plurality of first processor elements in parallel. A second portion of the instruction specifies the operation of the second processor element. Also included is a motion estimator (7) and an internal data bus coupling together a first parallel port (3A), a second parallel port (3B), a third parallel port (3C), an external memory interface (2), and a data input/output of the first cache and the second cache.
Owner:CUFER ASSET LTD LLC
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