4 results about "Code density" patented technology

The invention provides a database storage link performance optimization method which can be applied to the technical field of computer system software performance optimization. The method comprises the steps of performing compression and reconstruction on an original instruction sequence of a structured query language parser in a database storage link based on instruction compression and expansion provided by a reduced instruction set processor platform, and generating an optimized instruction sequence with higher code density; based on a memory management attribute of a reduced instruction set processor platform and a layout control function of a compiling linker, performing aggregation layout optimization on a physical storage position of an instruction code of a core storage management function in a database storage link in a processor instruction cache; based on single-instruction multi-data stream extension provided by a reduced instruction set processor platform, key operations related to batch data access and processing in a database storage link execution process are converted from a scalar execution mode to a vectorization execution mode.

The invention discloses a high-linearity self-adaptive delay chain type TDC based on an FPGA. The high-linearity self-adaptive delay chain type TDC comprises a signal conversion module and a linear compensation module, wherein the signal conversion module is arranged between an IDELAY delay module and a delay chain module; the linear compensation module is arranged between a code density calibration module and a data storage module; the IDELAY delay module is used for carrying out segmentation processing on a system clock and generating six paths of single-edge delay signals with fixed rising edge time intervals; the signal conversion module is used for carrying out time sequence conversion on the six paths of single-edge delay signals and outputting three paths of double-edge signals, and the time interval of adjacent rising edges is fixed; and the linear compensation module is used for calculating the standard resolution before linear compensation and then combining the small delay units of the delay time into the large delay units of the delay time, and N is a linear compensation coefficient so as to convert the code density data with relatively low linearity into the code density data with high linearity. The TDC architecture has high linearity, strong environmental adaptability and cross-platform portability, and meets the application requirements of a high-precision time measurement scene.

This application relates to a code density calibration method and system based on dark counting. The method includes: setting a SPAD in Geiger mode under no-light conditions; generating a Poisson-distributed dark counting pulse unrelated to the TDC clock using thermal perturbation; using this pulse as a trigger signal to acquire and convert raw code during non-measurement periods / independent channels; recording the frequency of each unit using a counter array; calculating the total number of samples and the system period; calculating the calibration results of each unit, as well as differential and integral nonlinear indices; calculating the correction time value based on the indices; storing the calibration time in on-chip storage using the raw code as an index; constructing a calibration lookup table; during actual detection, using the raw code to address and look up the table, reading the calibration time and combining it with the coarse count to synthesize a high-precision result. This method can improve the measurement accuracy, stability, and environmental adaptability of a high-precision time-to-digital converter.

The application discloses a time-to-digital converter applied to a time-of-flight sensor, which adopts a tapped delay chain, a flip-flop array, a thermometer-to-binary (T2B) decoder and a code density calibration circuit to form a fine clock counting circuit, and cooperates with a coarse clock counter to perform time measurement on a to-be-measured signal; the tapped delay chain is adopted in the fine clock counting circuit, the observation points are set by taps, a bubble-free sub thermometer code is found through the observation points, the change boundary position of the tap state in the original thermometer code is observed and searched by means of the bubble-free sub thermometer code, the number of the tap state being 1 in the latched tapped delay chain is found out, accurate binary decoding is realized, and the bubble problem interference is eliminated. The TDC system design of the single chain, the 4-chain and the PSDL capable of completing online code density calibration is realized by using the application scheme, the measurement precision test is performed on the three kinds of TDC, and the measurement precision of the three kinds of TDC systems on the TOF sensor is optimized to different degrees.