55 results about "Code density" patented technology

A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.

The invention discloses a colorful two-dimension code, a generating method and generating system thereof and a printed article. The colorful two-dimension code is printed on the printed article, and the system comprises an original two-dimension code generating module, a dot matrix code generating module and an overlaying module. The method comprises the steps that S1, an original two-dimension code is generated on the basis of first target article information, and part of or all areas of the original two-dimension code are filled with colors; S2, a dot matrix code is generated on the basis of second target article information; S3, the dot matrix code is overlaid to the part or all the areas of the original two-dimension code, filled with the colors, so that the colorful two-dimension code is generated. The generated colorful two-dimension code is large in coding density, and high in decoding difficulty and imitation difficulty.

A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.

The invention discloses a structured light coding method and a related device. The structured light coding method includes the first step of generating a first coding pattern through a pseudo-random code, wherein coding elements in the first coding pattern are distinguished through at least color graphs in four colors and at least one geometric graph, the second step of projecting the first coding pattern onto the surface of a measured object, the third step of obtaining a second coding pattern formed after the first coding pattern and the surface of the measured object are overlapped, the fourth step of determining a feature point set on the second coding pattern, the fifth step of determining the corresponding position of each feature point in the feature point set in the first coding pattern, and the sixth step of calculating the depth of each feature point in the feature point set in the second coding pattern according to the position of each feature point in the feature point set in the first coding pattern and finally determining three-dimensional contour information of the measured object. Through the technical scheme of the method, on the premise that the coding density is ensured, the success rate of decoding is effectively increased.

A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques.

A scaleable microprocessor architecture has an efficient and orthogonal instruction set of 20 basic instructions, and a scaleable program word size from 15 bits up, including but not limited to 16, 24, 32, and 64 bits. As many instructions are packed into a single program word as allowed by the size of a program word. An integral return stack is used for nested subroutine calls and returns. An integral data stack is also used to pass parameters among nested subroutines. The simplified instruction set and the dual stack architecture make it possible to execute all instructions in a single clock cycle from a single phase master clock. Additional instructions can be added to facilitate accessing arrays in memory, for multiplication and division of integers, for real time interrupts, and to support an UART I/O device. This scaleable microprocessor architecture greatly increases code density and processing speed while decreasing significantly silicon area and power consumption. It is most suitable to serve as microprocessor cores in System-on-a-Chip (SOC) integrated circuits.

A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.

An input signal is compared to 2N - 1 reference voltages to generate 2N - 1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.

Embodiments of a method and system for compiling code, such as program-generated code, are disclosed herein. The method and system efficiently encode combined range and stride checks. For example, the method and system are operable to encode combined range and stride checks as they occur in a translation of switch statements. The method and system can generate code to perform the range and stride check, and to branch to the case body, if the range and stride checks are successful. The various embodiments may operate to provide an efficient code transformation, better code density, and processing performance. Other embodiments are described and claimed.

The invention discloses a method for allocating registers for a mixed length instruction set. By less revising the conventional graph coloring register allocation method, namely fully utilizing the characteristics of a mixed coding instruction set, codes with higher code density are generated. The method has the characteristics of simplicity, practicability and high in reliability.

A bar gauge by grading coding relates to the technical field of measuring instrument. According to the invention, the technical problem of high difficulty of present bar gauge identification is solved. Scale of the bar gauge provided by the invention is equally divided into a plurality of code segments. Each code segment is divided into a plurality of code words. Each code word is equally dividedinto D code element, A code element and B code element. The distances between centers of adjacent code elements are consistent. The D code element has a plurality of code bars, which are centrosymmetrically distributed to form a code segment counter. There is only one code bar at the center of the A code element and the B code element. The A code element and the B code element form a code word counter. The center line of the D code element is the start point of code words as well as the stop point of the front code word. There are a plurality of code bars in the D code element. Code segment counter values in the same code segment are consistent and convenient to identify. The bar gauge provided by the invention is characterized by few combinations of code elements and low bar code density. Wide-range levelling can be realized by using few combinations of code elements. Good conditions are created for long-distance measurement of barcode positioning, and measurement reliability is raised.

This invention relates to a method for decreasing LCD display distortion. Wherein, changing the forced voltage on liquid crystal ends to control the LCD; taking gamma conversion to the image signal by the front circuit to provide control voltage, controlling the conversion to set lower/higher code density on slow/serious varying interval respectively, and expressing the bit length from n into n+2; applying one DA circuit of n+2 bit on back of the gamma conversion. This invention saves much cost with almost same display effect.

A binary translation stack operation accelerated processing method includes a stack data loading instruction and a stack data storage instruction, the two instructions finish reading, writing, modification of a stack pointer, inspection of stack boarder crossing and processing of stack boarder crossing on the basis of a stack boarder universal register, a stack pointer universal register, a stack boarder crossing transfer address universal register, a source universal register set and a target universal register set, and finish updating of the state of a processor according to whether stack access crosses the boarder or not. The invention provides the binary translation stack operation accelerated processor. On the situation that it is guaranteed that hardware resources are unchanged, binary translation system performance and code density are greatly improved.

A device for generating a floating point constant comprises a decoding unit and a floating point constant generating unit. The decoding unit is used for decoding a floating point instruction to generate an instruction indication symbol and an m-bit binary immediate value. The floating point constant generating unit is used for receiving information of the decoding unit to perform logic operation on the m-bit binary immediate value, wherein the m-bit binary immediate value comprises two domains, namely a 1-bit first bit domain and a (m-1)-bit second bit domain, the first bit domain in the m-bit binary immediate value is extracted to generate a symbol field of the floating point constant, the second bit domain in the m-bit binary immediate value is extracted and serves as a fixed-point number with a fixed scaling position to be processed to generate a mantissa field and an index field of the floating point constant, the symbol field, the index field and the mantissa field are packaged into the n-bit floating point constant jointly, and the n is an integer. The invention further discloses a method for generating the floating point constant. By the device and the method, execution efficiency is improved effectively, and code density is reduced.

An VLIW instruction mechanism is described which accesses multiple slot instructions for execution to achieve high levels of selectable parallelism and to make improvements to code density. To this end, the VLIW instruction mechanism includes a short instruction word (SIW) register for holding an SIW. The SIW includes an indication of a slot instruction to execute and a dynamic slot instruction operand which is used by the slot instruction to execute. Further, the VLIW instruction mechanism includes a register for holding slot instructions which are retrieved from VLIW memory. The retrieved slot instructions include a stored operand which is used when executing the retrieved slot instruction. The VLIW instruction mechanism further includes a controller and an execution unit. The controller selects which of the operands are utilized with the retrieved slot instructions. The execution unit executes the retrieved slot instruction with the selected operand.

The invention relates to a calibration method and a calibration system. The calibration method is suitable for a successive approximation analog-digital converter, and the successive approximation analog-digital converter comprises a capacitor array. The calibration method comprises the following steps: inputting an input signal into the analog-digital converter, wherein the analog-digital converter generates an output signal according to the input signal, and the output signal comprises a plurality of specific digital codes; calculating respective average code densities of a plurality of digital code groups in the plurality of specific digital codes, wherein each digital code group comprises one or more specific digital codes in the plurality of specific digital codes; comparing the average code density of a first target group in the plurality of digital code groups with a first reference code density to generate a first comparison result; and calibrating the capacitance value of a first capacitor unit to be calibrated of the capacitor array according to the first comparison result. The calibration method can be used for calibrating the successive approximation analog-digital converter in real time.

The invention relates to an instruction processing method and a processor, and the method comprises the steps of dividing 16 universal registers equally into two groups, defining one group as an address register, and defining the other group as an integer register, wherein the address register is used for storing a memory address, and the integer register is used for storing integer data; when a specific instruction is parsed, respectively using 3bit operands for pointing to the address register or the integer register which is used as a source register or a target register. According to the present invention, on the basis of hardly influencing the flexibility and high efficiency of an instruction set, the bit number used by the instruction set can be reduced, so that the 16bits compressedinstruction set can accommodate more functions, the effect of using less 32-bit instructions or not using 32-bit instructions in a mixed manner is achieved, and the code density and the execution efficiency are further improved.

The invention discloses a memory which comprises an on-chip program area and an on-chip data area that are arranged for a normal working mode, an on-chip program area and on-chip data area exchange enable pin, an on-chip address encoder or an address arbiter module, a first selector, and a second selector, wherein the on-chip program area and on-chip data area exchange enable pin provides an enable signal for exchanging the on-chip program area and the on-chip data area; the on-chip address encoder or the address arbiter module receives the enable signal, and outputs a program area bus accessing to the on-chip program area, and a data area bus accessing to the on-chip data area; the first selector is provided with a selection end for receiving the enable signal, an input end for receiving the program area bus, an input end for receiving the data area bus, and an output end connected with the on-chip program area; and the second selector is provided with a selection end for receiving the enable signal, an input end for receiving the program area bus, an input end for receiving the data area bus, and an output end connected with the on-chip data area. The memory has the advantages of flexible testing, high client code density, and the like. The invention further discloses a memorizing method of the memory.

The invention discloses a code density high-order harmonic calibration system based on FFT extraction. The system comprises an analog to digital converter, an operation unit for extracting high-order harmonic distortion information, modeling unit for extracting and modeling code density information of a calibration signal, and a lookup table. The analog to digital converter is used for converting an input analog signal into a digital signal. The operation unit is used for obtaining a time domain signal required for calibration of three-order distortion. The modeling unit is used for modeling the code density information of the calibration signal, thereby obtaining code density calibration configuration information. The code density calibration configuration information is stored in the lookup table. The lookup table is used for carrying out data calibration processing on the digital signal according to the code density calibration configuration information stored in the lookup table. According to the code density high-order harmonic calibration system based on FFT extraction, corresponding high-order harmonic can be effectively suppressed in a high bandwidth, so the frequency response of a whole information system can be improved.